Instructor: Prof. Chung-Kuan, Cheng
CSE Dept. UCSD
“Principles and Practices of Interconnection
Networks” by W. Dally et al.
“High Speed Signal Propagation: Advanced
Black Magic” by H. Johnson et al.
Appendix E of “Interconnection Networks,
Computer Architecture: A Quantitative
Approach”(4th edition) by Hennessy et al.
Help on lecture slides: 15%
Interconnection Network Design: 45%
Subject study: 40%
Class participation: 5% bonus
Technology advancement: Performance bottleneck
shifts from processor to interconnects
In the past: for communication between cities.
Now: for communication between cabinets, or for
Distortionless transmission line:
No need for pre-emphasis or equalization.
Moore’s Law: increment of system density and
System integration: array of processors.
Memory wall: maximize bandwidth, minimize
Interface: limit of number of pins.
Communication becomes bottleneck of performance
Internet search engines
Computational intensive applications:
Bioengineering: protein and genome
Medical applications: MRI, EKG, MKG
To link processors, memory banks, disks
Objective function and constraints:
Minimize power consumption
Volume and cost constraints
Easy to repair
About volume constraint
For chip, board and mid-plane under
I/O pins and wires have volume.
Estimate number of I/O pins and wires.
Where is the problem?
Formulation is hard:
We need to build a machine for the year 2010.
We don’t know the state of the art technology at
Huge design space
non-overlapping -> communication latency
Where is the problem (cont’d)
Parallel processing and distributed
Competition of resources
Delay of feedback