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99/59.203/Alb
MASSEY UNIVERSITY
ALBANY CAMPUS
EXAMINATION FOR 59.203 COMPUTER SYSTEMS
Semester 1 - 1999
Time Allowed: THREE (3) hours
ANSWER ALL QUESTIONS.
Please wait until you are instructed to open this exam paper.
Turn over to p.2, etc...
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Question_1
(a) Give the truth table for an Exclusive OR gate. Draw the Exclusive OR gate and show how it
can be controlled to give an inverting or non-inverting output. [ 2 marks]
(b) Given the Boolean expression: X = AE + ŪE
Draw the logic circuit of the above expression and then show, using DeMorgan's theorem,
that it is equivalent to the expression: X = ĀU + Ē [ 3 marks]
(c) Draw a circuit for a four bit shift register using Edge triggered D-Type flip-flops. The circuit
is to be driven by a 1Hz clock and has [0] as a permanent input. [ 3 marks]
(d) If the initial Q values of the above shift register are [0110], what would be the Q values after
two cycles of the clock, and what would be the Q values after two cycles of the clock if level
triggered instead of edge triggered devices were used? [ 2 marks]
(e) You are required to link FOUR, non tri-state devices, onto a single data bus. Two of the
devices, D0 and D1, are Read Only, the other two, D2 and D3 are Write Only. You are given
two select lines S0, S1, and two control lines Read and Write (RD and WR).
Draw a block diagram showing how you would attach the devices to the data bus, how they
can be selected individually, and the use of the RD and WR control lines.
Use components from the following list for your design.
Buffers, latches, tri-state buffers, multiplexors, decoders, flip-flops.
[ 5 marks]
Turn over to p.3, etc...
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Question_2
HFull 50 gallon
Header Tank
HEmpt
5,000 gallon
water tank
HOUSE
Alarm A-Control
5KEmpt
PUMP P-Control
Above is the block diagram of the water system for a house, which has a 5,000 gallon
reservoir, and a header tank to give water pressure. A controller is required which will
monitor the water levels of the header (HFull and HEmpt) and the level of the reservoir
(5KEmpt).
If the reservoir empty signal is asserted this means only 100 gallons of water are left and a
warning lamp lights. If the header tank is empty and there is sufficient water in the reservoir
then the pump is switched on until the header tank is full.
For the controller of the above water system:
(a) Draw an ASM chart.
[ 3 marks]
(b) Give Boolean expressions for the states.
[ 2 marks]
(c) Design a circuit, including the output signals.
[ 5 marks]
(d) Now consider that your system has been recreated using a microcontroller. Write the
software in 2051 Assembler code which will control the above water system, assuming the
following:
Port_1 is an input with P1.0 = 5KEmpt, P1.1 = HFull, P1.2 = HEmpt......... ([1] = input true)
Port_3 is an output with P3.0 = P-Control, P3.1 = A-Control......... ([1] = on)
Information about the 2051 instruction set can be found in tables at the end of the paper.
[ 7 marks]
Turn over to p.4, etc...
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Question_3
Pico-computer architecture
WEMEM
Bus OEMEM
OEPC OECONST OEACC OEPORT
Tristate Tristate Tristate Tristate
buffer buffer buffer buffer Memory
Program INCPC L D A C CA c c u m u l a t o r
counter LDPC Input Port
CO/C1
const
mux
zero EQZ
detect
Arithmetic
Logic Unit
1 0
xor sub
LDABR A Buffer LDMAR Memory
Register invertor Address
Register
(a) Describe how machine instructions are implemented on the Pico-computer, using the
STA OPERAND instruction as an example, to illustrate your answer.
[ 5 marks]
(b) Describe in general terms how you would implement a new instruction ADD IMMEDIATE,
where the value after the instruction is added into the Accumulator.
[ 5 marks]
Turn over to p.5, etc...
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Question_4
Information about the 2051 instruction set can be found in tables at the end of the paper.
(a) Write a program, in 2051 assembler, that will convert a string of hexadecimal data bytes into
their ASCII equivalents.
The data string is located in addresses 40h to 4Fh inclusive. The ASCII equivalents are to
replace the initial hexadecimal numbers.
eg if location 40h contains 06h it will be replaced by 36h, if it contains 0Bh it will be
replaced by 42h.
(0 - 9 ≡ 30h - 39h, A - F ≡ 41h - 46h)
[ 6 marks for programming]
[ 2 marks for useful comments]
[ 2 marks for using a looping structure]
(b) Bits RS0 and RS1 in the PSW are used to select the current register bank. Discuss briefly
how register banks can be used to associate separate data with separate tasks, say in an
interrupt driven program. Use a minimum sized interrupt routine (just a few lines) as an
example for your discussion.
[ 4 marks]
(c) Write a piece of 2051 assembler code to enable interrupts from timer T0 after a Reset.
[ 2 marks]
Question_5
(a) Given that Differential Phase Modulation is being used with a clock speed of 1800cps. What
will be the baud rate? [ 1 mark]
(b) What will be the phase differentiation, in degrees, if a transmission rate of 3600 bps is to be
achieved in (a)? [ 1 mark]
(c) Draw the Constellation chart associated with sending THREE bits per baud using both phase
AND amplitude modulation.
[ 2 marks]
(d) Explain briefly the process of Frequency Shift Keying, and hence show the waveform for the
data [1001].
[ 3 marks]
(e) Given that a = 1, b = 2, c = 3 describe how Lempel-Ziv encoding is used to compress the
character string aabcabaa. Show the code table that is generated by this process, and finally
the code to be sent.
[ 5 marks]
+++++++++++
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99/59.203/Alb
AT89C2051 Reference
Program Memory: Data Memory:
07FFH
7FH
2FH
Serial P0 0 2 3 H
ort Bit-addressable
space (0-7F)
T i m e r 10 0 1 B H 20H
I n t e r r u p tE x t I n t 0 1 1 3 H 1FH
Locations
0
Bank 1 1{ 1 8 H
T i m e r 00 0 0 B H S e l e c t 1 0{ 1 0 H 1 7 H4 banks of
registers
bits in 0 F HR0 - R7
Ext I n t 00 0 3 H
0 PSW 0 1{ 0 8 H
RESET 0000H 0 0{ 0 0 H 07H
Reset value of
Stack Pointer
Program Counter: 16 bit register restricted to 0000H -> 07FFH
Special Function Registers (SFR) Space:
Byte Address | Name | Description | Bits
81H | SP | Stack Pointer | not bit addressable
82H | DPL | Low byte of DPTR | not bit addressable
83H | DPH | High byte of DPTR | not bit addressable
87H | PCON | Power control | not bit addressable
88H | TCON | Timer control | TF1-TR1-TF0-TR0-IE1-IT1-IE0-IT0
89H | TMOD | Timer mode control | not bit addressable
8AH | TL0 | Timer 0 low byte | not bit addressable
8BH | TL1 | Timer 1 low byte | not bit addressable
8CH | TH0 | Timer 0 high byte | not bit addressable
8DH | TH1 | Timer 1 high byte | not bit addressable
90H | P1 | Parallel port 1 | P1.7 -> P1.0
98H | SCON | Serial control | SM0-SM1-SM2-REN-TB8-RB8-TI -RI
99H | SBUF | Serial buffer | not bit addressable
A8H | IE | Interrupt Enable | EA - - -ES -ET1-EX1-ET0-EX0
B0H | P3 | Parallel port 3 | P3.7 -> P3.0
B8H | IP | Interrupt priority | - - -PS -PT1-PX1-PT0-PX0
D0H | PSW | Program Status Word | CY -AC -F0 -RS1-RS0-OV -F1 -P
E0H | ACC | Accumulator | ACC.7 -> ACC.0
F0H | B | B register | B.7 -> B.0
Interrupt control register
IE: EA Global bit to enable interrupts
ES,ETx Serial interrupt (either RI or TI), Clock interrupt on overflow
Power control register
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PCON: set to 2 will stop the processor
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Timer control and mode registers - 2 timers, 0 and 1
TCON: TF0/TF1 Timer overflow flag timers 0/1
TR0/TR1 Timer run control bit. Set by software to switch timer ON
TMOD: mode1-mode0 2 4-bit nibbles. Timer 1 high order nibble, Timer 0 low order.
mode = 0 13 bit timer
mode = 1 16 bit timer
mode = 2 8 bit auto-reload timer. THx -> TLx on overflow. Used by Serial
i/o as bit rate (*32). 0FDH in THx gives 9600bps for 11.059Mhz clock
Serial control register
SCON: SM0-SM1-SM2-REN-TB8-RB8 should be set to 010100 for normal operation
TI set when the character has been transmitted
RI set when a character is received
Addressing Modes:
Rn = Register R0 - R7 of the currently selected register bank.
direct = 8-bit internal data location's address. This could be an internal Data
RAM location (0-127) or a SFR.
@Ri = 8-bit internal Data RAM location addressed indirectly through R0 or R1.
#data = 8-bit constant included in instruction.
#data16 = 16-bit constant included in instruction.
addr11 = 11-bit destination address. Used by ACALL and AJMP.
The branch will be within the same 2K byte page of Program Memory as
the first byte of the following instruction.
addr16 = 16-bit destination address. Used by LCALL and LJMP.
A branch can be anywhere within the 2K byte Program Memory address
space.
rel = Signed (two's complement) 8-bit offset byte. Used by SJMP and all
conditional jumps. Range is -128 to +127 bytes relative to first
byte of the following instruction.
bit = Direct addressed bit in internal Data RAM or SFR.
Arithmetic | Byte | Cycle | C OV AC
ADD A,Rn | Add register to Accumulator | 1 | 1 | X X X
ADD A,direct | Add direct byte to Accumulator | 2 | 1 | X X X
ADD A,@Ri | Add indirect RAM to Accumulator | 1 | 1 | X X X
ADD A,#data | Add immediate data to Accumulator | 2 | 1 | X X X
ADDC A,Rn | Add register to Acc. with Carry | 1 | 1 | X X X
ADDC A,direct | Add direct byte to Acc. with Carry | 2 | 1 | X X X
ADDC A,@Ri | Add indirect RAM to Acc. with Carry | 1 | 1 | X X X
ADDC A,#data | Add immediate data to Acc. / Carry | 2 | 1 | X X X
SUBB A,Rn | Subtract reg. from Acc. with borrow | 1 | 1 | X X X
SUBB A,direct | Sub. direct byte from Acc. / borrow | 2 | 1 | X X X
SUBB A,@Ri | Sub. indirect RAM from Acc./ borrow | 1 | 1 | X X X
SUBB A,#data | Sub. imm. data from Acc. / borrow | 2 | 1 | X X X
INC A | Increment Accumulator | 1 | 1 |
INC Rn | Increment register | 1 | 1 |
INC direct | Increment direct byte | 2 | 1 |
INC @Ri | Increment indirect RAM | 1 | 1 |
DEC A | Decrement Accumulator | 1 | 1 |
DEC Rn | Decrement register | 1 | 1 |
DEC direct | Decrement direct byte | 2 | 1 |
DEC @Ri | Decrement indirect RAM | 1 | 1 |
INC DPTR | Increment Data Pointer | 1 | 2 |
MUL AB | Multiply A and B | 1 | 4 | 0 X
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DIV AB | Divide A by B | 1 | 4 | 0 X
DA A | Decimal adjust Accumulator | 1 | 1 | X
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Logical | Byte | Cycle | C OV AC
ANL A,Rn | AND register to Accumulator | 1 | 1 |
ANL A,direct | AND direct byte to Accumulator | 2 | 1 |
ANL A,@Ri | AND indirect RAM to Accumulator | 1 | 1 |
ANL A,#data | AND immediate data to Accumulator | 2 | 1 |
ANL direct,A | AND Accumulator to direct byte | 2 | 1 |
ANL direct,#data | AND immediate data to direct byte | 3 | 2 |
ORL A,Rn | OR register to Accumulator | 1 | 1 |
ORL A,direct | OR direct byte to Accumulator | 2 | 1 |
ORL A,@Ri | OR indirect RAM to Accumulator | 1 | 1 |
ORL A,#data | OR immediate data to Accumulator | 2 | 1 |
ORL direct,A | OR Accumulator to direct byte | 2 | 1 |
ORL direct,#data | OR immediate data to direct byte | 3 | 2 |
XRL A,Rn | Exc-OR register to Accumulator | 1 | 1 |
XRL A,direct | Exc-OR direct byte to Accumulator | 2 | 2 |
XRL A,@Ri | Exc-OR indirect RAM to Accumulator | 1 | 1 |
XRL A,#data | Exc-OR immediate data to Acc. | 2 | 1 |
XRL direct,A | Exc-OR Accumulator to direct byte | 2 | 1 |
XRL direct,#data | Exc-OR imm. data to direct byte | 3 | 2 |
CLR A | Clear Accumulator | 1 | 1 |
CPL A | Complement Accumulator | 1 | 1 |
RL A | Rotate Accumulator left | 1 | 1 |
RLC A | Rotate Acc. left through Carry | 1 | 1 | X
RR A | Rotate Accumulator right | 1 | 1 |
RRC A | Rotate Acc. right through Carry | 1 | 1 | X
SWAP A | Swap nibbles within the Accumulator | 1 | 1 |
NOP | No operation | 1 | 1 |
Boolean | Byte | Cycle | C OV AC
CLR C | Clear Carry | 1 | 1 | 0
CLR bit | Clear direct bit | 2 | 1 |
SETB C | Set Carry | 1 | 1 | 1
SETB bit | Set direct bit | 2 | 1 |
CPL C | Complement Carry | 1 | 1 | X
CPL bit | Complement direct bit | 2 | 1 |
ANL C,bit | AND direct bit to Carry | 2 | 2 | X
ANL C,/bit | AND complement of dir. bit to Carry | 2 | 2 | X
ORL C,bit | OR direct bit to Carry | 2 | 2 | X
ORL C,/bit | OR complement of dir. bit to Carry | 2 | 2 | X
MOV C,bit | Move direct bit to Carry | 2 | 1 | X
MOV bit,C | Move Carry to direct bit | 2 | 2 |
JC rel | Jump if Carry is set | 2 | 2 |
JNC rel | Jump if Carry not set | 2 | 2 |
JB bit,rel | Jump if direct bit is set | 3 | 2 |
JNB bit,rel | Jump if direct bit is not set | 3 | 2 |
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JBC bit,rel | Jump if dir. bit is set & clear bit | 3 | 2 |
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Data transfer | Byte | Cycle | C OV AC
MOV A,Rn | Move register to Accumulator | 1 | 1 |
MOV A,direct | Move direct byte to Accumulator | 2 | 1 |
MOV A,@Ri | Move indirect RAM to Accumulator | 1 | 1 |
MOV A,#data | Move immediate data to Accumulator | 2 | 1 |
MOV Rn,A | Move Accumulator to register | 1 | 1 |
MOV Rn,direct | Move direct byte to register | 2 | 2 |
MOV Rn,#data | Move immediate data to register | 2 | 1 |
MOV direct,A | Move Accumulator to direct byte | 2 | 1 |
MOV direct,Rn | Move register to direct byte | 2 | 2 |
MOV direct,direct| Move direct byte to direct byte | 3 | 2 |
MOV direct,@Ri | Move indirect RAM to direct byte | 2 | 2 |
MOV direct,#data | Move immediate data to direct byte | 3 | 2 |
MOV @Ri,A | Move Accumulator to indirect RAM | 1 | 1 |
MOV @Ri,direct | Move direct byte to indirect RAM | 2 | 2 |
MOV @Ri,#data | Move immediate data to indirect RAM | 2 | 1 |
MOV DPTR,#data16 | Load Data Pointer with 16-bit const | 3 | 2 |
MOVC A,@A+DPTR | Move Code byte rel. to DPTR to Acc. | 1 | 2 |
MOVC A,@A+PC | Move Code byte rel. to PC to Acc. | 1 | 2 |
PUSH direct | Push direct byte onto stack | 2 | 2 |
POP direct | Pop direct byte from stack | 2 | 2 |
XCH A,Rn | Exchange register with Accumulator | 1 | 1 |
XCH A,direct | Exchange direct byte with Acc. | 2 | 1 |
XCH A,@Ri | Exchange indirect RAM with Acc. | 1 | 1 |
XCHD A,@Ri | Exchange low order digit indirect | | |
| RAM with Accumulator | 1 | 1 |
Branching | Byte | Cycle | C OV AC
ACALL addr11 | Absolute subroutine call | 2 | 2 |
LCALL addr16 | Long subroutine call | 3 | 2 |
RET | Return from subroutine | 1 | 2 |
RETI | Return from interrupt | 1 | 2 |
AJMP addr11 | Absolute jump | 2 | 2 |
LJMP addr16 | Long jump | 3 | 2 |
SJMP rel | Short jump (relative address) | 2 | 2 |
JMP @A+DPTR | Jump indirect relative to the DPTR | 1 | 2 |
JZ rel | Jump if Accumulator is zero | 2 | 2 |
JNZ rel | Jump if Accumulator is not zero | 2 | 2 |
CJNE A,direct,rel | Compare direct byte to Accumulator | | |
| and jump if not equal | 3 | 2 | X
CJNE A,#data,rel | Compare immediate data to | | |
| Accumulator and jump if not equal | 3 | 2 | X
CJNE Rn,#data,rel | Compare immediate data to register | | |
| and jump if not equal | 3 | 2 | X
CJNE @Ri,#data,rel| Compare immediate data to indirect | | |
| RAM and jump if not equal | 3 | 2 | X
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DJNZ Rn,rel | Decr. register and jump if not zero | 2 | 2 |
DJNZ direct,rel | Decrement direct byte and jump if | | |
| not zero | 3 | 2 |
Constants:
Numbers: Decimal - 34, Binary - 01110101B, Hexadecimal - 0A8H
Characters: ‘A’ - ‘Abc’ - ‘A’,00DH,00AH (mixed mode)
Operators: ()’s + - / * MOD SHR SHL NOT AND OR XOR
Assembler directives and controls
$MOD2051 Include file MOD2051 - defines 2051 symbols
; Everything following a semicolon is a comment
Label: Labels of statements used for program branches.
TEN EQU 10 EQUates 10 with the symbol TEN
ON_FLAG BIT 6 Assigns bit 6 (either data or SFR space) to the symbol ON_FLAG
BUFFER DATA 32 Assigns byte 32 (either data or SFR space) to the symbol BUFFER
RESET CODE 0 Assigns 0 in code space to the symbol RESET
DSEG Makes the data space the currently selected segment
CSEG Makes the code space the currently selected segment
BSEG Makes the bit addressable area of data space the cur sel seg.
SP_BUFFER: DS 6 Reserves 6 bytes of storage in data space. DSEG must be active.
IO_MAP: DBIT 8 Reserves 8 bits of storage in bit space. BSEG must be active.
MESS1: DB ‘Hi’ Store byte constants in code space.
ORG 56H Specify a value for the cur sel segments location counter.
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