2005 Modeling v1 by 9b2SLCz2

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									      Table 121      Modeling and Simulation Difficult Challenges
WAS   Difficult Challenges  45 nm/Through 2010                Summary of Issues
 IS   Difficult Challenges ≥ 32 nm                             Summary of Issues
WAS   High-frequency device and circuit modeling for             Efficient extraction and simulation of full-chip
      5–100 GHz applications                                     interconnect delay
                                                                 Accurate and yet efficient 3D interconnect models,
                                                                 especially for transmission lines and S-parameters

                                                                 Extension of physical device models to III/V
                                                                 materials
                                                                 High-frequency circuit models including non-quasi-static,
                                                                 substrate noise, 1/f noise and parasitic coupling

                                                                 Parameter extraction assisted by numerical electrical
                                                                 simulation instead of RF measurement
                                                                 Scalable active and passive component models for
                                                                 compact circuit simulation
                                                                 Co-design between interconnects and packaging
IS




WAS   Front-end process modeling for nanometer Structures        Diffusion/activation/damage models and parameters
                                                                 including SPE and low thermal budget processes in Si-
                                                                 based substrate, i.e., Si, SiGe:C, Ge (incl. strain), SOI, and
                                                                 ultra-thin body devices
                                                                 Characterization tools/methodologies for these ultra
                                                                 shallow geometries/junctions and low dopant levels

                                                                 Modeling hierarchy from atomistic to continuum for
                                                                 dopants and defects in bulk and at interfaces
                                                                 Front-end processing impact on reliability
IS




WAS     Integrated modeling of equipment, materials, feature     Fundamental physical data (e.g., rate constants, cross
        scale processes and influences on devices                sections, surface chemistry for ULK, photoresists and high-
                                                                 k metal gate); reaction mechanisms, and reduced models
                                                                 for complex chemistry

                                                                 Linked equipment/feature scale models (including high-k
                                                                 metal gate integration, damage prediction)
                                                                 CMP (full wafer and chip level, pattern dependent effects)

                                                                 MOCVD, PECVD, ALD, electroplating and electroless
                                                                 deposition modeling
                                                                 Multi-generation equipment/wafer models
IS
IS




WAS     Lithography simulation including NGL          Optical simulation of resolution enhancement techniques
                                                      including mask optimization (OPC, PSM)

                                                      Predictive resist models (e.g. mesoscale models)
                                                      including line-edge roughness, etch resistance, adhesion,
                                                      and mechanical stability
                                                      Methods to easily calibrate resist model kinetic and
                                                      transport parameters
                                                      Models that bridge requirements of OPC (speed) and
                                                      process development (predictive)
                                                      Experimental verification and simulation of ultra-
                                                      high NA vector models, including polarization
                                                      Models and experimental verification of non-optical
                                                      immersion lithography effects (e.g. topography and
                                                      change of refractive index distribution)

                                                      Multi-generation lithography system models
                                                      Simulation of defect influences/defect printing
IS




WAS   Ultimate nanoscale CMOS simulation capability   Methods and algorithms that contribute to prediction of
                                                      CMOS limits
                                                      Quantum based simulators
                                                      Models and analysis to enable design and evaluation of
                                                      devices and architectures beyond traditional planar CMOS

                                                      Gate stack models for ultra-thin dielectrics
                                                      Models for device impact of statistical fluctuations in
                                                      structures and dopant distributions
                                                      Phenomenological material models for stress
                                                      engineering
IS




WAS     Thermal-mechanical-electrical modeling for    Model thermal-mechanical, thermodynamic and
        interconnections and packaging                electronic properties of low k, high k, and conductors and
                                                      the impact of processing on these properties especially
                                                      for interfaces and films under 1 micron dimension

                                                      Model reliability of packages and interconnects, e.g. stress
                                                      voiding, electromigration, piezoelectric effects; textures,
                                                      fracture, adhesion.
        interconnections and packaging




                                                              Models for electron transport in ultra fine patterned
                                                              conductors.
IS




WAS   Difficult Challenges <45 nm/Beyond 2010                 Summary of Issues
IS    Difficult Challenges < 32 nm
WAS     Modeling of chemical, thermomechanical, and           Computational materials science tools to describe
        electrical properties of new materials                materials properties, process options, and operating
                                                              behavior for new materials applied in devices and
                                                              interconnects, including especially for the following: gate
                                                              stacks, predictive modeling of dielectric constant, bulk
                                                              polarization charge, surface states, thermomechanical
                                                              (including stress effects on mobility), optical
                                                              properties, reliability, breakdown, and leakage currents
                                                              including band structure, tunneling from process/materials
                                                              and structure conditions. Models for air gap and novel
                                                              integrations in 3D interconnects including data for
                                                              ultrathin material properties.



IS
WAS     Compact modeling including more physical models and   Computer-efficient inclusion of influences of statistics
        statistics                                            (incl. correlations) before process freeze, quantum/ballistic
                                                              transport, etc., into compact modeling


IS
WAS     Nano-scale modeling                                   Process modeling tools for the development of novel
                                                              nanostructure devices (nanowires, carbon nanotubes (incl.
                                                              doping) , quantum dots, molecular electronics)

                                                              Device modeling tools for analysis of nanoscale device
                                                              operation (quantum transport, resonant tunneling,
                                                              spintronics, contact effects)
IS



WAS     Optoelectronics modeling                              Coupling between electrical and optical systems, optical
                                                              interconnect models, semiconductor laser modeling

                                                              Physical design tools for integrated electrical/optical
                                                              systems
IS
      Table 122a      Modeling and Simulation Technology Requirements: Capabilities—Near-term
                                            Near-term
      Year of Production                              2005                2006               2007               2008               2009          2010   2011   2012
      DRAM ½ Pitch (nm) (contacted)                    80                  70                 65                 57                 50            45     40     35
WAS   MPU/ASIC Metal 1 (M1) ½ Pitch                    95                  85                 76                 67                 60            54     48     42
      (nm)(contacted)
IS                                                     85                  76                 67                 60                 54            48     42     38
      MPU Physical Gate Length (nm)                    32                  28                 25                 22                 20            18     16     14
      Lithography
WAS   Exposure                                       Simulation of immersion             Simulation of EUV, EPL, ML2, imprint lithography
                                                           lithography                 options, models bridging OPC and predictive feature
                                                                                                         scale simulation



IS
WAS   Resist models                              Detailed chemically amplified resist and EUV resist          Finite polymer-size effects
                                                models including LER, and methods to easily calibrate
                                                       parameters; coupling with etch models



IS
WAS   Full-chip lithography simulation           Simulation of lithography and etching across whole exposure field to detect weak spots


IS
      Front End Process Modeling
WAS   Gate Stack*                               High-k             Model materials properties and          Processing and properties of
                                                dielectrics and      electrical behavior of prioritized          alternative materials
                                                gate materials       alternative dielectrics and gates
                                                (interfaces,         (interfaces, defects, impurities,
                                                impurity                     mobility, leakage)
                                                diffusion,
                                                electrical
                                                barrier)



IS
WAS   Diffusion and activation models              Enhancement of models for Si based materials, including stress/strain and including
                                                                    flash/laser anneals and solid phase epitaxy



IS
      Topography Modeling
WAS   Deposition                                  Electrical properties, stress, incl. microstructure;     Adhesion and reliability, including
                                                  layout dependence; prediction of liquid dispense           microstructure; full molecular
                                                 (resist, spin on ULK) on planarity and gate pattern;       dynamics (or atomistic) feature
                                                    coupling with etching and lithography models.         scale models, prediction of surface
                                                                                                                      properties




IS
WAS   Planarization                              Chip-level including dummy placement optimization,        CMP process models for circuit
                                                  padwear and conditioning disc modeling, physics-                   design
                                                 based optimizations of rates, uniformity, and defect
                                                                       reduction




IS
WAS   Etching                                   (Surface) physics Integration of feature-scale simulation with equipment (plasma) models;
                                                  based feature         process integration (coupling of etch-deposition-plating-CMP-
                                                  scale models    lithography- including data beyond topography), full molecular dynamcs
                                                                                      (or atomistic) feature scale models




IS
      Numerical Device Modeling [1]
WAS   Classical CMOS*                           Device models with relevant quantum effects included       Models/algorithms to the scaling
                                                                                                                         limit

IS
WAS   Non-classical CMOS including transport-   Device models with relevant quantum effects included,             Ballistic transport
      enhanced devices*                                    especially for ultra-thin films


IS
WAS   Novel memory devices (MRAM,               Processing, material properties and performance modeling of MRAMs, PCMs, FeRAMs and
      FeRAM, ..)                                                                     SONOS/NROMs

IS
WAS   RF Modeling                                                 Physical device models for HF noise and mobility in III/Vs
      Table 122a        Modeling and Simulation Technology Requirements: Capabilities—Near-term
                                              Near-term
      Year of Production                                   2005                 2006                 2007                   2008                 2009       2010   2011   2012
      DRAM ½ Pitch (nm) (contacted)                         80                   70                   65                      57                   50        45     40     35
IS
      Circuit Component Modeling [2]
WAS   Active devices*                                   Non-       Circuit models for non-classical                      Include ballistic effects
                                                     classical CMOS CMOS devices including influences
                                                         compact                of statistics
                                                      models/ non-
                                                       quasi-static
                                                       models and
                                                    series resistance




IS
WAS   Interconnects and integrated passives              Hierarchical full chip RLC                                   Include reliability


IS
WAS   Process and Materials Impact on                    Models that relate material properties (process related or fundamental) to electron
      Electrical Performance                         transport (e.g. in conducting lines). Includes models for electron scattering. Models that
                                                          predict paths to material property repair (e.g. low-k repair, capacitance repair)




IS
      Package Modeling
WAS   Electrical modeling*                          Unified RLC               Reduced order models                           Full-wave analysis
                                                     extraction for
                                                    package/chips




IS
WAS   Thermal-mechanical modeling                     Thermo-              Include non-bulk and porous                   Include reliability (esp. life
                                                      mechanical-                 materials properties                             prediction)
                                                       integrated
                                                         models




IS
WAS   Material properties                              Improved                  Full die simulation
                                                    material models
                                                    (visco-elasticity,
                                                          creep,
                                                       plasticity),
                                                        interfaces




IS
      Numerical analysis
WAS   Algorithms*                                  Faster algorithms                              Exploit parallel computation
                                                    including linear
                                                        solvers



IS


      *For 2003/2004, interim solutions are known but research is still needed towards mature commercial solutions.


                                                                               Manufacturable solutions exist, and are being optimized
                                                                                                  Manufacturable solutions are known
                                                                                                            Interim solutions are known     
                                                                                             Manufacturable solutions are NOT known

      Notes for Table 122a
      [1] In Numerical Device Modeling equations are solved which are typically based on fundamental physics and describe the electrical
      behavior on spatially fine resolved quantities. This means usually partial differential equations (with respect spatial coordinates) are
      employed. The goal is technology optimization and device insight.
      [2] In Circuit Element Modeling no spatially resolved models are used. Approximatively analytically solveable, physically based models
      give a guidance for the used relations between electrical quantities. The goal is a description of device behaviour (currents, charges,
      noise) in circuit simulators.
      Table 122a      Modeling and Simulation Technology Requirements: Capabilities—Near-term

      Year of Production                        2013
      DRAM ½ Pitch (nm) (contacted)              32
WAS   MPU/ASIC Metal 1 (M1) ½ Pitch              38
      (nm)(contacted)
IS                                               34
      MPU Physical Gate Length (nm)              13
      Lithography
WAS   Exposure




IS
WAS   Resist models




IS
WAS   Full-chip lithography simulation


IS
      Front End Process Modeling
WAS   Gate Stack*




IS
WAS   Diffusion and activation models




IS
      Topography Modeling
WAS   Deposition




IS
WAS   Planarization




IS
WAS   Etching




IS
      Numerical Device Modeling [1]
WAS   Classical CMOS*


IS
WAS   Non-classical CMOS including transport-
      enhanced devices*


IS
WAS   Novel memory devices (MRAM,
      FeRAM, ..)

IS
WAS   RF Modeling
      Table 122a        Modeling and Simulation Technology Requirements: Capabilities—Near-term

      Year of Production                                2013
      DRAM ½ Pitch (nm) (contacted)                      32
IS
      Circuit Component Modeling [2]
WAS   Active devices*




IS
WAS   Interconnects and integrated passives


IS
WAS   Process and Materials Impact on
      Electrical Performance




IS
      Package Modeling
WAS   Electrical modeling*




IS
WAS   Thermal-mechanical modeling




IS
WAS   Material properties




IS
      Numerical analysis
WAS   Algorithms*




IS


      *For 2003/2004, interim solutions are known but research is still needed towards mature commercial solutions.




      Notes for Table 122a
      [1] In Numerical Device Modeling equations are solved which are typically based on fundamental physics and describe the electrical
      behavior on spatially fine resolved quantities. This means usually partial differential equations (with respect spatial coordinates) are
      employed. The goal is technology optimization and device insight.
      [2] In Circuit Element Modeling no spatially resolved models are used. Approximatively analytically solveable, physically based models
      give a guidance for the used relations between electrical quantities. The goal is a description of device behaviour (currents, charges,
      noise) in circuit simulators.
      Table 122a      Modeling and Simulation Technology Requirements: Capabilities—Near-term
                                            Long-term
      Year of Production                        2014       2015        2016        2017         2018   2019   2020
      DRAM ½ Pitch (nm) (contacted)              28         25          22          20           18     16     14
WAS   MPU/ASIC Metal 1 (M1) ½ Pitch              34         30          27          24           21     19     17
      (nm)(contacted)
IS                                               30         27          24          21           19     17     15
      MPU Physical Gate Length (nm)              11         10           9           8           7      6      6
      Lithography
WAS   Exposure




IS
WAS   Resist models




IS
WAS   Full-chip lithography simulation


IS
      Front End Process Modeling
WAS   Gate Stack*




IS
WAS   Diffusion and activation models




IS
      Topography Modeling
WAS   Deposition




IS
WAS   Planarization




IS
WAS   Etching




IS
      Numerical Device Modeling [1]
WAS   Classical CMOS*


IS
WAS   Non-classical CMOS including transport-
      enhanced devices*


IS
WAS   Novel memory devices (MRAM,
      FeRAM, ..)

IS
WAS   RF Modeling
      Table 122a        Modeling and Simulation Technology Requirements: Capabilities—Near-term
                                              Long-term
      Year of Production                                2014            2015            2016            2017          2018   2019          2020
      DRAM ½ Pitch (nm) (contacted)                      28              25               22              20           18     16            14
IS
      Circuit Component Modeling [2]
WAS   Active devices*




IS
WAS   Interconnects and integrated passives


IS
WAS   Process and Materials Impact on
      Electrical Performance




IS
      Package Modeling
WAS   Electrical modeling*




IS
WAS   Thermal-mechanical modeling




IS
WAS   Material properties




IS
      Numerical analysis
WAS   Algorithms*




IS


      *For 2003/2004, interim solutions are known but research is still needed towards mature commercial solutions.




      Notes for Table 122a
      [1] In Numerical Device Modeling equations are solved which are typically based on fundamental physics and describe the electrical
      behavior on spatially fine resolved quantities. This means usually partial differential equations (with respect spatial coordinates) are
      employed. The goal is technology optimization and device insight.
      [2] In Circuit Element Modeling no spatially resolved models are used. Approximatively analytically solveable, physically based models
      give a guidance for the used relations between electrical quantities. The goal is a description of device behaviour (currents, charges,
      noise) in circuit simulators.
      Table 122b       Modeling and Simulation Technology Requirements: Accuracy and Speed—Near-term
                                                Near-term
      Year of Production                                 2005       2006       2007       2008       2009      2010   2011   2012   2013
      DRAM ½ Pitch (nm) (contacted)                       80         70         65         57         50        45     40     35     32
      MPU/ASIC Metal 1 (M1) ½ Pitch
WAS                                                       95         85         76         67         60        54     48     42     38
      (nm)(contacted)
IS                                                        85         76         67         60         54        48     42     38     34
      MPU Physical Gate Length (nm)                       32         28         25         22         20        18     16     14     13
IS
      Technology-development cost reduction (due to
WAS                                                      35%        40%        40%        40%        40%
      TCAD)
IS
      Lithography Modeling
      CD prediction accuracy (incl. OP effects)
WAS   for dense and isolated lines - 2% of              0.9 nm     0.8 nm     0.7 nm     0.6 nm     0.6 nm
      targetted printed gate length
IS
      Front End Process Modeling

WAS   Vertical junction depth simulation accuracy        10%        10%        10%        10%        10%

IS
WAS   (% of physical gate length)                       (3.2 nm)   (2.8 nm)   (2.5 nm)   (2.2 nm)   (2.0 nm)
IS
      Lateral junction depth: 50% of FEP Lgate 3
WAS                                                     1.6 nm     1.4 nm     1.3 nm     1.1 nm     1.0 nm
      sigma
IS

WAS   Total source/drain series resistance (accuracy)    10%        10%        10%        10%        10%

IS

      Back-end process/Equipment/Topography
      Modeling


      Etch/deposition cross wafer uniformity (%
WAS                                                      2.50%      2.50%      2.50%      2.50%      2.50%
      accuracy of the MPU physical gate length)

IS
      2D/3D topography accuracy (% accuracy of            5%         5%         5%         5%         5%
WAS
      MPU physical gate length)                         (1.6 nm)   (1.4nm)    (1.3 nm)   (1.1 nm)   (1.0 nm)

IS

      Numerical Device Modeling [1]
      Accuracy of ft at given ft (% of maximum chip
WAS                                                      10%        10%        10%        10%        10%
      frequency)
IS
WAS   Gate leakage accuracy (% of Ig)                    25%        25%        25%        25%        25%
IS
WAS   Ion accuracy                                        5%         3%         3%         3%         3%
IS
WAS   Ioff accuracy                                      30%        30%        30%        30%        30%
IS
WAS   Long-channel Vt accuracy [3]                        3%         3%         3%         3%         3%
IS
WAS   Vt rolloff accuracy (mV) [4]                       15mV       10mV       10mV       7mV        7mV
IS
WAS   Vt 3F variation (%)                                25%        25%        25%        25%        25%
IS
      Circuit Element Modeling/ECAD [2]
WAS   I-V error in saturation region                      8%         6%         6%         5%         5%
 IS
WAS   I-V error in linear region                          3%         3%         3%         3%         3%
IS

WAS   I-V error in subthreshold and off-current          15%        15%        10%        10%        10%


IS

WAS   Intrinsic MOS C-V accuracy                          5%         5%         5%         5%         5%
IS
WAS   Parasitic C-V accuracy                              5%         5%         5%         5%         5%
IS
      Accuracy of Gm and Gd at Vt +150mV versus L,
WAS                                                      10%        10%        10%        10%        10%
      Vbs, Vds and T
IS
      Circuit delay accuracy (% of 1/maximum chip
WAS                                                       5%         5%         5%         5%         5%
      frequency)
      Table 122b      Modeling and Simulation Technology Requirements: Accuracy and Speed—Near-term
                                               Near-term
      Year of Production                                    2005            2006           2007          2008           2009            2010      2011          2012           2013
      DRAM ½ Pitch (nm) (contacted)                          80               70            65             57            50              45        40            35             32
IS
      RLC delay accuracy (% of 1/maximum chip
WAS                                                          5%              5%             5%            5%             5%
      frequency)
IS
      Package Modeling
      Package delay accuracy (% of 1/off-chip
WAS                                                          1%              1%             1%            1%             1%
      clock frequency)
IS
      Temperature distribution for package
WAS                                                          1C               1C            1C            1C             1C
      (accuracy)
IS
      Numerical Method
      Speed-up of algorithms for 3D
WAS   process/device/interconnect simulation                 8             11.2           16          22.4          32
      (compared with year 2000)*
IS
      *Numbers referring to continuum models. Estimated scaling similar to the ITRS. Different figures expected for other models.


                                                                          Manufacturable solutions exist, and are being optimized
                                                                                             Manufacturable solutions are known
                                                                                                     Interim solutions are known    
                                                                                       Manufacturable solutions are NOT known



      Notes for Table 122b
      [1] In Numerical Device Modeling equations are solved which are typically based on fundamental physics and describe the electrical behavior on spatially fine resolved quantities.
      This means usually partial differential equations (with respect spatial coordinates) are employed. The goal is technology optimization and device insight.


      [2] In Circuit Element Modeling no spatially resolved models are used. Approximatively analytically solveable, physically based models give a guidance for the used relations
      between electrical quantities. The goal is a description of device behaviour (currents, charges, noise) in circuit simulators.
      [3] Absolute values strongly differ for HP and LSTP. Important aspects for nominal devices also included in rolloff accuracy

      [4] (Positive) difference in Vth of nominal and subnominal device
      Table 122b       Modeling and Simulation Technology Requirements: Accuracy and Speed—Near-term
                                                Long-term
      Year of Production                                2014   2015    2016       2017      2018       2019   2020
      DRAM ½ Pitch (nm) (contacted)                      28     25      22         20        18         16     14
      MPU/ASIC Metal 1 (M1) ½ Pitch
WAS                                                      34     30      27         24        21         19     17
      (nm)(contacted)
IS                                                       30     27      24         21        19         17     15
      MPU Physical Gate Length (nm)                      11     10      9          8          7         6      6
IS
      Technology-development cost reduction (due to
WAS
      TCAD)
IS
      Lithography Modeling
      CD prediction accuracy (incl. OP effects)
WAS   for dense and isolated lines - 2% of
      targetted printed gate length
IS
      Front End Process Modeling

WAS   Vertical junction depth simulation accuracy

IS
WAS   (% of physical gate length)
IS
      Lateral junction depth: 50% of FEP Lgate 3
WAS
      sigma
IS

WAS   Total source/drain series resistance (accuracy)

IS

      Back-end process/Equipment/Topography
      Modeling


      Etch/deposition cross wafer uniformity (%
WAS
      accuracy of the MPU physical gate length)

IS
      2D/3D topography accuracy (% accuracy of
WAS
      MPU physical gate length)

IS

      Numerical Device Modeling [1]
      Accuracy of ft at given ft (% of maximum chip
WAS
      frequency)
IS
WAS   Gate leakage accuracy (% of Ig)
IS
WAS   Ion accuracy
IS
WAS   Ioff accuracy
IS
WAS   Long-channel Vt accuracy [3]
IS
WAS   Vt rolloff accuracy (mV) [4]
IS
WAS   Vt 3F variation (%)
IS
      Circuit Element Modeling/ECAD [2]
WAS   I-V error in saturation region
 IS
WAS   I-V error in linear region
IS

WAS   I-V error in subthreshold and off-current


IS

WAS   Intrinsic MOS C-V accuracy
IS
WAS   Parasitic C-V accuracy
IS
      Accuracy of Gm and Gd at Vt +150mV versus L,
WAS
      Vbs, Vds and T
IS
      Circuit delay accuracy (% of 1/maximum chip
WAS
      frequency)
      Table 122b      Modeling and Simulation Technology Requirements: Accuracy and Speed—Near-term
                                               Long-term
      Year of Production                                    2014          2015           2016           2017          2018           2019         2020
      DRAM ½ Pitch (nm) (contacted)                          28             25            22             20             18            16           14
IS
      RLC delay accuracy (% of 1/maximum chip
WAS
      frequency)
IS
      Package Modeling
      Package delay accuracy (% of 1/off-chip
WAS
      clock frequency)
IS
      Temperature distribution for package
WAS
      (accuracy)
IS
      Numerical Method
      Speed-up of algorithms for 3D
WAS   process/device/interconnect simulation
      (compared with year 2000)*
IS
      *Numbers referring to continuum models. Estimated scaling similar to the ITRS. Different figures expected for other models.




      Notes for Table 122b
      [1] In Numerical Device Modeling equations are solved which are typically based on fundamental physics and describe the electrical behavior on spatially fine resolved quantities.
      This means usually partial differential equations (with respect spatial coordinates) are employed. The goal is technology optimization and device insight.


      [2] In Circuit Element Modeling no spatially resolved models are used. Approximatively analytically solveable, physically based models give a guidance for the used relations
      between electrical quantities. The goal is a description of device behaviour (currents, charges, noise) in circuit simulators.
      [3] Absolute values strongly differ for HP and LSTP. Important aspects for nominal devices also included in rolloff accuracy

      [4] (Positive) difference in Vth of nominal and subnominal device
      Table 122c       Modeling and Simulation Technology Requirements: Capabilities—Long-term

      Year of Production                       2010       2011       2012        2013      2014       2015        2016     2017      2018
      DRAM ½ Pitch (nm) (contacted)             45         40         35          32         28         25           22     20          18
WAS   MPU/ASIC Metal 1 (M1) ½ Pitch             54         48         42          38         34         30           27     24          21
      (nm)(contacted)
IS                                              48         42         38          34         30         27           24     21          19
WAS   MPU Physical Gate Length (nm)             18         16         14          13         11         10           9      8           7
IS
      Lithography Modeling
WAS   Next generation lithography              NGL models and modeling of materials and components (immersion, EUV, EPL, ML2
                                                                      lithographic processes, imprint)

IS
WAS   Resist technology                       Meso-scale resist models         Non-conventional photo-resist models and coupling with
                                              with finite molecule effects                         etch models
IS
      Front End process Modeling
WAS   Advanced process models                                                  Atomistic process modeling
 IS
WAS   Models for advanced doping techniques                                      New technology needed
IS
      Topography Modeling
WAS   Alternative material models               Calculation of thermal (thermodynamic),                      Atomistic material model
                                              mechanical and electronic properties; process
                                              impact on intrinsic material behavior integrity
                                                and electrical performance under strain.



IS
WAS   Equipment impact on process results     Computer engineered materials and process recipes; predictive manufacturability and
      including material properties                                yield; full process integration models.

IS
      Numerical Device Modeling
WAS   Emerging devices                                 Nanoscale simulation capability including accurate quantum effects
 IS
      Circuit Element Modeling/ECAD
WAS   Advanced circuit models                                   Circuit models for nanoscale devices and interconnects


IS
      Package Modeling
WAS   Electrical/optical models                 Mixed electrical/-optical               Reliability prediction in coupled modeling
                                                       analysis

IS
      Numerics
WAS   Numerical algorithms                    Efficient atomistic/ quantum        Multi-scale simulation (atomistic-continuum); fast
                                                  methods; ab-initio or         coupling of equipment-topography-electrical-reliability
                                              molecular dynamcis based                 models; hierarchical full-chip simulation
                                                topography simulations.




IS



                                                      Manufacturable solutions exist, and are being optimized
                                                                           Manufacturable solutions are known
                                                                                   Interim solutions are known   
                                                                     Manufacturable solutions are NOT known
                         Table 122c       Modeling and Simulation Technology Requirements: Capabilities—Long-term

                         Year of Production                      2019     2020
                         DRAM ½ Pitch (nm) (contacted)            16       14
              WAS        MPU/ASIC Metal 1 (M1) ½ Pitch            19       17
                         (nm)(contacted)
                IS                                                17       15
              WAS        MPU Physical Gate Length (nm)             6       6
                IS
                         Lithography Modeling
              WAS        Next generation lithography


                IS
              WAS        Resist technology
                IS
                         Front End process Modeling
              WAS        Advanced process models
               IS
              WAS        Models for advanced doping techniques
                IS
                         Topography Modeling
              WAS        Alternative material models




                IS
              WAS        Equipment impact on process results
                         including material properties

                IS
                         Numerical Device Modeling
              WAS        Emerging devices
               IS
                         Circuit Element Modeling/ECAD
              WAS        Advanced circuit models


                IS
                         Package Modeling
              WAS        Electrical/optical models


                IS
                         Numerics
              WAS        Numerical algorithms




                IS



utions exist, and are being optimized
      2005 Headers
                                      Near-term
      Year of Production               2005       2006   2007   2008   2009   2010   2011   2012   2013
      DRAM ½ Pitch (nm) (contacted)     80         70     65     57     50     45     40     35     32
      MPU/ASIC Metal 1 (M1) ½ Pitch
WAS                                     95         85     76     67     60     54     48     42     38
      (nm)(contacted)
IS                                      85         76     67     60     54     48     42     38     34
      MPU Physical Gate Length (nm)     32         28     25     22     20     18     16     14     13
      2005 Headers
                                      Long-term
      Year of Production               2014   2015     2016   2017   2018   2019   2020
      DRAM ½ Pitch (nm) (contacted)     28        25    22     20     18     16     14
      MPU/ASIC Metal 1 (M1) ½ Pitch
WAS                                     34        30    27     24     21     19     17
      (nm)(contacted)
IS                                      30        27    24     21     19     17     15
      MPU Physical Gate Length (nm)     11        10    9      8      7      6      6
Notes for Tables
see Word document file containing all tables' notes
Notes for Tables
see Word document file containing all tables' notes
       First Year of IC Production          2005   2006   2007    2008   2009   2010   2011   2012    2013   2014   2015   2016    2017   2018   2019   2020
                DRAM 1/2 Pitch              80nm   70nm   65nm    57nm   50nm   45nm   40nm   35nm    32nm   28nm   25nm   22nm   20nm    18nm   16nm   14nm




This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.
Research Required
Development Underway
Qualification / Pre-Production
Continuous Improvement


Work-in-Progress--Do Not Publish

								
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