A method to distribute power and synchronized
clocks in a distributed data acquisition system.
Presented at the University of Illinois for ECE 445, Spring 2008
Presented By Group 5, Richard Ross
Power and sample clock in a distributed data acquisition system
This project was selected because it presents challenges from diverse areas of
electrical engineering. It has both a digital and analog component and includes design
elements from power, networking, FPGA and embedded software.
The objective of this system is to develop a method to distribute power and sample
clocks to distributed data acquisition channels over standard Ethernet UTP cable. The
system consists of a channel controller board that will supply power and a sampling clock to
connected channel cards. The controller card will eventually have eight ports for channel
cards; this project will only implement one channel for testing purposes. The channel cards
will provide up to two measurement channels that sense various physical phenomena (e.g.
digital I/O, analog voltage, temperature). This portion of the project will focus on the
distribution of the power and clocks, the channel cards will be developed after this distribution
system is proven. This solution has many benefits:
1. Sampling clock provided using standard components. This eliminates the need for
specialized IEEE 1588 MAC/PHYs that are currently single-sourced.
2. Test and sample synchronization provided across multiple channels by sending control
commands and one pulse-per-second signals (1-PPS) over the distributed clock.
3. Power supplied over the Ethernet cable, no local supply or separate power cable
4. Remote channel cards allow the measurement of signals at the source and allow the
transmission of the collected data by digital means, reducing the need for shielding
and filtering of analog signals.
5. Data from events recorded by sensors that are physically far apart can be included in
the same test sequence with a high degree of confidence in the accuracy of the
reported relationship between the sensor samples in the time domain.
See Attached sheets. The following sections provide a brief description of each
Ethernet MAC (Both Channel Controller Card and Channel Card)
The Ethernet MAC interface consists of an Asix AX88178 USB to Gigabit Ethernet
Interface chip. The Windows XP driver is supplied by Asix and presents itself as a standard
NIC card. Configuration information is stored in a serial EEPROM. It uses a MII interface to
communicate with the ETHERNET PHY.
Ethernet PHY (Both Channel Controller Card and Channel Card)
The Ethernet PHY is implemented using an IEEE1588 compliant PHY from National,
DP83640. This PHY communicates with the Ethernet MAC via a standard MII interface.
Testing of the PHY is done through a JTAG interface. The PHY is connected to a Power Over
Ethernet compliant transformer, which interfaces with the PoE controller.
Channel Controller FPGA and Flow Chart
The Channel Controller FPGA is an Altera Cyclone III part. Currently the sponsoring
organization is reviewing the use of this part and a final decision is due 2-22-2008. The
commands to be sent are received via a USB to Serial chip. This is a dual chip with one UARt
being connected to the Channel Controller Card's FPGA, and the other going out a 3-pin
connector to the Channel Card's FPGA.
The Flow chart for the FPGA code is shown in Figure 1. The FPGA will get its
commands from the controlling system via a USB-Serial interface. The FPGA will use a
software UART to receive these commands and place them in the Receive FIFO. Once a
complete packet has been received, the command generator will take the data in the Receive
FIFO use it to modify the pulse width of the clock. A 50% duty cycle is the idle state, a 25%
duty cycle is a zero state (it also indicates the start of a command packet) and a 75% duty
cycle represents a one state.
SERIAL IN UART RX FIFO
CLOCK PLL CLOCK OUT
Figure 1 Channel Card FPGA Flow Chart
Channel Controller Power Over Ethernet and Power Supply
Power over Ethernet functions are performed by a Linear Technology PSE Controller
(LTC-4263-1). This controller accepts 60V and will negotiate with a connected PD to deliver
the correct amount of current. The 60V power supply is under review and will be replaced by
a bench power supply for initial testing. The local power is supplied by a Step-Down
Switching Regulator, LT1076HV. This regulator takes the 12-20V input and steps it down to
5V. This 5V supplies Low Dropout regulators for the 3.3V and 2.5V voltages.
Channel FPGA and Flow Chart
The Flow chart for the FPGA code is shown in Figure 2. The FPGA will get the
incoming clock from the Ethernet interface through a high pass filter. The received
commands will be recovered by a command recovery block (one that recognizes the zero,
one and idle states) and placed in a FIFO. Once a complete command has been recovered
the packet generator will take the received command and send it out a UART to the
CLOCK IN RX FIFO
UART/TX FIFO SERIAL OUT
Figure 2 Channel Card FPGA Flow Chart
Channel Controller Power Over Ethernet and Power Supply
Power over Ethernet functions are performed by a Linear Technology PD Controller
(LTC-4264). This controller accepts 60V from the Ethernet cable and negotiates with the PSE
for the correct amount of current. The 60V is then stepped down to 5V by a Step-Down
Switching Regulator, LT1076HV. This 5V supplies Low Dropout regulators for the 3.3V and
This system will allow a channel control card to communicate with a channel card over
100Mbit/sec Ethernet up to a distance of 100 feet at a bus utilization rate of 50%.
The PoE+ supply on the channel control card must be able to supply 45-55V (measured at
the channel card) when the channel card is drawing of 30W.
The channel card will be completely powered through the Ethernet cable and will draw 30W
of power. The generated sample clock will be modulated to transmit and receive simulated
test control signals (1-PPS and command). There will be no lost Ethernet or Clock control
See attached Bills of Material (BOM) for Controller and Channel board parts and order status.
Due to the dual nature of the interfaces on the channel control card and the channel card the
similar sections on each card will be nearly identical and will be developed together. The
schedule reflects the parallel design of the different blocks.
Research and identify Ethernet MAC/PHY
Select FPGA for Clock Generators 2/8/2008 In Progress
Determine simulated control data generation and
2/10/2008 Not Started
Select Magnetics and Link LEDs. 2/11/2008 Completed
Select method to impose clock on PoE+ Line 2/11/2008 In Progress
Identify components for 50V, 30W power supply. 2/11/2008 In Progress
Identify components for channel card local supply
and PoE+ interface.
Determine Ethernet Packet Generator/Receiver 2/13/2008 In Progress
Outline VHDL Code for clock generation/recovery
2/15/2008 In Progress
and command modulation/demodulation.
Outline code to interface with Ethernet MAC 2/16/2008 In Progress
Breadboard PoE Supplies and test. 2/18/2008 In Progress
Complete and review Schematic 2/20/2008 In Progress
PCB Layout 2/29/2008 Not Started
Write VHDL Code 3/8/2008 Not Started
PCB Fabrication (Outside Vendor) 3/8/2008 Not Started
Write Code to interface with Ethernet MAC 3/10/2008 Not Started
Write code to generate and receive simulated
3/10/2008 Not Started
Populate PCB with PoE+ Supplies and test 3/11/2008 Not Started
Simulate and debug VHDL code 3/15/2008 Not Started
Populate PCB with Clock Generator and Receiver
3/18/2008 Not Started
Populate PCB with Magnetics and MAC/PHY and
3/25/2008 Not Started
Populate PCB with Ethernet Traffic Generator and
4/8/2008 Not Started
Receiver and test.
Debug Interfaces between blocks 4/16/2008 Not Started
Performance Testing 4/19/2008 Not Started
Demonstration 4/25/2008 Not Started
Final Report 4/30/2005 Not Started