Basics - Boolean functions - PowerPoint by zn4qok8

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									                                             ECE 667
                                                 Spring 2011

                       Synthesis and Verification
                           of Digital Circuits

                                          Introduction
                                           Design Flow


                                                               1
ECE 667 - Synthesis & Verification - Lecture 1
           Electronic Design Automation EDA)




                                                           Synthesis



 Design &
 simulation                                      Verification




ECE 667 - Synthesis & Verification - Lecture 1                         2
                       Synthesis Process (high-level view)

                                                            ALGORITHM                                                        ARCHITECTURE
                           APPLICATION
                                                            IN k
                                                                                              +                 +
                                                                                                                             interconnect
                                                                    +                 +
                                                                             D                         D
                  -20 .0                                            +
                                                                        c1       c2
                                                                                      +       +
                                                                                                  c4       c5
                                                                                                                +

                                                                             D                         D
                  -40 .0                                                c3                        c6

                                                                                                                                             GP signal
    Am pl (db )




                                                                                                                      ASIC
                                                                                          d
                  -60 .0                                       IN       k
                                                                                 +            c1 +     +
                                                                                                                OUT
                                                                                                                                             processor
                                                                                          D
                  -80 .0                                                         +c
                                                                                      2        c3
                                                                                          D
                                                                                 c4
            -100 .0
                                                                                 +            c5 + +
                                                                                          D
            -120 .0                                                              +c            c7
                  0.0        200.0        4 00.0   600. 0                             6
                                                                                          D
                                     F req                                       c8

                                                                                                                      MCM
                                                                                                                                              memory


                             LOGIC AND PHYSICAL SYNTHESIS

                                                                                                                      HIGH-LEVEL SYNTHESIS




                                                                                                                        S1      S2      S3        S4




ECE 667 - Synthesis & Verification - Lecture 1                                                                                                           3
     Typical High-Level Synthesis System




ECE 667 - Synthesis & Verification - Lecture 1   4
      Architectural Synthesis & Optimization
                             a     b           c           b        a           c        b       a       c
                                                                            x
                     S0                    +         s0                             s0       x       x
                                                               x
                                       x             s1                                          +
                     S1                                                             s1
                                                                     +
                                       F                                                             F
                                                      s2
                                                                        F
                                                                                                 b           a       c
                     a         b       c                       a b          c
                                                                                     CK
                                                   CK
             CK
                                   +                                                                 X               X
                                                                    X
                                                                                     CTL
                                                   CTL                               logic
            CTL                                    logic                                                     FF
            logic                  FF                          FF           FF


                                                                                                                 +
                                   X                                +

ECE 667 - Synthesis & VerificationF Lecture 1
                                  -                                  F                                           F       5
                                       RTL Synthesis
                                                  - read HDL
            RTL to Network Transformation
                                                  - control/data flow analysis


                                                  - basic logic restructuring
       Technology independent Optimizations
                                                  - crude measures for goals

                                                  - use logic gates from target
                     Technology Mapping
                                                    cell library

                                                 - timing optimization
       Technology Dependent Optimizations
                                                 - physically driven optimizations

                                                  - improve testability
                         Test Preparation
                                                  - test logic insertion
ECE 667 - Synthesis & Verification - Lecture 1                                   6
                     Synthesis Flow (logic level)
                                      a multi-stage process

                                     Specification
                                      Logic a, b, c, d, f, g,
                            module example(clk,Extraction h)
                            input clk, a, b, c, d, e, f;
                            a Technology-Independent
                            output g, h; reg g, h;                   Optimization
                           b        a Technology-Dependent Mapping
                            always @(posedge clk) begin g1                    h
                           e          g = a | b;                  0        G
                                    bif (d) beging0
                                  f              if (c) h = a&~h;
                                                 else h = b;          h5          g
                                                                               G
                                  dcend else if (f) g = c; else a^b;
                                                                 h3           g
                                  bd             if (c) h = 1; else h ^b;  H
                            end e
                           fendmodule                     h1                    H h
                                  ae
                           c      c                                          clk
                           d
                                    f
                                                                               clk
ECE 667 - Synthesis & Verification - Lecture 1                                        7
ECE 667 - Synthesis & Verification - Lecture 1   8
            Implementation Choices (target)

                               Digital Circuit Implementation Approaches


                             Custom              Semicustom


                            Cell-based                           Array-based


          Standard Cells                                Pre-diffused         Pre-wired
                                         Macro Cells
          Compiled Cells                               (Gate Arrays)       (FPGAs, PLDs)




ECE 667 - Synthesis & Verification - Lecture 1                                             9
                              Two-level Logic: PLA

     • Logic represented as a two-level AND-OR structure
                                                              Product terms

                                                      x0 x1
                                                       x2
                                      AND                              OR
                                      plane                           plane




                                                                 f0           f1


                              x0          x1     x2

ECE 667 - Synthesis & Verification - Lecture 1                                     10
                 Programmable Logic Array (PLA)
           Pseudo-NMOS PLA
                                                                              VDD
               GND           GND                 GND    GND
                                                                              GND




                                                                              GND




                                                                              GND




           VDD             X0      X0       X1    X1   X2     X2   f0   f1

                                  AND-plane                        OR-plane

ECE 667 - Synthesis & Verification - Lecture 1                                      11
                 Two-Level Logic Optimization
                                                 Every logic function can be
                                                 expressed in sum-of-products
                                                 format (AND-OR)



                                                  minterm




     Inverting format (NOR-NOR)
     more effective


ECE 667 - Synthesis & Verification - Lecture 1                              12
                            Multi-level Logic
     • Logic represented as a network of logic gates
       from cell library
            – Logic decomposition (multi-level network)
            – Technology mapping
                                                 NAND21i

                                                           NAND3




                                      AOI21
                                                                   NAND2i




ECE 667 - Synthesis & Verification - Lecture 1                              13
             Cell-based Design (standard cells)




                                                 Routing channel
                                                 requirements are
                                                 reduced by presence
                                                 of more interconnect
                                                 layers




ECE 667 - Synthesis & Verification - Lecture 1                          14
 Standard Cell Layout Methodology – 1980s


         Routing
         channel
                                                 VDD



         signals



                                                 GND



ECE 667 - Synthesis & Verification - Lecture 1         15
                              Standard Cell - Example




                                                 3-input NAND cell
                                                 (from ST Microelectronics):
                                                 C = Load capacitance
                                                 T = input rise/fall time



ECE 667 - Synthesis & Verification - Lecture 1                                 16
                  Standard Cell – New Generation



                                                 Cell-structure
                                                 hidden under
                                                 interconnect layers




ECE 667 - Synthesis & Verification - Lecture 1                    17
                        Semicustom Design Flow
                                                     Design Capture    Behavioral

                                                          HDL
                                   Pre-Layout
                                   verification                        Structural
                                                     Logic Synthesis
     Design Iteration




                                                     Floorplanning
                                   Post-Layout
                                    simulation         Placement       Physical

                                Circuit extraction      Routing


                                                       Tape-out

ECE 667 - Synthesis & Verification - Lecture 1                                      18
                                             Verification
     • Design verification = ensuring correctness of the design
            – against its implementation (at different levels)
            – against alternative design (at the same level)


           model                                 ?    Design 1          Design 2
                                                                    ?
                           behavior                   HDL / RTL             RTL
                                                 ?
                            function                  Logic level        Logic level
                                                 ?
                                                                    ?
                           structure                  Gate level         Gate level    ?
                                                 ?
                               layout                 Mask level         Mask level

ECE 667 - Synthesis & Verification - Lecture 1                                          19
                The “Design Closure” Problem




          Iterative Removal of Timing Violations (white lines)



ECE 667 - Synthesis & Verification - Lecture 1                       20
                                                 Courtesy Synopsys
    Integrating Synthesis with Physical Design

                                                 RTL (Timing) Constraints



                                           Physical Synthesis


               Macromodules                                                  Netlist with
               Fixed netlists                                            Place-and-Route Info




                                             Place-and-Route
                                               Optimization

                                                                Layout
ECE 667 - Synthesis & Verification - Lecture 1                                                  21

								
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