project21 final paper

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					     Quantum Cryptography
        Matthew Brenner
         Brian Ricconi

          FALL 2002

      TA: Russell Schreiber
         Project No. 21

The design of a modulator and demodulator via a one-shot method with a maximum system delay of 400
ns and a maximum demodulator delay of 100 ns is presented in this report for an application to quantum
cryptography.    The modulator receives three sets of two inputs, each set corresponding to the
polarization basis of a photon. The signal is then modulated by a series of pulses relating to the
polarization basis. This newly generated signal is output to a laser, which pulses when the input to it is
pulsed. At the other end of the link, a photodetector transforms the optical signal back to an electrical
one. The output from the photodetector (the receiver) then feeds into our demodulating circuit, which
demodulates the pulsing signal back to a single pulse on one of three lines corresponding to the
polarization basis that was sent. Overall, the maximum delay of the modulator was measured to be 235
ns and the maximum demodulator delay was 44 ns therefore meeting the required specifications.

                                                  TABLE OF CONTENTS

1. INTRODUCTION ..................................................................................... 1
   1.1 Background Information .......................................................................1
   1.2 Project Benefits/Functions .....................................................................3
   1.3 Project Description/Specifications .........................................................3
2. DESIGN PROCEDURE ............................................................................ 5
   2.1 Modulation Scheme Decisions ..............................................................5
   2.2 Basic Design ..........................................................................................5
   2.3 Original Design ......................................................................................6
   2.4 Final Design ...........................................................................................9
3. DESIGN DETAILS ................................................................................. 10
   3.1 Input Stage ...........................................................................................10
   3.2 Modulator.............................................................................................11
   3.3 Demodulator ........................................................................................12
   3.4 Delay Times .........................................................................................13
4. DESIGN VERIFICATION ...................................................................... 16
   4.1 Preliminary Testing ..............................................................................16
   4.2 Total System Delay ..............................................................................16
   4.3 Modulator Delay ..................................................................................17
   4.4 Low Input Voltage ...............................................................................18
5. COST ANALYSIS ................................................................................... 20
6. CONCLUSIONS........................................................................................21
   REFERENCES ..........................................................................................22

                                           1. INTRODUCTION

1.1 Background Information
Quantum cryptography is a quantum mechanical approach to cryptography, the art of code sending.
Alice represents the person trying to send data, Bob is the receiver, and Eve is the eavesdropper who
tries to penetrate the system to steal information. In classical cryptography, information is only sent
over a public channel. However, in quantum cryptography, information is sent via a public and a
quantum channel as shown in figure 1 [1].

                          Figure 1. Cryptography Scenario

The purpose of all cryptography methods is for Alice to send what is called a “key” to Bob without Eve
figuring out what the key is. The key is necessary in order to decode the seemingly random information
sent over the public channel. In quantum cryptography, the key can only be figured out by tapping into
the quantum channel.

Alice sends a single photon via the quantum channel to Bob. The photon can be polarized in three
different bases with a total of six types of polarization, which can be seen in figure 2.

                                 Figure 2. Polarization Basis

Alice also sends Bob the polarization basis over the public channel so that Bob knows how to measure
the photon to figure out the photon’s exact polarization. The key is then created as a random number by
having a quantum entangler randomly create photons with different polarizations and generating each bit
of the key according to the polarization of the photon. As the key is created it is added to the bit
representation of the information, which is still a random number, and sent via the public line to Bob.
Therefore, Bob receives over the quantum channel:

   1. The photon with one of six polarizations.

And over the public line:
   1. The polarization basis used to measure the photon.
   2. The information + key (appears as random number).

With this information, Bob can recover the data that was sent. He simply takes the photon sent over the
quantum channel and measures it using the correct polarization basis which was sent over the public
line. He can then recover the bits of the key. He then takes the (information + key) and subtracts the
key, which gives him the information.

Eve is prevented from retrieving the key because she cannot tap into the quantum channel without being
noticed. If she taps into the quantum line to measure the photon, she can obtain a correct bit of the key,
but by the non-classical results of quantum mechanics, she cannot copy the photon and resend it.
Therefore, that bit of the key + information will be lost and will not enter the key, still ensuring a secure
system. If Eve only takes the polarization basis of the photon from the public line and does not tap into
the quantum channel, she will only know the polarization of the photon with a 50% probability. She
will then have to go through all the possible combinations of information and pick the one that she
thinks is most likely the transmitted message. The number of combinations scales as 2n, where n is the
number of photons sent. Eve still cannot obtain the key and thus cannot tap into the system.

1.2 Project Benefits/Functions
With the design of a low-delay modulator and demodulator, this system can be completed and the
product would be a cryptography machine that has application in numerous areas. It can be used in the
military arena to transmit positions, codes, and attack strategies. A cryptography machine can also be
used in the business domain to send secret designs and new technologies and to transmit codes to
financial institutions. The quantum cryptography system will even have applications in the public arena
and can be used in remote garage door openers, remote locking of automobiles, and secure remote
internet connections.

The completed design of the quantum cryptography system will enable the intended customers to have
peace of mind knowing that sensitive data cannot be tapped into. Also, passwords will not need to be
changed as often and customers will never have to deal with the hassle of recovering stolen data. In
addition to a completely secure communications line, our system can operate at a variety of frequencies,
and at very high frequencies, the total delay is much less than 400ns, thus allowing a high information
transmission rate.

1.3 Project Description/Specifications
Our project was to build a modulator and demodulator to transmit the photon measurement basis via the
public line. The block diagram can be found in figure 3.

                             Figure 3. Project Block Diagram

The input is going to be a single pulse consisting of a 5 V square wave with a ~30 ns pulse width. The
input will come on one of the 6 possible input lines and the next input will not arrive until the previous
input has traversed the circuit far enough so as not to interfere with the signals of the next.

Once the signal is received, it will then enter the box labeled “Or Basis With Error Detection Logic”.
The purpose of this box is to ensure that only one signal is high at a time and to “OR” the signals of the
different polarization basis together. This stage of the system will guarantee that two signals do not
register a high input at the same time. The quantum cryptography system will never have more than two
inputs high at the same time, so all other cases didn’t need to be considered. However, if only one
signal is high the output will be a high on the line corresponding to the basis that the input signal came
in on.

Once the 6 inputs are combined to be on 3 lines corresponding to the polarization basis, the signals enter
the modulator. The modulator was split up into three subcomponents, which are all similar in design
and correspond to one of the particular polarization basis. The modulating scheme will be to encode the
basis measurement as a series of pulses. Each subcomponent, C, H/V and D, will have a different series
of pulses. The output of all 3 subcomponents will then be combined and be sent as the output of the

This output will be received as the input of the laser. The laser will transform this electrical signal to an
optical one which will be received by the photodetector. The photodetector will proceed to transform
the optical signal sent by the laser back into and electrical signal of the same shape. This signal is the
input to the demodulator.

The demodulator, which must have a delay of less than 100 ns, will receive the output of the
photodetector, which will be of the same waveform as that created by the modulator. The purpose of the
demodulator is to convert the series of pulses back to a single signal on the output line corresponding to
the polarization basis represented by the series of pulses. The output pulse should be a square wave of
~1 V with no specification on the length of the pulse.

                                       2. DESIGN PROCEDURE

2.1 Modulation Scheme Decisions
One of the first and most important decisions we needed to make was to determine the modulation
scheme our design should use. As designers, usually we would choose between phase modulation and
amplitude modulation, but in this situation, phase modulation could be quickly ruled out. It is nearly
impossible to phase modulate a cheap laser pointer and the photodiode receiver1 does not provide the
demodulator with any phase information, so phase modulation in this system is impractical. Next, we
determined the type of amplitude modulation the circuit should use. The circuit could use on-off keying
or a multilevel amplitude system. Preliminary tests using the transmitter and receiver showed that the
output voltage from the receiver varied greatly depending on small changes in the alignment of the laser
and the distance between the laser and receiver. We didn’t expect the distance dependence, though we
hypothesized it happened due to absorption and scattering in air and the inability to focus the light
exactly on the photodiode as the distance between the two increased. Therefore, the best type of
modulation for this system is binary on-off keying, which we used digital logic to encode.

2.2 Basic Design
We then determined how to design the “OR Basis With Error Detection Logic” box, which will from
now on be referred to as the Input Stage. To do this, a multilevel system of XOR gates was employed
which output a “1” when one of the six signals was high and a “0” when 0 or 2 of the inputs were high.
Whenever the output of this block was high we were confident that there was no error and could begin
sending the modulated signal.

These three signals then fed into the 3 subcomponents of the modulator as can be seen in Figure 4.

                               Figure 4. Modulator Layout

 This project was not concerned with the laser and receiver design. Both components were built by a
previous senior design group.
Each subcomponent sends a different modulated signal. Table 1 lists the pulse sequence corresponding
to each of the polarization basis.

                                               TABLE 1.
  Polarization Basis            Base Sequence               Original Design               Final Design
        Circular                       001                       10011                        1001
          H/V                          010                       10101                        1010
       Diagonal                        100                       11001                        1100

In both the original and final design, the leading “1” acts as a start bit. In the original design, a “1” was
placed at the end to signal to the demodulator that the sequence of bits was ending. After rethinking
through the choice of modulation, we realized this bit was completely unnecessary, so it was dropped in
our final design. The final modulated scheme was chosen over a 3-bit modulation scheme to it would
not suffer from many false positive signals. We specifically wished to avoid the cases where our signal
was only one high bit or where it was all high bits. The errors that are likely in the quantum
cryptography system are single-bit errors that may be present in any system or a constant error that may
be caused by another reflected laser in the lab causing the photodiode to register a constant high output.

When the input was a specific series of pulses, the demodulator would output a pulse corresponding to
that series. For example, if the input to the demodulator for the final design was a 1010, an output
would be sent on the middle line telling Bob that the H/V polarization basis was being used. Because
our demodulator needed to recognize specific series of pulses, this led us to first design the modulator
and demodulator using a state diagram, which would eventually be a circuit consisting of TTL logic
gates and flip-flops.

2.3 Original Design
Our original design relied on a state machine consisting of 6 states. The modulator state diagram for the
1“001”1 example case is shown in Figure 5.

                         Figure 5. Original Modulator State Diagram

State A is the ground state. When no input comes in, nothing happens. Once the input goes high, we
move onto state B and output the first “1”. After this, we traverse through states C, D, E, each time
outputting either “001”, “010”, or “100” depending on which the path the specific sub-modulator is on.
In this case, we output a “001”. Finally, on the transition to state F, the last ending “1” is outputted and
we remain in state F until the input goes low at which point we return to the ground state, state A and
await another input. The circuit corresponding to this state diagram can be found in figure 6 and will not
be discussed in detail.

                            Figure 6. Original Modulator Circuit

We expected the three D flip flops in the middle of the circuit because we had 6 states and needed 3 bits
to represent them. Outputs 2 and 3 in the circuit above can be ignored, as the circuit above is only for
the 10011 case. However, the 10101 case would have an identical, but separate circuit with an output on
line 2 (ignoring outputs 1 and 3). The 11001 case would also have an identical, but separate circuit with
an output on line 3 (ignoring outputs 1 and 2).

The demodulator state diagram was constructed in a similar, but reversed manner and can be seen in
figure 7.

                     Figure 7. Original Demodulator State Diagram

As before, state A is the ground state and we stay in it until a signal comes in from the photodetector.
Once the signal comes in we move to state B. At this point, a branch occurs in the state diagram. We
branch to state C if the next bit (the first bit of the base code) is a “1” and move to state F if the next bit
is a “0”. If we move to state C, we then continue to move to state D, then state E. Once in state E, we
jump back to state A (the ground state) and output a “1” on the line corresponding to “11001”. If earlier
we branched to state F, we then decide to either go to state G or state I depending on if the next bit is a
“1” or a “0”. If at this point we branch to state G, we then continue to traverse the circuit to state H and
then on the HA transition, we output a “1” on the line corresponding to “10101”. If we earlier ended
up in state I, we then move to J and on the JA transition, we output a “1” on the line corresponding to
“10011”. The circuit corresponding to the demodulator state diagram can be found in figure 8.

                             Figure 8. Original Demodulator Circuit

Again, notice that 4 D flip-flops are necessary because we used 10 states, which require 4 bits.

Overall, this design outputted the correct waveforms and therefore proved to function correctly, but with
more delay than allowed. The specifications given for this project allowed maximum delay in the
modulator to be 300 ns, and this design operated with a minimum delay of 415 ns. It was noticed that
by increasing the frequency, the delay time could be reduced. Theoretically, the modulating circuit
should have functioned up to 26 ns pulses (38 MHz) before violating the setup and hold times of the
flip-flops (which would have given us a delay of ~225 ns), but due to impedance mismatching and some
bizarre high frequency effects, the circuit only operated up to a fluctuating 16-24 MHz, which gave us
delays above 300 ns. The circuit was also difficult to debug because the act of measurement disturbed
the system and caused 5 V signals to drop to 3 V. Therefore, a new and simpler design was needed.

2.4 Final Design
The second design we considered was quite different from the first. The three signals sent in this design
are 1100, 1010 and 1001. Because the signal is shorter, the completed signal will arrive at the
demodulator more quickly than in the previous design. The state machine model for the modulator was
abandoned, instead opting for a model shown in Figure 9. The “Pulser” block in Figure 9 is simply a
circuit that outputs a single-clock-cycle pulse each time it receives a rising edge from the Input line.
The model shown in Figure 9 will transmit the 1001 signal, but it is easy to see that the concept can be
extended to the two remaining signals.

Figure 9. Block Diagram of Modulator                    Figure 10. Block Diagram of Demodulator

The demodulator’s model was also changed. The new model, shown in Figure 10, allowed us to remove
the logic and delay that was in the synchronous path. Figure 10 shows the demodulation in the 1001
case. This demodulator requires three clock cycles between the end of the first signal and the beginning
of the second signal to ensure proper output. Although this feature lowers the maximum transmission
rate with respect to the clock frequency, this design was chosen because it may be run at a higher clock
frequency. The demodulator will have approximately the same clock frequency limit as the modulator.
The slight increase in clock frequency and subsequent decrease in delay is much more important than
the slight increase in transmission rate provided by a state-machine based demodulator, so this design
was chosen to be our final implementation.

                                                            3. DESIGN DETAILS

3.1 Input Stage
The incoming signals first had to be paired together and checked that two of the inputs are not high at
the same time. This was accomplished by using the input stage shown in Figure 11. This circuit was
carefully simulated to ensure it would meet our needs. The simulation of this circuit, showing that it
performs the way we expected, is shown in Figure 12. This circuit ensures that the modulator will get a
rising edge only if a signal should be sent. The buffer XOR gate (the one that has one input tied to low)
is included to make each path in the diagram from input to output have approximately equal delay.
Without this gate, a pulse with length at least 3 ns longer than it should be would result.

                                                       Figure 11. The Input Stage

 /LeftCircular      +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +           +

/RightCircular      +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +

   /Horizontal      +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +

      /Vertical     +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +

    /+Diagonal      +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +

    /-Diagonal      +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +

      /Circular     +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +

          /Axial    +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +

      /Diagonal     +    +    +     +    +       +    +     +    +     +      +     +     +     +     +     +     +     +     +     +     +     +
                   0.0       20.0       40.0         60.0       80.0        100.0       120.0       140.0       160.0       180.0       200.0

                                               Figure 12. Simulations of the Input Stage

3.2 Modulator
The pulser circuit, mentioned in Section 2.4, was designed completely from its specifications. It needed
to take an input with a single rising edge and output a pulse that had a duration of a single clock cycle.
If that input were synchronous and it was fed to the input of a D flip-flop, a very simple implementation
of this circuit results. A single AND gate can be connected to the input and the inverted output of the
flip-flop. This implementation also simplifies the delay path for the modulator because each of the flip-
flops can also serve as unit delays. Figure 13 shows the complete modulator design.

                                                                                                                                                                                            V1                      11 A



              U16A                                U16B                                   U17B                                   U17A                       U18A                  5Vdc                               12 B
                                                                                                                                                                                                                    13 C




             2                           5    12                            9        12                       9              2                     5   2                    5                                        2 D
 PAIR2               D           Q                     D            Q                         D           Q                        D           Q             D          Q                                            3 E           8
             3                           6    11                            8        11                       8              3                     6   3                    6              0                         4 F       Y




   CLK               CLK Q                             CLK Q                                  CLK Q                                CLK Q                     CLK Q                                                   5 G
                                                                                                                                                                                                                     6 H
             74F74                                74F74                              74F74                                   74F74                     74F74                                                         9 I





                                                                                                                                                                                 1                                                 1 U34A
                                                                                                                                                                                11 A                                               2



             U19A                             U19B                               U20B                                 U20A                                                      12 B                                     Vcc                              6
                                                                                                                                                                                13 C                                               4




         2                           5       12                         9       12                        9       2                    5                                         2 D                                               5
 PAIR1           D         Q                       D          Q                      D          Q                       D          Q                                             3 E             8                                                74F20
         3                           6       11                         8       11                        8       3                    6                                         4 F       Y




                 CLK Q                             CLK Q                             CLK Q                              CLK Q                                                    5 G
                                                                                                                                                                                 6 H
         74F74                               74F74                              74F74                             74F74                                                          9 I





                                                                                                                                                                                                                                       11 A
                                                                                                                                                                                                                                       12 B
                                                                                                                                                                                                                                       13 C





             U21A                                 U21B                                   U22B                                   U22A                       U23A                                U23B                                     2 D
                                                                                                                                                                                                                                        3 E               8






         2                           5        12                            9        12                       9              2                     5   2                    5              12                   9                       4 F        Y
PAIR3            D         Q                           D            Q                         D           Q                        D           Q             D          Q                        D          Q                           5 G
         3                           6        11                            8        11                       8              3                     6   3                    6              11                   8                       6 H






                 CLK Q                                 CLK Q                                  CLK Q                                CLK Q                     CLK Q                               CLK Q                                  9 I
                                                                                                                                                                                                                                       10 J
         74F74                                    74F74                              74F74                                   74F74                     74F74                               74F74                                          K






                                                                                                    Figure 13. Modulator Circuit

The chips on the right of the diagram are 74F64 ICs, which are 4-2-3-2 input AND/OR-INVERT chips.
These chips were used because it has a small maximum delay of 6.5 ns and the chips needed for an
implementation as discussed above are not manufactured. The excess inputs on the chip are tied to the
signal ground so the output of the chip will change as expected when the inputs change.

The flip-flops that we used in the circuit had a minimum setup time of 3 ns and a hold time of 1 ns.
These values mean that an input to the flip-flop must be stable before and after a rising clock edge by 3
ns and 1 ns, respectively. We could not guarantee that the input pulse would have this intrinsic property,
so we stabilized the signal by adding an extra two D flip-flops before we would consider the output to be
synchronous and stable. This is equivalent to assuming the output of the first flip-flop will have
stabilized by about one clock cycle later, which is a decent approximation. We had no problems with a
circuit missing any input pulses or sending multiple inputs, which would have happened about once in
every 10 input pulses if this assumption was invalid.

Figure 14 shows a simulation of the modulator, which shows this implementation works exactly as it

   /CLK +       +    +     +     +     +     +     +     +     +     +        +     +     +     +     +     +     +     +     +     +     +     +

/Input1    +    +    +     +     +     +     +     +     +     +     +        +     +     +     +     +     +     +     +     +     +     +     +

/Input2    +    +    +     +     +     +     +     +     +     +     +        +     +     +     +     +     +     +     +     +     +     +     +

/Input3    +    +    +     +     +     +     +     +     +     +     +        +     +     +     +     +     +     +     +     +     +     +     +

/Signal    +    +    +     +     +     +     +     +     +     +     +        +     +     +     +     +     +     +     +     +     +     +     +
          0.0       50.0       100.0       150.0       200.0       250.0          300.0       350.0       400.0       450.0       500.0       550.0

                                                 Figure 14. Simulation of Modulator

3.3 Demodulator
The demodulator will receive the modulated signal and output a single pulse based on which signal it
receives. This is accomplished by constructing a memory to store the previous four received bits and
comparing the four stored bits to the three valid signals. If the stored signal matches one of the valid
sequences, the system outputs a high pulse on the corresponding line that stays high for at least one
clock cycle and less than two clock cycles. Figure 15 shows the circuit that implements this function.

The lower memory block with the delayed input needed to be implemented in case the signal and the
clock inputs had rising edges around the same times. The setup or hold time of the first flip-flop may be
violated in that case, which results in unstable output for the first flip-flop. Again, as in the modulator,
we assumed that the outputs after the first flip-flop would be stable, so the circuit would not create an
unpredictable series of high pulses which may be interpreted as valid signals. However, this circuit
could not afford to lose the signal because its rising edge was about the same time as the clock’s rising
edge, which necessitated the buffers. At the end of the stage, the two outputs corresponding to the same
sequence were paired together to create an output pulse if either one registers a correct sequence. This
circuit was also tested to ensure that both lines operated correctly. As before, a setup or hold time
problem would have occurred about 10 percent of the time, but the output was always correct, so the
circuit apparently served its purpose.

                                                                                                                                                                                                  1 U13A



                               U1A                                   U1B                                   U2A                                   U2B                                              5




                           2                     5               12                       9            2                            5        12                       9
                                   D         Q                           D            Q                         D           Q                        D            Q                                                                              U7C
                           3                     6               11                       8            3                            6        11                       8                           13 U13B                                   10




                                   CLK Q                                 CLK Q                                  CLK Q                                CLK Q                                        12                                                           8
                                                                                                                                                                                                                    8                       9
                           74F74                                 74F74                                 74F74                                  74F74                                               10


                                                                                                                                                                                                   9                                                   74F00



                                                                                                                                                                                                  13 U14B                                        U7B
                                                                                                                                                                                                  12                                        4
                                                                                                                                                                                                                    8                                          6
                                                                                                                                                                                                  10                                        5
                                                                                                                                                                                                            74F20                                      74F00

                                                                                                                                                                                                            1 U15A
                                                                                                                                                                                                                                6                U7A
        U36A                                                                                                                                                                                                4                               1



  1                            U36B                          U3A                               U3B                                      U4A                                U4B                              5                                                  3
                       3                                                                                                                                                                                                74F20               2



  2                                                  6       2                        5       12                            9           2                         5       12                  9
                       5                                         D          Q                          D          Q                          D          Q                      D          Q             13 U15B                                        74F00
               74F86                                         3                        6       11                            8           3                         6       11                  8         12



                                             74F86               CLK Q                                 CLK Q                                 CLK Q                             CLK Q                                            8
                                                             74F74                            74F74                                     74F74                             74F74                          9


        0                      0

                                                                                                                                                                                                            1 U14A

                                                                                                       Figure 15. Demodulator Circuit

        /CLK +                     +                     +                  +                      +                            +             +                       +             +             +             +               +     +      +

  /Signal       +                  +                     +                  +                      +                            +             +                       +             +             +             +               +     +      +

/Circular       +                  +                     +                  +                      +                            +             +                       +             +             +             +               +     +      +

      /Axial    +                  +                     +                  +                      +                            +             +                       +             +             +             +               +     +      +

/Diagonal       +                  +                     +                  +                      +                            +             +                       +             +             +             +               +     +      +
               0.0                               100.0                                        200.0                                         300.0                              400.0                        500.0                   600.0

                                                                                                       Figure 16. Demodulator Simulation

3.4 Delay Times
The circuit would have been useless had it not operated with a short enough delay, so a theoretical worst-case
delay analysis is presented here. Table 2 lists the delay parameters for the various chips we used in our design.
The maximum delay of the input stage is the same for any input to output. These numbers were extracted from
the datasheet as the maximum delay at room temperature with a 5.0 V supply voltage and a load capacitance of 50

The maximum delay of the input stage is independent of clock frequency and is 26.6 ns.

To compute the maximum delay of the modulator, you must consider that the input is received at the D flip-flop
just after its setup time. Therefore, a single clock period (CP) added to 3 ns needs to be added to the following
analysis. Also, note that the 1001 output takes the most time to complete because the other two lines were able to
be optimized for delay. The last output comes from the string of D flip-flops 5 clock cycles later, plus the 8 ns
propagation delay of the flip-flop. Then the output is delayed further by a 74F64 and 74F20 before leading to the
laser. The calculation of delay in nanoseconds and clock pulses is as follows:

                                 p = CP + 3 + 5*CP + 8 + 6.5 + 5 = 22.5 + 6*CP

After the signal is completely sent, it is received as an input to the modulator 40 ns later by the tests mentioned in
Section 4. The demodulator’s worst-case input instant is when the input is received just after the setup time of the
flip-flop, adding one CP to the delay in the worst-case. After that value is clocked in, the circuit has only
asynchronous delay left. The calculation for total delay of the receiver and demodulator is given by:

                                        p = 40 + CP + 8 + 5 + 5 = 58 + CP

The two values given above add to the receiver delay to give the total propagation delay of the system as:

                              p,total = 26.6 + 22.5 + 6*CP + 58 + CP = 107.1 + 7*CP

This equation for the demodulator and receiver delay, when coupled with the requirement that the delay of the
receiver and demodulator must be less than 100 ns, governs that the clock period be less than 47 ns. However, the
governing requirement is that the system delay be less than 400 ns, which means the clock pulse must be less than
41.8 ns. That translates into a clock frequency of about 23.5 MHz, which means our circuit must function at
greater than 23.9 MHz to ensure a delay of less than 400 ns.

There is one further factor that is possibly a limiting factor on clock speed. If the pulse that comes out of the
input stage lasts less than (CP + 4 + 14) ns, there is no guarantee that the pulse will be seen by the D flip-flops of
the modulator. Therefore, for a 30 ns input pulse is only guaranteed to be always seen if the clock frequency of
the flip-flops is 83.3 MHz. This is not a problem because when the specifications were given to us, only the order
of the length of the pulse was specified, but an exact value was not given. If the pulse in the system were actually
45 ns long, a 37 MHz clock would guarantee the signal would be seen. The minimum clock duration for which
this consideration will not be the limiting factor is 59.8 ns.

The datasheet for the flip-flops claim they will operate up to 100 MHz, and all of the constraints given in this
section will be met if the clock frequency is far below that. The actual constraint for this system is less than 100
MHz because the propagation delay added to the setup time is greater than the 10 ns period of a 100 MHz signal.
Therefore, the maximum clock frequency for this circuit, according to the datasheet, should be 90.9 MHz.

                         TABLE 2.

IC Part Number   Function      Maximum Propagation Delay (ns)
74F00            NAND          5.0
74F08            AND           5.6
74F20            NAND          5.0
74F64            AND/OR/INV 6.5
74F74            D flip-flop   8.0
74F86            XOR           7.0

                                     4. DESIGN VERIFICATION

4.1 Preliminary Testing
Before the circuit was built, we drove the laser with a function generator to test the delay inherent to the
transmitter/receiver system. We performed the test at various frequencies between 1 kHz and 20 MHz
and noted that the delay was approximately constant over the entire range. The delay was determined to
be 35 ± 5 ns. This measurement put a constraint on our system that the demodulator must have a delay
less than 60 ns.

The first test the completed circuit underwent was to find the maximum clock frequency at which the
circuit would give a correct output. This test was performed each time the circuit was hooked up.
Generally, the modulator was tested first and separately from the demodulator. The frequency obtained
by this test always worked with the demodulator connected. The maximum clock frequency allowed by
the circuit was a nearly monotonically decreasing function of the number of days since the circuit had
been built. The clock frequency was 42 MHz the first time the circuit was tested, and a low of
approximately 24 MHz was observed weeks later. The large variance in this value may be due to the
deteriorating quality of connections on the protoboard, which may have been slightly pushed out of
place during the circuit's transportation. Also, some wires broke off in the protoboard which indicates a
lack of strength near the end of the wire. If a wire had been partially broken in the board, it may have
introduced a spurious capacitance which would delay the signal on that line. If the extra capacitance
was introduced on a synchronous path, if would cause the observed maximum clock frequency to be

The modem drew an average current of 170 mA from the power supply at a clock frequency of 30 MHz
when connected with a wire. This means the system dissipates 850 mW of power. This is a useful
specification to consider when determining the type of power supply that should be used for this system.

4.2 Total System Delay
After the maximum clock frequency for that testing session was determined, we tested various delay
times in the circuit. The most important delay time we tested was the system’s overall delay. These
values were tested by finding cables of the same length and composition to observe the signals on an
oscilloscope. Then, a square-wave input was fed to the input stage so the modulated signal would be
1001. The output of the demodulator and the input signal were observed on the oscilloscope to
determine the delay between the two rising edges. The data was taken in single trigger mode to ensure
an actual signal would correspond to the graph we displayed and no averaging was taking place. The
input impedance of the oscilloscope was set to 1 MW so it would not disrupt the input signal. We
manually triggered the oscilloscope rapidly to convince ourselves that the signal always appeared, and
after convincing ourselves the signal was always present, we downloaded several data sets to the
computer to analyze it. We repeated the process of downloading the data until a “worst-case” delay time
was found. Figure 17 shows this graph for a 32 MHz clock frequency and a 1 kHz input pulse. It shows
a delay of 259 ns between rising edges. This system was tested with a wire between the modulator and
demodulator, so this delay doesn’t incorporate the 35 ns that we previously measured inherent to the
receiver and transmitter. Still, the observed delays are less than the maximum theoretically calculated


The large amplitude of the oscillation in the time when the signal is low is due to the impedance
mismatch at the detector and the signal ground corrupting the supply ground. Other tests will be shown
later that solve these problems.

                            Figure 17. Worst-delay response of the system

4.3 Modulator Delay
The modulator with the input stage was also tested to find its delay independent of the demodulator.
Figure 18 shows a plot of the modulator response when it was sending a 1001 signal. The delay for the
modulator, which was measured as the time between the rising edge of the input and the falling edge of
the final “1”, was 235 ns at a clock frequency of 25 MHz.

The signals in the above tests are very noisy and unacceptable as outputs to the quantum cryptography
system. There are two obvious characteristics to those graphs: a modulation in the low signal and an
impedance mismatch as evidenced by the spikes after the high pulse output. The amplitude of the
modulation in the low signal was lessened by adding capacitors between the supply voltage and ground
at various points along the protoboard and by decoupling the signal and supply grounds by separating
the two and connecting them with an inductor. Also, we placed capacitors between the supply voltage
and ground to decouple the supply from the circuit. The outputs were taken across a 50 W output
impedance, the impedance of the system, to see the shape of the waveform in a 50 W system. The signal
was verified to be of the correct pulse duration and was observed to have a maximum around 2 V. The
outputs of the modulated signal and the demodulated signal are shown in Figure 19 and 20.

                  Figure 18. Worst-delay response of modulator

        Figure 19. Modulator Output               Figure 20. Demodulator Output

4.4 Low Input Voltage
We also tested for the minimum input signal that would correctly trigger the circuit to operate at its
maximum clock frequency. As Figure 21 shows, the minimum input that will allow the circuit to still
correctly function is approximately 3 V. Below this threshold, the signal was not generated. Notice that
the delay time is independent of the signal magnitude.

Figure 21. System delay at a low input voltage

                                         5. COST ANALYSIS

                                             TABLE 3.
                                           PART COSTS
   Part Description             Quantity                Unit Cost ($)        Amount ($)
   TTL D Flip Flop                  12                      0.41                  4.92
  TTL Invert/NAND                   3                       0.40                  1.20
 TTL 4-Input NAND                   5                       0.22                  1.10
     2-Input XOR                    3                       0.65                  1.95
    2-Input NAND                    3                       0.25                  .75
         PCB                        1                        383                  383
                                                                        Total Parts Cost = 392.92

Labor Cost = ($40/hour)*(110 hours)*(2 people)*(2.5) = $22,000

Total Cost = Total Parts Cost + Labor Cost = $393 + $22,000 = $22,393

Total Cost = $22,393

                                           6. CONCLUSIONS

The circuits built for the modulator and demodulator met the delay requirements imposed on them at
even lower clock frequencies than we calculated. The fluctuations we observed in the maximum clock
frequency leads us to the conclusion that this circuit must be moved out of a protoboard and onto a
printed circuit board (PCB) so the maximum clock frequency will not vary. The circuit that realizes this
function is built of very cheap 74F TTL parts. The maximum observed delay shows that the system may
be run at a very high signal repetition rate, greater than 2 MHz. The performance achieved by this
system should be adequate to encounter no problems in the integration of the system into the quantum
cryptography system.

However, before integration into this system, the receiver and transmitter need to be made functional
and verified that they will accept TTL outputs. We have confirmed the laser will accept TTL outputs
and output pulses based on the input, but we were not able to verify the form of the output wave.


1. Tittel, W., Ribordy, G., and Gisin, N, "Quantum Cryptography," Physics World, pp. 240-244,

   March 1998.


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