Bus Systems by 2m18Zj

VIEWS: 14 PAGES: 39

									             PC Bus Technology
                          George South

          Note: the same buses are used for many other
          computer systems especially x64 servers – see
          also DDR3 notes
12 September 2012         PC Bus Technology               1
1. Introduction (see X58, H55, Q57 diagrams)
Overview
  A PC can be considered to be a number of
  processing and peripheral units joined
  together by buses
• There are many internal buses in, say the
  processor, but the bus technology discussed
  here relates to buses external to the
  processor
• See the full size chipset diagrams in the notes
  – identify the buses e.g. PCI, PCI Express, QPI

12 September 2012   PC Bus Technology               2
2. Typical modern PC buses
•   PCI
•   PCI Express e.g. x1, x16
•   FSB Front Side Bus
•   DMI Direct Media Interface
•   QPI QuickPath Interconnect (Intel)
•   HyperTransport (AMD)
•   SATA/ SAS
•   USB 1.1/ 2.0/ 3.0
•   Firewire
•   RAM Interface DDR/ DDR2/ DDR3
12 September 2012      PC Bus Technology   3
3. Parallel vs Serial buses
• All the original adapter buses in the PC
  architecture were parallel e.g.
     – PC-bus (5 MHz/ 8-bit) / ISA-bus (8 MHz/ 16-bit)
       PCI-bus (33 MHz/ 32-bit) / AGP (66 MHz/ 32-bit)
     – Parallel buses can be high performance
     – However as the frequency increases so does the
       problem of crosstalk – each signal line acts as both a
       transmitting and a receiving aerial
     – The frequency limit of such buses with very careful
       layout and complex signalling is about 1000 MHz

12 September 2012          PC Bus Technology                    4
4. Parallel vs Serial buses
• Modern interface buses in a PC are serial
• Serial buses can operate at high speeds using
  differential transmitters and receivers to
  reduce the effects of crosstalk .. Add a sketch
• Examples include
     –   PCI Express: a multi-lane serial bus
     –   SATA: a serial bus for disk drives ..also SAS
     –   QPI: a high speed interconnection bus ..more
     –   HyperTransport: a high speed interconnection bus ..more

12 September 2012           PC Bus Technology                      5
5. Limitations of a parallel bus
• A typical example of a classic PC parallel bus is
  the AGP bus
• It operated at 66 MHz and was 32-bits wide
• AGP bandwidth =        66 MHz times 32 bits
                         2112 Mbits/sec
• Versions of AGP which allowed multiple transfers
  within the basic clock cycle were termed 2x/ 4x/
  8x
• 8x signalling gives approximately 2 GBytes/sec

12 September 2012    PC Bus Technology                6
6. Bandwidth for PCI Express v1.x
• PCI Express (version 1.0) operates at 2.5 Gbit/sec
• Each lane incorporates a transmit and a receive path
• So each lane can transfer 2.5 Gbits/sec in each direction
  or 5 Gbits/sec in total (usually written as 5 GT/sec)
• This corresponds to 4000 Mbits/sec or 500 MByte/sec
  since the 8B/10B coding used requires 10-bits for every
  8-bit byte transferred
• So a 16 lane system will operate at a maximum rate of 8
  GBytes/sec
• PCIe version 2.0 doubles the frequency and data rate
• PCIe version 3.0 doubles the data rate ..more


12 September 2012        PC Bus Technology                    7
7. SATA - Serial ATA
• Disk drive interfaces traditionally used 16-bit parallel
  technology called ATA Advanced Technology Attachment
• The maximum operating frequency was 66 MHz called ATA133
• Most disk drives on PCs now use a serial interface - SATA
• SATA was introduced with a data rate of 1.5 Gbits/sec SATA 1.0
• This corresponds to 150 MBytes/sec because of the 8-bit/10-bit
  coding ..more
• Modern hard disks can probably handle data rates of 130
  MBytes/sec (Flash disks higher)
• SATA Revision 2.0 doubles the data rate (SATA 3Gbits/s)
• The SATA cable has 4 data lines (providing two data channels )
  and 3 grounds .. Requires additional power cable


12 September 2012        PC Bus Technology                   8
8. The FSB - Front Side Bus
• The FSB Front Side Bus was the classic parallel
  interface to microprocessors
• A front side bus might have a clock of 200 MHz
  and perform four transfers per clock (quad
  pumping) – this is termed 800 MT/sec
• In desktop processors, the FSB technology
  peaked at about 266 MHz when Quad Pumped
  corresponding to 1064 MT/sec
• Core i3/ i5/ i7 processors do not use FSB
  technology (Core 2 Duo and original Atom use FSB)
12 September 2012     PC Bus Technology               9
9. QPI - QuickPath
• The Front Side Bus was the classic interface to
  microprocessors
• FSB technology is limited because it is parallel
• An alternative interface technology is
  HyperTransport - however Intel developed its
  own high performance interface bus for:
     – Processor to motherboard e.g. Core i7 9xx
     – Processor to processor
     – Processor to peripheral etc
• QPI is processor independent
12 September 2012       PC Bus Technology            10
10. Bandwidth for QPI (QuickPath)
• QuickPath incorporates two 20-lane point-to-
  point data links (each lane has a transmit and
  a receive path) with a separate clock pair in
  each direction, for a total of 42 signals
• Each signal is a differential pair, so the total
  number of ‘pins’ is 84
• Data Rate for a 3.2 GHz clock =
  3.2 x 2 x 20 x (64/80) x 2 / 8 (bits/byte)
  = 25.6 GBytes/s .. Note: it uses DDR technology
12 September 2012    PC Bus Technology               11
11. DMI (see X58 and H55 diagrams)
• DMI Direct Media Interface is the classic Intel
  connection between the Memory Controller hub
  and the IO Controller hub
• It uses a data rate of up to 2 GBytes/sec
• It is typically implemented as two unidirectional
  lanes (as PCIe)
• Previous technology used a slower bi-directional
  interface
• Core i3, i5 and Core i7-8xx use DMI to connect to
  the Platform Controller Hub (see Q57 diagram)
12 September 2012    PC Bus Technology            12
12. Bandwidth for HyperTransport
• HyperTransport is a bus created by a consortium
  made of several companies, including AMD, nVidia
  and Apple
• HyperTransport can operate from 200 MHz to 3.2
  GHz ..more
• Uses differential signalling and DDR
• A 32 lane version of HyperTransport operates at (3.2
  GHz/link * 2 bits/Hz * 32 links * 1 Byte / 8 bits) per
  direction, or 51.2 GBytes/s aggregated bandwidth
  per link
• Applications - FSB replacement ..more
12 September 2012      PC Bus Technology               13
13. USB Technology
• Introduced as USB1.0 (upgraded to USB1.1) at
  1.5 and 12 Mbits/sec (1996)
• Targeted at replacing legacy peripheral
  interfaces Kb, Mouse, COM, LPT and being a
  useful interface for simple multimedia
  peripherals e.g. webcam
• USB2.0 at 480 Mbits/sec (2000)
• USB3.0 at about 5000 Mbit/sec (2008)


12 September 2012   PC Bus Technology        14
14. USB 2.0
• USB2.0 at 480 Mbits/sec
• Compatible with USB1.1 peripherals by
  detecting the version of USB and
  implementing USB1.1 and USB2.0 controllers
  as part of the chipset
• Very popular product
• 2 billion USB devices sold each year



12 September 2012   PC Bus Technology          15
15. USB 3.0 SuperSpeed
• USB3.0 at about 4800 MBit/sec
• Initially there was the prospect of two USB 3.x
  standards ..more
• USB 3.0 adds extra channels for high speed
  comms
     –
     –
     –
     –

12 September 2012   PC Bus Technology           16
16. USB 3.0 SuperSpeed Update
• Some motherboards are appearing with
  USB3.0 using a separate USB3.0 controller
  chip
• Initial USB3.0 peripherals have been marketed
  – these include
          • Disk Backup units
          •
          •
          •
• Comment on the products selected for USB3.0
12 September 2012           PC Bus Technology   17
17. SMBus System Management Bus
• A simple low performance serial bus used to
  allow interfacing to peripherals e.g.
     – system monitor chips (temperature/ fans etc)
     –
     –




12 September 2012       PC Bus Technology             18
   Chipset diagrams follow:

   • X58 – Core i7-9xx – high performance
   • Q57 - vPro, Active Management etc
   • P55 – no support for integrated graphics
   • H55 – budget ?
   • H57 – low end professional




12 September 2012   PC Bus Technology           19
                  X58 chipset – Core i7-9xx
       PCIe 2.0



                                                         3 channel
                                                   QPI   DDR3 RAM




                                                                    Note:
                                                                  Top of the
                                                                range Core i7



Gigabit LAN Connect Interface
   - LAN Connect Interface
    12/09/2012                  Nehalem Overview                         20
 Q57 – i7/ i5/ i3 – professional users



                                        Note support
                                         for Trusted
                                          Execution
                                         Technology
                                         and Active
                                        Management
                                         Technology
                                        vPro chipset



12 September 2012   PC Bus Technology           21
P55 Chipset - Core i5 and core i7-800




                                       Note:
                                   No support
                                  for integrated
                                     graphics
         H55 chipset – Core i7/ i5/ i3




                                                       Note:
                                                   No support
                                                   for RAID etc
                                                     budget
                                                     market ?
                          FDI - Flexible Display
                          Interface


12 September 2012   PC Bus Technology                       23
                      H57




                                           Note:
                                           OK for
                                        professional
                                         use if you
                                        don’t need
                                          vPro etc




12 September 2012   PC Bus Technology            24
12 September 2012   PC Bus Technology   25
12 September 2012   PC Bus Technology   26
Original Atom for Netbook
Revised Atom architecture
   Classic chipset

                     Core 2
    PCIe                         FSB
                                             DDR2
    x16                                      RAM
                              DDR2
                     MCH
                                      DDR2

    Display*
                                     DMI
                     IOCH            bus
Also
SMBus                                SPI
bus                  BIOS
                                     bus

  * Some chipsets have integrated graphics/
  some support PCIe x16 external graphics           29
      Core i7 9xx
                                                        DDR3
      chipset               e.g.         DDR3
                                                        RAM
                           Core i7          DDR3
                            920                  DDR3   8.5 GB/sec
   e.g. PCIe
   x16 or two               X58
                                                QPI (25.6
   PCIe x16                 IOH                 GB/sec)

                                             DMI bus
                            IOCH
                                             (2 GB/sec)

                            BIOS


IOCH supports 12 USB2.0 ports/ 6 SATA ports/ 6 PCI x1 ports/
Gigabit LAN/HD Audio/ Turbo RAM/ Matrix storage
                                                                30
Nahalem 2 chip solution                      DDR3
                                             RAM
                           IMC        DDR3
       PCIe                                  e.g. 2
                 e.g. Core i5                channels
       x16
                  GFX
FDI                                      DMI
                                         bus
 Display*
                 Display     NVRAM
                        MCH
                  ME             IO


* Some chipsets have integrated graphics/
some support PCIe x16 external graphics             31
          Figure 1. Typical Client System
                   Architecture




         http://www.dell.com/downloads/global/vectors/2004_pciexpress.pdf

12 September 2012                       PC Bus Technology                   32
         Figure 2. Bandwidth of Devices
               Serviced by PCI Bus




         http://www.dell.com/downloads/global/vectors/2004_pciexpress.pdf

12 September 2012                       PC Bus Technology                   33
  A PCI Express link consists of dual simplex channels, each implemented as a transmit pair and a receive pair for simultaneous
     transmission in each direction. Each pair consists of two low-voltage, differentially driven pairs of signals. A data clock is
 embedded in each pair, using an 8b/10b clock-encoding scheme to achieve very high data rates. Figure 4 compares the PCI and
                                                          PCI Express links.




12 September 2012                                     PC Bus Technology                                                          34
• The bandwidth of a PCI Express link can be
  scaled by adding signal pairs to form multiple
  lanes between the two devices. The
  specification supports x1, x4, x8, and x16 lane
  widths and stripes the byte data across the
  links accordingly. Once the two agents at each
  end of the PCI Express link negotiate lane
  widths and frequency of operation, the
  striped data bytes are transmitted with
  8b/10b encoding.
12 September 2012   PC Bus Technology           35
12. Bandwidth for HyperTransport
• HyperTransport is a bus created by a
  consortium made of several companies,
  including AMD, nVidia and Apple
• 200 MHz = 400 MT/s = 800 MB/s
• 400 MHz = 800 MT/s = 1,600 MB/s
• 600 MHz = 1,200 MT/s = 2,400 MB/s
• 800 MHz = 1,600 MT/s = 3,200 MB/s


12 September 2012   PC Bus Technology     36
             PCI Express Implementation

Encoded Data Rate /Unencoded Data Rate
• x1 5 Gbps 4 Gbps (500 MB/sec)
• x4 20 Gbps 16 Gbps (2 GB/sec)
• x8 40 Gbps 32 Gbps (4 GB/sec)
• x16 80 Gbps 64 Gbps (8 GB/sec)
• Table 2. PCI Express Bandwidth



12 September 2012     PC Bus Technology   37
                PCI Express technology
• PCI Express technology achieves high data rates
  reliably by using low-voltage differential signaling.
  In this approach, the signal is sent from the
  source to the receiver over two lines. One
  contains a “positive” image and the other, a
  “negative” or “inverted” image of the signal. The
  lines are routed using strict routing rules so that
  any noise that affects one line also affects the
  other line. The receiver collects both signals,
  inverts the negative version back to the positive
  and sums the two collected signals, which
  effectively removes the noise.
12 September 2012       PC Bus Technology            38
    http://www.lecroy.com/ProtocolAnalyzer/ProtocolStandard.aspx?standardID=3


•   PCI Express Overview
•   Peripheral Component Interconnect Express(PCIe) protocol was developed by
    Microsoft, Dell, IBM, Intel, and others in 2002. It was first called 3GIO but later
    became known as PCI Express. The PCI Express architecture is a state-of-the-art
    serial interconnect technology that keeps pace with recent advances in processor
    and memory subsystems. From its initial release at 0.8V, 2.5GT/s(Giga Transfers), to
    the newly announced Gen3 at 8GT/s the PCI Express technology roadmap will
    continue to evolve, while maintaining backward compatibility, well into the next
    decade with enhancements to its protocol, signaling, electromechanical and other
    specifications. The PCI Express architecture retains the PCI usage model and
    software interfaces for investment protection and smooth development migration.
    The technology is aimed at multiple market segments in the computing and
    communication industries, and supports chip-to-chip, board-to-board and adapter
    solutions at an equivalent or lower cost structure than existing PCI designs. PCI
    Express 2.0 currently runs at 5GT/s or 500MBps per lane in each direction,
    providing a total bandwidth of 16GBps in a 16-lane configuration which is the
    largest size in use.
•   PCI Express Gen3 will run at 8GT/s but will use a different encoding system to
    double the data rate but keep power consumption as low as possible.


12 September 2012                   PC Bus Technology                                 39

								
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