Sequential logic - PowerPoint by tgzIO6

VIEWS: 0 PAGES: 20

									Understanding Engineers #1
 The graduate with a Science degree asks, "Why does
  it work?"
 The graduate with an Engineering degree asks, "How
  does it work?"
 The graduate with an Accounting degree asks, "How
  much will it cost?"
 The graduate with an Arts degree asks, "Do you want
  fries with that?"




               CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 1
Understanding Engineers #2
 MS CS -- Soft-ware
 MS EE -- Hard-ware
 MBA -- Un-a-ware
 MFA -- No-ware




              CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 2
Midterm II
 THIS Thursday, 22 March (that is TWO days from today!),
  2:10 -- 3:30+, CS 150 Lab
 Lectures 10, 11, 12, (no lecture 13!), 14, 15, 16;
  Labs #4 and #5 (Debugging/Logic Analyzers) + Checkpoints #0
  and #1 (SDRAM + Video Encoder)
 Don’t forget: Spring 05/Fall 05 exams are on-line!
 5 x 10 point questions, mostly design-oriented
 Closed book, open crib sheet; PENCIL, not pen!
 Two review sessions: Tu 8 PM and W 8 PM in the lab
 NOTE: Discussion sections and lab lecture cancelled this week




                  CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 3
Sequential Logic Implementation
 Models for representing sequential circuits
    Mealy, Moore, and synchronous Mealy machines
    Verilog specifications for state machines
 Finite state machine design procedure
    Deriving state diagram from word specifications
    Deriving state transition table
    Determining next state and output functions
    Implementing combinational logic




                 CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 4
SDRAM Memory Controller
 Static RAM Technology
   6T Memory Cell
   Memory Access Timing
 Dynamic RAM Technology
   1T Memory Cell
   Memory Access Timing
 Theory in lecture, but practical detailed memory
  system organization and timing in Lab Checkpoint #0




               CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 5
Two-way Video Conferencing Project
 Project Concept and Background
 SDRAM Controller (Checkpoint #0)
 Video Encoder/Display System (Checkpoint #1)




              CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 6
Videoconferencing System Concept
     Video Decoder               Multiport SDRAM                     Video Encoder
                                 Memory System


    Camera
                                     SDRAM
                                 (Checkpoint #0)                      Display

           Videostream

      Video                         Multiport                    Video Encoder
     Decoder                       Arbitration                   (Checkpoint #1)



 Checkpoint #2


                            Wireless Transceiver
 Checkpoint #4                    (Checkpoint #3)

                     CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 7
Computer Organization
 Computer design as an application of digital logic design procedures
 Computer = processing unit + memory system
 Processing unit = control + datapath
 Control = finite state machine
     Inputs = machine instruction, datapath conditions
     Outputs = register transfer control signals, ALU operation codes
     Instruction interpretation = instruction fetch, decode, execute
 Datapath = functional units + registers
     Functional units = ALU, multipliers, dividers, etc.
     Registers = program counter, shifters, storage registers




                      CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 8
 Register Transfer
                        A           B           CA
      D   Sel0                                      Sel  0; Ld  1
Sel     0
      E
        1
      C
          Sel1
                                                CB
                                                    Sel  1; Ld  1
                                 Bus

          Ld
                            C                            Clk

                 Clk                                     Sel           A on Bus   B on Bus


                                                         Ld
                                                                       Ld C         ?
                                                                       from Bus
                       CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 9
Register Transfer
 Point-to-point connection
    Dedicated wires                         MUX            MUX           MUX   MUX

    Muxes on inputs of
                                               rs            rt           rd    R4
     each register
 Common input from multiplexer
    Load enables
     for each register
                                               rs             rt          rd    R4
    Control signals
     for multiplexer
                                                                   MUX
 Common bus with output enables
    Output enables and load
     enables for each register
                                               rs             rt          rd    R4


                                                                    BUS
                  CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 10
State Machine Implementation
 Alternative controller FSM implementation
  approaches based on:
   Classical Moore and Mealy machines
   Time state: Divide and Counter
   Jump counters
    Microprogramming (ROM) based approaches
      branch sequencers
      horizontal microcode
      vertical microcode




                 CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 11
Time State (Divide & Conquer)
                                                                     T0
         Time State FSM
Most instructions follow same basic sequence                         T1             Wait/

Differ only in detailed execution sequence
                                                                            Wait/

                                                                     T2             Wait/
Time State FSM can be parameterized by
   opcode and AC states                                                     Wait/

                                                                     T3         Wait/
                                                                            Wait/
                                       IR
                                                                     T4
Instruction State:
stored in IR<15:14>     =00     =01          =10     =11
                                                                               BRN • AC • 0/
                                                                     T5
                        LD        ST        ADD BRN                         (LD + ST + ADD) • Wait/
                                                                     T6
                                                                                    BRN + (ST • Wait)/
Condition State:
                              AC<15>=0                
                                                      0
                                                   AC •
stored in AC<15>                                                            (LD + ADD) • Wait

                      AC < 0                                         T7
                                        AC<15>=1
                      CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 12
Jump Counters

 Pure Jump Counter
    Inputs

                                                                    NOTE: No inputs to
                                                                     jump state logic
       Count, Load,              Jump State
       Clear Logic                 Logic

                    Clear
             Load
                                Synchronous
        Count                      Counter
                                State Register
             CLOCK




  Logic blocks implemented via discrete logic, PLAs, ROMs


              CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 13
Jump Counters

Hybrid Jump Counter

           Inputs
                                                                  Load inputs are
                                                                 function of state
                                                                  and FSM inputs
      Count, Load,              Jump State
      Clear Logic                 Logic

                  Clear
           Load
                              Synchronous
      Count
                                 Counter
                              State Register
            CLOCK




           CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 14
     Jump Counters
                                                                                                                           15
                                     /CLRm                                       CNT                                       14
CLR, CNT, LD                         /Reset
                                                                 /CLR                                                154   13     \S13
                                                                                          P                                12     \S12
implemented via                                                                           T     163              G2        11     \S11
                                                                                                 RCO                       10     \S10
Mux Logic                                                    Jump State                    CLK
                                                                                                    QD
                                                                                                                 G1
                                                                                                                            9     \S9
                                                                             3            D                      D                \S8
                                                    IR15                                            QC                      8
                                                         IR<15>              2            C                      C          7     \S7
                                                                             1            B         QB           B                \S6
                                                                                                                            6
                                                    IR14 IR<14>              0            A         QA           A                \S5
                                                                                                                            5
CLR = CLRm + Reset               1     Reset           /Reset
                                                                                  /LD     LOAD                              4     \S4
                                                                                                                            3     \S3
                                 0                                               /CLR
                                                                                          CLR                               2     \S2
                                                                                                                                  \S1
CLR = CLRm + Reset               1
                                 0
                                        Wait           /Wait                                                                1
                                                                                                                            0     \S0




 Active Lo outputs:                           S3 S2 S1 S0                               S3 S2 S1 S0              S3 S2 S1 S0
                                              G                                         G                        G
 hi input inverted at                         E15     150                               E15   150                E15   150
                                              E14                                       E14                      E14
      the output          +                   E13                     +                 E13                      E13
                                              E12                                       E12                      E12
                                              E11                                       E11                      E11
   Note that CNT is                           E10
                                              E9                     /Wait
                                                                                        E10
                                                                                        E9
                                                                                                                 E10
                                                                                                                 E9
 active hi on counter                         E8      EOUT
                                                                10                      E8
                                                                                              EOUT
                                                                                                                 E8
                                                                                                                       EOUT
                                              E7                     CNT                E7               /CLRm   E7             /LD
so invert MUX inputs!                         E6                                        E6                       E6
                                              E5                                        E5                       E5
                                              E4                                        E4               +       E4
                                              E3                                        E3                       E3
                          Wait                E2                                        E2                       E2
                         /Wait                E1                                        E1                       E1
                                              E0                                        E0                       E0

                        CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 15
Branch Sequencers
 4 Way Branch Sequencer
  I                            64 Word ROM
          Mux                                                                 N
  n      Mux  b     a0                       CS
  p
  u           a     a1      x11          Z   o i                  ab
                                                                                           ab
                            x10          Y   n g                         ab           ab
  t
  s                 a2      x01          X   t n
                                                                  W       X       Y        Z
                    a3      x00          W   r a
                    a4                       o l
                    a5
                                             l s



                                state



      Current State selects two inputs to form part of ROM address
      These select one of four possible next states (and output sets)
      Every state has exactly four possible next states
                   CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 16
Branch Sequencers
                     a and b MUX Control


                                      a b                a b            a b        a b
                                                                                                 Datapath
Alternative                               A0             A1             A2             A3        Control

Horizontal
                                                                                                 Signals
                                    n-1        1 0 n-1        1 0 n-1        1 0 n-1        10
Implementation
                    I       M   a
                    N                     0                      0 1 2 3 0 1 2 3
                            U                             ...
                    P     MX                                     4:1 MUX 4:1 MUX
                    U     U               1 bit n-1                  bit 1    bit 0
                    T     X     b
                    S
                                                         n bit state register


           Input MUX controlled by encoded signals, not state
           Much fewer inputs than unique states!
           In example FSM, input MUX can be 2:1!
           Adding length to ROM word saves on bits vs. doubling words
                 Vertical format: (14 + 4) x 64 = 1152 ROM bits
                 Horizontal format: (14 + 4 x 4 + 2) x 16 = 512 ROM bits
                  CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 17
Vertical Microprogramming
                           Branch Jump Format

   Branch Jump
                                          Condition Select
                               Type
                                               Condition Compare
   Compare indicated                     1     2       1                6
   signal to 0 or 1                      1                         Next Address

                                                             00   =   Wait
                                                             01   =   AC<15>
                                                             10   =   IR<15>
                                                             11   =   IR<14>



                           Register Transfer Format
  Register Transfer                      1         3               3           3

      Source,                            0   Source Destination Operation

    Destination,
     Operation             000:   NO OP                    000:   NO OP            000:   NO OP
                           001:   PC  ABUS                001:   RBUS  AC        001:   ALU ADD
                           010:   IR  ABUS                010:   MBUS  IR        010:   ALU PASS B
                           011:   MBR  MBUS               011:   ABUS  MAR       011:   0  PC
  10 ROM Bits              100:   MAR  M                  100:   M  MBR          100:   PC + 1  PC
                                                                                   101:   Read
                           101:   AC  RBUS                101:   RBUS  MBR
                                                                                   110:   Write
                           110:   ALU Res  RBUS           110:   ABUS  PC
                                                           111:   MBR  M
                   CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 18
Vertical Programming
                                               ROM

 Controller Block
                         Address
                                   T     SRC    DST         OP


 Diagram                                                                                 Reset
                                                                      0
                                                                           ALU ADD
                                                                      1
                                                                           ALU PASS B
                                                                      2                             0  PC
                                                                  3:8 3
                                                                  DEC 4    PC + 1  PC
                                                                      5    Read                  Read/Write
                                                                      6    Write                 Request
                                                                  Enb 7
                                                                       0   RBUS  AC
                                                                       1   ABUS  IR
                                                                       2   ABUS  MAR
                                                                   3:8 3
                                                                           M  MBR
                                                                   DEC 4
                                                                           RBUS  MBR
                                                                       5
                                                                       6   ABUS  PC
                                                                  Enb 7    MBR  M

                                                                       0   PC  ABUS
                                                                       1
                                                                           IR  ABUS
                                                                       2
                                                                   3:8 3   MBR  ABUS
                                                                   DEC 4   MAR  M
                                                                       5   AC  RBUS
                                                                       6   ALU Res  RBUS
                                                                  Enb 7
                          Wait                  LD          CLR   Reset
                          AC<15>       Cond           PC
                                                CNT               Clk
                          IR<15>       Logic
                          IR<14>



                CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 19
Design/Reverse Engineering
 Design Procedure: Specification --> Abstract Design
  --> Concrete Implementation
   E.g., “What the state machine is supposed to do” to state
    diagram to jump counter implementation
 Reverse Engineering: Concrete Implementation -->
  Abstract Design --> Specification
   E.g., Jump counter implementation to state diagram to “what
    the state machine is supposed to do”




                 CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 20

								
To top