# DIGITAL ELECTRONICS lesson plan

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```					                       RAJALAKSHMI ENGINEEERING COLLEGE
THANDALAM
DEPARTMENT OF ECE
LESSON PLAN

SUBJECT: DIGITAL ELECTRONICS                           SUBJECT CODE: 147302

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FACULTY NAME/DESIGNATION: Mrs.J.Joselin Jeya Sheela
CLASS: II YEAR ECE A
AIM
To learn the basic methods used to design digital circuits and to provide the fundamental

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concepts used in the design of digital systems.

OBJECTIVES

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 To introduce basic postulates of Boolean algebra and shows the correlation between Boolean
expressions
 To introduce the methods for simplifying Boolean expressions

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 To outline the formal procedures for the analysis and design of combinational circuits and
sequential circuits
 To introduce the concept of memories and programmable logic devices.
 To illustrate the concept of synchronous and asynchronous sequential circuits
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TEXT BOOKS
T1-M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson
Education (Singapore) Pvt. Ltd., New Delhi, 2003.
T2-S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas
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Publishing House Pvt. Ltd, New Delhi, 2006

REFERENCES
g.

1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.
3. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003.
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4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6 th Edition,
TMH, 2003.
5. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.
6. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New Delhi, 2003
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Donald D.Givone, Digital Principles and Design, TMH, 2003

SI.no        Date      Period      Topics to be covered      No.of hours       Text book
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required          page no.
UNIT I -NUMBER SYSTEMS
1                                    Boolean postulates and            1          T1-33-40
laws –De-Morgan’s                            T2-41-45
Theorem- Principle of
Duality

1
2              Boolean expression –        2   T1-40
Minimization of                 T2-45-50
Boolean expressions
3              Minterm – Maxterm -         1   T1-50
Sum of Products (SOP)           T2-51-56
Product of Sums (POS)

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4              Karnaugh map                2   T1-64
Minimization                    T2-57-65
5              Don’t care conditions       1   T1-76
T2-65-67
6              Quine-McCluskey             2   T2-67-72
method of minimization

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7               AND, OR, NOT,              1   T1-54
NAND, NOR,                      T2-77-89
Exclusive – OR and

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Exclusive – NOR
8               Implementations of         1   T1-82-94
Logic Functions using           T2-84-95

9
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gates, NAND, NOR
implementation
Multi level gate
implementations
1   T2-99-108
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10              Multi output gate          1   T2-108-110
implementations
11              TTL and CMOS Logic         2   T1-410-
and their characteristics       427,151
–Tristate gates.                T2-121-135,
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145-147
UNIT II COMBINATIONAL CIRCUITS
12               Design procedure –        2   T1-111-129
g.

T2-161-168
– Half subtractor – Full
subtractor
13               Parallel binary adder,    2   T1-122-126
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parallel binary                T2-168-175
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16               Binary Multiplier –       1   T1-131
Binary Divider                 T2-181,184
17               Multiplexer/              2   T1-141-146
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Demultiplexer                  T2-187-204
18               Encoder / decoder         2   T1-134-141
T2-220-
227,205-212
19             Parity checker, Parity      1   T2-227
generator
20             Code converters             2   T2-233-242

2
21             Magnitude Comparator        1   T1-133
T2-242-246
UNIT III - SEQUENTIAL CIRCUITS
22              Latches,Flip flops SR,     1   T1-167-180
JK, T, D– Characteristic       T2-255-268
table and equation –

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Application table
23               Master slave Flip flop    1   T1-174,456
T2-276-277
24              Edge triggering –Level     1   T1-173
Triggering                      T2-270-275
25              –Realization of one flip   1   T2-277-286

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flopusing other flipflops
26              Serial adder/ subtractor   1   T2-177
27              Asynchronous Ripple        1   T1-227-232

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or serial counter               T2-293-306
28              Asynchronous               1   T2-304
Up/Down counter
29              Synchronous counters       1   T1-232

30

31
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Synchronous Up/Down
counters
Programmable counters
1

1
T2-306
T2-324

notes
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32             Design of Synchronous       1   T1-232
counters: state diagram-         T2-312
State table –State
minimization –State
assignment, Excitation
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table and maps-Circuit
implementation
33             Modulo – n counter          1   T1-239R1-311
Register – shift
g.

34                                         1   T1-217-229
registers, Universal shift       T2-345-358
register
35             Shift counters – Ring       1   T1-241
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counters.                        T2-368,362
36             Sequence generators         1   T2-373
UNIT IV MEMORY DEVICES
37             Classification of           2   T1-256
memories – ROM -                 T1-270
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ROM organization -               T2-392,401,
PROM – EPROM –                      406,409
EEPROM – EAPROM
38             RAM         –      RAM      2   T1-256
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organization – Write             T2-386,410
operation
39             Memory cycle - Timing       1   T1-260-261
wave forms
40             Memory decoding –           1   T1-262
memory expansion                 T2-423, 428

3
41                         Static   RAM       Cell- 2 T2-411-418
Bipolar RAM cell –
MOSFET RAM cell –
Dynamic RAM cell –
42                         Programmable Logic       2 T1-275-280
Devices– rogrammable        T2-429,432

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Logic Array (PLA)
43                         Programmable Array       2 T1-280
Logic (PAL)                 T2-440
44                         Field    Programmable    1 T1-287
Gate Arrays (FPGA)          T2-443
45                         Implementation        of 2 T1-144

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combinational       logic   T2-195,
circuits using ROM,         398,440, 435
PLA, PAL

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UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS
46                        Synchronous Sequential    1 T2-453
Circuits: General Model
47                        Classification – Design   2 T1-299

48
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– Use of Algorithmic
State Machine
Analysisof Synchronous
Sequential Circuits
2
T2-454,469-
477
T1-203
T2-486
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49                        Asynchronous              2 T1-344
Sequential      Circuits:   T2-496
Design of fundamental
mode circuit
50                        pulse mode circuits       1 T2-507
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51                        Incompletely specified    1 T2-520
State Machines
52                        Problems               in 2 T1-349-
g.

Asynchronous Circuits       352,379-384
T2-521-523
53                        Design of Hazard Free     1 T1-381
Switching circuits          T2-525
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54                        Design of                 3 T1-99,147-
Combinational and           160,190-198
Sequential circuits
using VERILOG
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