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Flip flop storage element can enter to the metastable state by Q9btea5

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									East-West Design & Test Symposium




FPGA FFT Implementation




Sergey Churayev, Bakhyt Matkarimov


 Kazakh-British Technical University


        September 21, 2009
1. Abstract

 We consider FPGA design flow with C/C++ to Verilog translation
 and verification and report on FPGA implementation of fast Fourier transform
 and Wiener filter for noise reduction of speech signals on Xilinx Virtex-4


    Efficient noise reduction of speech signals is very important task in
 modern communications systems.
    The main goal of this work is to port into Verilog HDL C/C++
 implementation of spectral noise reduction with Wiener filter


                   Noisy      Segmentation            FFT
                   signal      windowing


                   Output     Inverse             Wiener
                   signal       FFT                filter

                                    1 / 13          September 21 2009
2. Introduction


 Input speech signal:   8 KHz frequency

 Frames:                32 sample length

 FFT:                   128-point

 Work:                  synchronous
                        (sequential processing of frames)

 Clock:                 external




                           2 / 13       September 21 2009
3. General structure of noise reduction test board


                                                       FPGA Virtex-4



    Voice
                                                SPI
    Input &      Audio codec                  controller
    Output
                                                                           FFT
                                                                             +
                                                                         Wiener
                                                                         filtering
     PC                                                                  module
                                              SYSCON-2
                       RS232
     RXD          TTL-PC Converter
                                              UART
     TXD



                                          TEST BOARD




                                     3 / 13                September 21 2009
4. Block schema of noise reduction module

                                        DUAL                    INPUT                      DUAL
                          data                       data                        data                   data
           LOAD                         PORT                     DATA                      PORT                  FFT
 INPUT
                                        RAM                     PROC.
  DATA     DATA                                                                            RAM                    (3)
                         request                                  (2)           request
 FROM       (1)
                                               acknowledge                                         acknowledge
 AUDIO
 CODEC
                                 data
                                                 request        acknowledge
                                        data
                       DUAL                                                   DUAL
                                                                   data                    data
                       PORT                      WIENER                       PORT                        FFT
                        RAM                      FILTER                        RAM                         (5)
                                                                  request
                                                   (4)
                                                                                     acknowledge



                data
                               request            acknowledge
                       data
         DUAL                                                   DUAL
                                                      data                    data
         PORT                      OUTPUT                       PORT                      OUTPUT
                                                                                                                    OUTPUT
         RAM                        DATA                        RAM                        DATA
                                                                                                                     DATA
                                    PROC.            request                                (7)
                                                                                                                      TO
                                     (6)                              acknowledge
                                                                                                                     AUDIO
                                                                                                                    CODEC

                                                             4 / 13                       September 21 2009
5. Main implementation issues


  Multiple clock domains
  Dual port RAM
  Handshake Protocol
  Conveyer optimization
  Synchronizing asynchronous events
  Synthesis of gating clock
  Finite state machine design




                            5 / 13     September 21 2009
6. Multiple clock domains



 Why: To maximize overall speed of data processing

 Different performance characteristics of FFT and Wiener filter
 modules
        FFT module:         35 MHz clock frequency
        FFT + Wiener filter 20 MHz clock frequency

 Implementation issues of multiple clock domains
 • inter-domain synchronization
 • data processing among all modules.



                               6 / 13       September 21 2009
7. Dual port RAM

Used as double sized data buffers for data transfers between
connected modules. When previous module writes output data
to one half of buffer, next module process previously written
data from another half of buffer.

Advantage:
• read and write data operations at different frequencies

         Module 1              Dual port           Module 2
                                 RAM
         Write data                                Read data
                          Request
                        Acknowledge


           Clock 1                                   Clock 2

                                7 / 13      September 21 2009
8. Handshake Protocol

 Why: To avoid collisions, when two modules trying to access
 data in one memory location.

 4 states simple handshake protocol:
 • Initial (start transaction) state
 • Request from Master
 • Acknowledge from Slave
 • Finish transaction from Master

  Clock 1

  Clock 2


  Request

  Acknowledge

                              8 / 13       September 21 2009
9. Conveyer optimization

                                                       FLIP-FLOP 1




                                                           Logic
                                       Clock                 1
  Increase clock frequency
  (overall speed) in conveyer,                         FLIP-FLOP 2
  transferring part of logic from
  module with biggest time delay
  to module with smallest time                             Logic
                                                             2
  delay, when it is possible.
                                                       FLIP-FLOP 3




                                                           Logic
                                                             3


                              9 / 13           September 21 2009
10. Synchronizing asynchronous events

 System operate synchronously with asynchronous input signals.

 Flip-flop storage element can enter to the metastable state, if
 data signals are unstable in setup&hold interval of preceding
 clock edge or if the data pulse is too narrow.

 Flip-flop metastability effect can reduced:

                   Asynchronous
                                  D   Q        D    Q
                   input


                                  Clock        Clock
                     Clock




                                  10 / 13      September 21 2009
11. Synthesis of gating clock


 Disable clock signal to reduce power waste

 FPGA device: using clock enable input signal




                                                                        FPGA
                ASIC
                                                        Data in             Flip Flop Data out
  Data in              Flip Flop   Data out

  Enable                                                Enable

            &
  Clock                                                 Clock



                                              11 / 13             September 21 2009
12. Finite state machine design

 RAM–based finite state machine
 Row address represents the current state of the machine
 Contents, associated with that address, holds the output
 functions and the next state.


                      RAM
                                         Output
       State

                                           State register
                                Next
           Input                State



                       Clock


                               12 / 13            September 21 2009
THANK YOU FOR ATTENTION

								
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