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A fully integrated radio transceiver chip for the 2.4 and 5 GHz WLAN standards 802.11a/b/g is presented in a 0.25 �m 40 GHz BiCMOS technology. The chip integrates the LNAs, mixers, channel filters, PGC, synthesizers with VCOs and reference oscillator, transmitters, anti-aliasing filters and voltage regulators. The presented transceiver exceeds all IEEE requirements for the 802.11a/b/g CCK and OFDM standards. At 2.4 GHz, an operational range of –85 to 8 dBm and of -74 dBm to 4 dBm have been demonstrated for the 11 Mb/s CCK and 54Mb/s OFDM modes, respectively. Furthermore a maximum EVM of -32 dB have been measured.
A highly integrated, dual-band, multi-mode Wireless LAN Transceiver Thomas Rühlicke, Markus Zannoth, Bernd-Ulrich Klepser Infineon Technologies AG, Secure Mobile Solutions, Technology and Innovations 81609 Munich, Germany Abstract: transceiver, including the major blocks of the transceiver: low noise amplifier (LNA), transmitter, synthesizers, A fully integrated radio transceiver chip for the 2.4 and voltage regulators and the 3-wire bus interface including 5 GHz WLAN standards 802.11a/b/g is presented in a the control logic. For the established 802.11b standard a 0.25 µm 40 GHz BiCMOS technology. The chip direct conversion architecture is used at the receive path integrates the LNAs, mixers, channel filters, PGC, to achieve a low power consumption and a high adjacent synthesizers with VCOs and reference oscillator, channel rejection. With this standard the requirements transmitters, anti-aliasing filters and voltage regulators. regarding linearity, dc-offset and signal to noise ratio The presented transceiver exceeds all IEEE (S/N) are not as constrained as for the high data rate requirements for the 802.11a/b/g CCK and OFDM standards 802.11a and 802.11g, where 54 MBit/s data standards. At 2.4 GHz, an operational range of –85 to rate can be achieved. For the high data rate, a low +8 dBm and of -74 dBm to +4 dBm have been intermediate frequency (LIF) based architecture has been demonstrated for the 11 Mb/s CCK and 54Mb/s OFDM chosen. Compared to a standard IF architecture , the modes, respectively. Furthermore a maximum EVM of LIF architecture provides a low-cost solution and -32 dB have been measured. overcomes the dc-offset problems of the Zero-IF solution with a direct conversion architecture. 1. Introduction RX 2.4GHz RSSI RSSI In recent years there has been a increased demand in RX 2.4/5GHz wireless local area networks (WLANs). The most 2.4GHz RX Filter / PGC CCK Filter commonly used frequency bands are the 2.4 to 2.5 GHz RX 5.2GHz ISM band and several frequency bands from 5.15 and RX I Q 5.85 GHz, with several communication standards defined 5GHz PGC1 PGC2 in the IEEE 802.11 standards. Thereby, the standards OFDM Filter Loop Filter 802.11a and 802.11g enable data rates of up to 54 MBit/s TX 5.2GHz 0° PLL 5 GHz 2.4GHz using orthogonal frequency division multiplexing 90° TX 5GHz 40 MHz out (OFDM) . The established standard 802.11b uses the Synthesizer direct sequence spread spectrum (DSSS) and has a 3-wire TX 2.4GHz 3-wire bus maximum data rate of 11 MBit/s. bus TX LDO This paper presents the circuit design and measurement 2.4GHz I results of highly integrated, 2.4 and 5 GHz dual-band, Q 802.11a/b/g multi-mode RF transceiver. The circuit is Fig. 1: Block-diagram of the dual band transceiver fabricated in a 0.25 um 40 GHz BiCMOS technology. The chip is assembled in a 48 pin package for small size The high frequency 5 GHz transmit path for 802.11a uses and small number of external components. a low-IF direct modulator, while for the lower band at 2.4 GHz a zero-IF direct modulator is implemented. 2. Architecture of the transceiver A major advantage of the chosen RF architectures in the receive and transmit path of the transceiver is the low For the architecture of the presented RF transceiver a component count of the system reference design. The direct conversion architecture with a combination of low- external parts are: blocking capacitors at each power IF and zero-IF interfaces to the baseband IC has been supply close to the pins; the external 40 MHz crystal chosen. In general, the advantage of a zero-IF architecture (xtal); one reference resistor to generate an exact is higher adjacent channel rejection using real channel reference current; the matching networks for LNA-inputs filters while the advantage of a low-IF architecture is a and modulator outputs and the external loop filters for larger robustness of the signal with respect to dc offset and both synthesizers. For the complete WLAN system, an image rejection since these impairments lead to out of- additional band-select filter at the LNA inputs, a band spectral components. baseband processor, power amplifiers for 2.4 GHz and Fig. 1 shows the schematic block diagram of the 5 GHz, antennas and switches are required. No further channel filtering at the receive path, anti-aliasing filtering give sufficient margins for the power amplifier to meet at the transmit path or voltage is needed. the specified EVM value of –25 dB for the 54 MBit/s mode . 11a 11b 11g 3. Description of the major blocks of the transceiver Frequency 5.15- 2.4- 2.4- 3.1. Transmit path 5.85GHz 2.5GHz 2.5GHz For the transmit path a direct modulator architecture is Sensitivity (54Mb/s) -74dBm -72dBm used for 2.4 GHz and for 5 GHz modes. As low-IF is Sensitivity (11Mb/s) -85dBm used at the 5 GHz path a larger bandwidth is Max. input power -10dBm +4dBm +4dBm implemented at the low frequency blocks than at the I-Q impairment 0.6% 0.8% 0.8% blocks for the 2.4 GHz path, where direct modulation is 1° 1.3° 1.3° used (see Fig. 2). The complex analog input signals are Adjacent channel 0dB/9dB -28 dB 0dB/9d fed directly to a integrated low pass filter that is suppression (7dB marg.) B integrated to reduce the harmonic spectra of the digital Alternate channel >30dB >30dB analog converter of the baseband chip to the required suppression value of -40 dBc for the OFDM modes and –50 dBc for RX EVM limit -32dB -32dB -32dB the CCK modes, respectively . TX EVM -32dB -32dB -30dB The filtered signal is then fed to a programmable gain PLL rms phase error 1° 0.6° 0.6° amplifier that is used to convert the voltage output signal Table. 1 : Summary of WLAN transceiver performance of the active RC filters to a current. With the The 2.4 GHz output spectrum of the transmitter is shown programmable gain the production tolerances of the in Fig. 4 for the 11 MBit/s CCK mode as well as for the output power can be canceled out. The modulator core 54 MBit/s OFDM mode. The transmission spectrum itself consists of two bipolar switching pairs where the masks are exceeded with sufficient margins for the current is directly inserted . LO for I Signal nonlinearities of the power amplifiers. The whole transmit path operates with a supply voltage 3rd Order of 2.6 V and has a current consumption of 155 mA at the Butterworth I U/I- 5 GHz mode and 110 mA at the 2.4 GHz modes. These 3rd Order Converter measured values demonstrate a state-of-the art direct IX Chebyshev modulation transmitter performance, with the capability out outx of supporting the 54 MBit/s modes with a very small 3rd Order Q Butterworth number of external components, e.g. output matching U/I- 3rd Order Converter network and supply blocking capacitors. Q Chebyshev -13 X -23 -33 LO for Q Signal -43 Fig. 2: 2.4 GHz transmit path of the WLAN transceiver -53 -63 For OFDM signals with 10 dB back-off, a mean output -73 power of –4 dBm can be measured with a matched output -83 -93 at the 5 GHz band as well as the 2.4 GHz band. The -103 constellation diagrams for the CCK 11 MBit/s mode and -113 2392 2402 2412 2422 2432 2442 Frequency/MHz 2452 2462 2472 2482 2492 for the 54 MBit/s OFDM mode are shown in Fig 3. Fig. 3: Transmission mask for 802.11g 11Mb/s QPSK CCK (left) and 54Mb/s 64QAM OFDM (right) signals 3.2. Receive path The receive path consists of two LNAs with mixers at the input for the 5 GHz band and 2.4 GHz band, a first programmable gain control stage (PGC1), channel filters and second PGC stages (PGC2) as shown in see Fig. 5. The down conversion mixers consist of Gilbert-Cell Fig. 4: 2.4 GHz transmit constellation diagram for mixers. The first PGC optimizes the level of the signal to 802.11g 11Mb/s QPSK CCK (left) and 54Mb/s 64QAM reduce the linearity requirements of the channel filter. Both OFDM (right) signals OFDM and CCK channel filters have been integrated in order to replace external SAW filters. For the Low-IF The measured error vector magnitudes are –32 dB and OFDM modes (802.11a/g) polyphase bandpass filters are -30 dB for the 5 GHz and 2.4 GHz band, respectively used. For the OFDM signals a Butterworth approximation th (see Table. 1). These measured values for the transceiver of 5 order with a center frequency of 10 MHz and a 3 dB- RSSI out -20 RSSI RSSI outx 1b/g RF in I-Signals Channel Filter -30 LO IQ RF inx Chebyshev I out PGC1 PGC2 Channel IX out Filter -40 Butterworth Polyphase to ADC Level [dBm] Channel Filter Butterworth Q out -50 PGC1 PGC2 RF in Channel QX out 11a Q-Signals Filter RF inx LO IQ Chebyshev -60 -70 measured ACP Fig. 5: Receive path of the WLAN tranceiver -80 Spec limit bandwidth of 25 MHz is used. For the 802.11b and Channel 802.11g CCK mode a low-pass filter with a bandwidth of -90 8 MHz is used. Both filters are implemented with active 2397 2417 2437 2457 2477 frequency [MHz] RC circuits in leap-frog structures. In addition to the signal path, a received signal strength indicator (RSSI) has been Fig. 7: Measured ACP in 11 MBit/s CCK mode implemented to detect any signal to wake up the baseband For the 11 MBit/s 2.4 GHz CCK mode, a sensitivity of chip and to measure the signal level. -85dBm has been measured, i.e. 9 dB better than the The LNA has a gain of 30 dB which can be reduced by IEEE specification of -76dBm. The high sensitivity and 20 dB at the 5 GHz mode and by 27 dB at the 2.4 GHz low noise floor measurements demonstrate the excellent mode, respectively. Fig. 6 shows the measured low noise performance of the presented receiver, which constellation diagram for a 11 MBit/s CCK signal as well will enable a large operational range and a high as for a 54 MBit/s OFDM signal for received 2.4 GHz robustness against multi-path disturbances. signals. 15 EVM 10 Specs limit 5 0 -5 EVM [dB] -10 -15 -20 Fig. 6: Receive constellation diagram for 11Mb/s QPSK -25 CCK (left) and 54Mb/s 64QAM OFDM (right) signals -30 An EVM of –30 dB has been measured, which is 12 dB -35 better than the minimum requirement for a 54 Mb/s -100 -80 -60 -40 -20 0 AWGN channel . The adjacent and alternate channel OFDM input power [dBm] suppression has been determined by measuring required ACP (adjacent/alternate channel power) for a EVM Fig. 8: Measured sensitivity for the 54 MBit/s 802.11g degradation to -18dB of a 54 Mb/s OFDM channel with OFDM mode –62 dBm . An adjacent and alternate channel suppression of 0dB and 30dB has been measured, respectively, which 3.3. Frequency synthesizer demonstrated the feasibility of a Low-IF receiver To achieve minimum power consumption at each band architecture for 802.11a/g OFDM receiver. At the (2.4 GHz and 5 GHz), two different frequency 11 MBit/s CCK mode an adjacent channel power of synthesizer blocks are used (cf. ). -28 dBm has been measured which shows a margin of The reference oscillator running at 40 MHz is a partly 7 dB to the specified value of –35 dBm, cf. Fig. 7. integrated Colpitts oscillator. Only the xtal and a The sensitivity for an EVM value of –18 dB, which capacitor has to be connected externally (cf. ). corresponds to a 54 MBit/s PER (package error rate) of The synthesizer for the 5 GHz band consists of an 10% as required by the IEEE standard , has been integer-N offset phase locked loop (PLL) with a voltage measured to be -73 dBm, cf. Fig. 8. The measured value controlled oscillator (VCO) at 4/3 of the desired is 8 dB better than the IEEE requirement. For higher transmitted frequency. With using this architecture (cf. inputs powers the specification is met up to an input level ) a quadrature phase error of only 1° has been of +4 dBm (see Fig. 8). measured, which is a state-of-the-art value for a 5 GHz synthesizer and demonstrates the advantages of the receivers a maximum EVM of -32 dB has been measured, presented architecture. which enables the design of highly robust WLAN systems In order to combine a large tuning range with low tuning regarding multi-path distortion. Using a reference design sensitivities the VCOs feature a band selection algorithm board, a large operational range from -85 dBm to +8 dBm to set one out of 128 VCO frequency bands followed by in 11 MBit/s CCK mode and -74 dBm to +4 dBm in an analogue settling process controlled by the PLL . 54MBit/s OFDM mode has been measured with a 2.4 GHz The bands of the VCO can be selected by switching input signals. capacitances in the oscillator tank (see Fig. 9) . VCC 5. Acknowledgement The presented circuitry has been developed within funded projects HGDAT and IBMS2 by the ministry of education and research in Germany (BMBF). Vtune  Wireless LAN Association, "Wireless Networking Standards and Organisations", www.wlana.org, April 2002  Su, M. Zargari, P. Yue, S. Rabii, D. Weber, B. Kaczynski, S. Mehta, K. Singh, S. Mendis, B. Wooley, "A 5 GHz CMOS TRansceiver for IEEE 802.11a Wireless LAN", ISSCC 2002 Digest of Technical Papers, Paper 5.4, Feb. 2002  Bernd-Ulrich Klepser, Manfred Punzenberger, Thomas Rühlicke, Markus Zannoth, “ 5-GHz and 2.4-GHz Dual- Band RF-Transceiver for WLAN 802.11a/b/g Applications”, to be published in the Proceedings of the on/off RFIC Conference, 2003.  C. Grewing, A. Hanke, S. V. Waasen, Fig. 9: VCO with switchable LC-Tank "Schaltungsanordnung zum Bereitstellen eines komplexwertigen Lokaloszillator-Signals und Summarizing all tolerances having impact on the Empfänger", Patent pending Nr.: P2001,0617WO frequency accuracy after band selection algorithm  Kral, F. Behbahani, A.A. Abidi, " RF-CMOS oscillators performed a fine-tuning sensitivity of 200 MHz/V is with switched tuning", in Custom IC Conf., Orlando, FL, sufficient for locking the PLL under all conditions. pp. 569-572, 2000 For a conventional VCO at 5 GHz, a tuning range of  J. Kucera, B.-U. H. Klepser, “3.6GHz VCOs for multi- 1500 MHz would be required to cover all defined bands band GSM Transceivers”, Proceedings of the ESCCIRC, over production tolerances. With a given tuning range of 2001  B.-U.H. Klepser, M. Scholz, E. Götz, "A 10-GHz SiGe BiCMOS 1 V, the resulting tuning sensitivity would be as large as Phase-Locked-Loop Frequency Synthesizer", IEEE Journal of 1500 MHz/V. These high tuning sensitivity would have Solid-State circuits, Vol. 37, No.3 March 2002 pp. 331 significant drawbacks with respect to crosstalk, pushing and phase noise, which clearly demonstrates the advantage of the presented VCO architecture. The phase noise floor normalized to 1 Hz of both PLLs is measured to be –215 dBc/Hz, which is comparable to a XO Regulator VCO PLL state-of-the-art SiGe-PLL . The rms phase error of the whole synthesizer including quartz oscillator and voltage TX-Filter VCO LNA regulator is measured to be 1° at the 5 GHz modulator output and 0.6° at the 2.4 GHz modulator output. With RX-Filter these values the requirements for EVM can be exceeded for the 54 MBit/s mode of the 802.11a/g standards. LO-Generation RX-PGC 4. Conclusion LNA Modulator A transceiver has been realized in a 0.25 um, 40 GHz RSSI BiCMOS technology for the WLAN standards 802.11a/b/g. The chip integrates a complete dual band transmitter, dual band receiver, two phase locked loops with integrated VCOs, level detector and voltage regulator Fig. 10: Chip photograph of the WLAN transceiver (see Fig. 10). The chip exceeds all IEEE specifications for 54 MBit/s modes. At a mean output power of –4 dBm, the measured transmit EVM is –32dB at 5 GHz and -30 dB at 2.4 GHz, respectively. For both 2.4 GHz and 5 GHz
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