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Scaling

VIEWS: 3 PAGES: 29

									    Scaling II

Mohammad Sharifkhani
                 Reading
• Textbook I, Chapter 2
• Textbook II, Section 3.5, Section 4.5.3,
  Section 5.6
            CMOS Scaling
• Basic MOS rule: L↓  gm↑, C ↓
• Short channel effect + Lithography limits
  L
• The worst SCE: reduction in gate Vt where
  MOS turns on, especially at high VDS
• Process needs to keep SCE under control
         Constant Field Scaling
• To scale vertical and
  horizontal dimensions at
  the same proportions
   – Gate insulator, junctions
     depth, etc.
   – Doping concentration ↑ 
     Depletion width ↓
• Decreasing the applied
  voltage
•  Size 1/k, voltage 1/k
  E constant
•  Hot carrier injection is
  not worse than the original
  device
Scaling of MOS and circuit
        parameter
     Scaling of MOS and circuit
             parameter
• R of the MOS remains unchanged (I and V
  scale together)
• Delay ~ R x C  1/K
• Power ~ V x I  1/K^2
• Power x Delay  1/K^3 
• Power density ~ Power / Area  1
 2-D effects (Deep sub-micron)
• Poisson equation:

• Increasing the doping keeps E unchanged
  over X axis
• Boundary cond. function of built-in p-n
  potential  Do not scale
• When V~1V (bandgap) the second order
  effects kick-in
 2-D effects (Deep sub-micron)



• Maximum gate depletion width: Wdm (no
  carriers under the gate)
• If horiz. side is twice as long as vertical side,
  long-channel device with good short-channel
  behavior
• Else, source channel potential (critical for setting
  threshold condition) is influenced by drain
  voltage (SCE)  No small Vt is possible
  2-D effects (Deep sub-micron)
• There are oxide and silicon
• Boundary cond. at interface

• Depth of oxide region
  equivalent to
     In silicon
• So the total vertical side
• L min ~= 2(Wdm+3tox)  both
  tox and Wdm has to be scaled
  proportionally
     Power-supply and threshold
          voltage scaling
• Power supply usually
  do not scale as much
  – Subthreshold diffusion
    current not scaled
  – Previous generation
    voltages are of interest
• Problems:
  – High electric field 
    Hot carrier injection to
    the gate,
    electromigration
  – Power consumption
    (100W)
         Power-supply and threshold
              voltage scaling
• In subthreshold the leakage drops
  exponentially proportional to kT
• I0~0.1uA/um for a 0.1um device
• Even if Vt is kept constant, the
  leakage increases in proportion to
  1/tox and Wtot/L because the
  current at threshold is proportional
  to Qi ~ 1.5 kT/q Cox
• Every 0.1V decrease in Vt  10x
  more leakage
• For a 100million T chip, the
  average leakage current <10nA
• Minimum bound for Vt ~ 0.2V
      Power-supply and threshold
           voltage scaling
• Vt/Vdd ↑  performance ↓:
• Performance ~ 0.7-Vt/Vdd ;
  stronger than Ion because
  of the finite rise time at the
  input
• With Vt bound to 0.2, Vdd
  less than 1V will not buy
  us a lot of performance
    Power-supply and threshold
         voltage scaling
• Performance gain
  – Lower Vt, higher stand-by
    power (high Vt for low
    power designs)
  – Higher Vdd, higher
    dynamic power (high
    performance processes)
    Power-supply and threshold
         voltage scaling
• A 0.1um CMOS ring
  oscillator 101 stage
• 10% decrease in
  performance  30%-
  40% reduction in active
  power
                        Gate oxide
• Gate oxide thickness ↓ α L ↓
• tox ~ 1/25-1/50 L
   – tox ~ 3nm: a few layers of atoms
• Gate leakage : Quantum Mech.
  Tunneling
   – Exponentially proportional to tox
   – Direct tunneling: gate voltage do not
     play an important role
   – Only for turned on NMOS (gate is on)
   – PMOS is better
• For 0.1cm2 gate area on a chip,
  tolarable gate leakage 1-10 A/cm2
• Minimum tox is 1.5-2nm
                  Gate oxide
• Two other phenomena:
  – Inversion layer quantization:
     • Density of inversion electrons 1nm below the Si
       surface  effectively 0.3-0.4 nm thicker tox (SiO2)
  – Polysilicon gate depletion effect:
     • Thin space charge layer within the poly  reduces
       the effectiveness of the gate
• At tox = 2nm; 20% loss in inversion charge
  
                      Gate
• Poly:
  – Resistive (silicide)
  – Depletion effect
• Why poly and not metal?
  – Metal : mid-gap bands
  – Compensating doping  poor short channel
    effect
       Channel profile design

• Both tox and Wdm must
  be scaled
  – Wdm ↓  Na ↑  higher
    depletion charge @ surface
     higher electric field 
    higher threshold voltage



  – Retrograde doping prevents
    this to happen
       Channel profile design
• Comparison between the
  uniform and (extreme)
  retrograde profiles
• For the same Wdm
  – In Retrograde the total
    depletion charge and
    hence the electrical field is
    half of that of the uniform
  Other channel doping effects
• Body-effect coeff.
  m=1+3tox/Wdm
• Inverse subthreshold
  slope, (ln 10) mkT/q
• Substrate sensistivity ↑,
  subthreshold slope↑
• We need to keep m
  close to 1; m<1.5 or
  3tox/Wdm<0.5
                 Halo Doping
• Non-uniform lateral profile
• Ion-implantation, self aligned
  to gate + diffusion (a little)
• Counter acts short-channel
  effects
   – Off current robust against L
     variations
   – Shortest channel length possible
                      Halo Doping
• Flat Vt dependence on
  channel length
  – Lower Vt is posssible
      • Performance



  Suffered from SCE
   i.e., Vds influences Vt
         Interconnect scaling
• Everything is scaled,
  including the oxide
                               tw
  between the stacked wires
                                    Ww
• Wire length Lw is also
  scaled as a result of tech
  scaling
• Fringing cap, wire-to wire
  caps/length remains
  constant
          Interconnect scaling




• Cw= K (gap between the wires) x 1/K (width)
• τ (Tau) =1/K (C for a scaled length) x K (R for a
  scaled length)
• Current density increases; Electromigration
         Interconnect scaling
• Some typical values:
  – @0.25um ; Cw = 2pF/cm
  – For aluminum
     • Tau = 3 x 10-18 (sec) x L2/(Ww x tw)
     • For a 0.25u x 0.25u size wire x 100um long; delay
       = 0.5pSec; comparable to a cmos inverter in 0.1u
       tech (20pSec).
• Conclusion: local wires is not a big issue
          Global wire issues
• Global block to block cross-chip wires
• The chip size usually do not scale; it may
  even increase
  – When remains the same; Tau increases by
    K2(see last page L cte)
  – The cross-chip wires can create up to 1ns
    delay
        Global interconnects
• Solutions:
  – Use of copper: 40% faster
  – Minimizing the number of corss-chip
    interconnects (Brain, CAD tools, etc.)
  – Repeaters
• Fundamental solution
  – Thicker wires (lower resistance, higher cap)
  – wider dielectric spacing (lower cap)
             Global interconnects
• Strategy:
   – Scale down the size and spacing of
     local interconnects
   – Un-scaled, scaled up
     wires/distance for higher layers
     (reduction in delay for a given length)
• Limit: Transmission Line delay
  (when inductance becomes
  dominant)
   – Rise time is shorter than the flight
     time over the length
• Speed of electromagnetic wave,
  instead of RC:
        Global interconnects
• For oxide, time of flight
  is:
  – 70pSec/cm
• A longer global wire 
  larger wire cross
  section

								
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