CSCE 932, Spring 2007 Fault Tolerance: Testing and Testable Design - PowerPoint

							CSCE 932, Spring 2009
       Syllabus




                        1
    Contact Information
My web page: cse.unl.edu/~seth
AvH 359, seth@cse.unl.edu, 472-5003
Office Hours: Flexible




                                      2
    Required Background
Logic design, Boolean algebra
Basic math background: probability
theory, discrete math
CSE courses: Computer architecture,
perhaps OS




                                      3
   Sources of Information
Listed on a separate sheet.




                              4
                Course Format
Part 1: Background in VLSI testing:
   Lectures by me + class discussion
   Knowledge tested by HW assignments
Part 2: Advance topics
   Lectures by every one + class discussion
   Graded on technical and presentation qualities
Part 3: Semester project:
   Identification (Preproposal – 2-3 pages)
   Full proposal (8-10 single-spaced pages + oral presentation)
       Literature review, problem formulation, solution and evaluation plan,
       expected outcomes
   Final Report (c. 25 double-spaced pages + oral
   presentation)


                                                                               5
               Grading
Homework                        40%
Topical Presentations           25%
Project
  Proposal & Presentation       15%
  Final Report & Presentation   20%
Percentage vs letter grade:



                                      6
Course Overview




                  7
             Outline
Fault Tolerance
Technological Context
Course Topics and Organization




                                 8
           Fault Tolerance
Ability of a system to function in the event of
a failure
Sources of Failure
  Permanent (hard) component failures causing
  system malfunction
  Transient failures due to internal or external
  causes
     Unreliable components
     Buggy software
     Radiation, Noise, Crosstalk
     ...



                                                   9
   Fault Tolerance Methods
 Redundancy Techniques
   Component (HW or SW) Level
   Information Level
 Frequent Testing and Possible Repair
   Online testing
   Offline testing
This course will focus on fault
 tolerance through testing of digital
 components

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          Types of Testing
 During Design & Manufacturing
   Design Verification (Validation)
   Process Characterization
   Silicon Debug
   Production (Go/No-Go)
 Beyond Manufacturing
   Acceptance
   Power-on
   Field test and repair
We will focus on design & manufacturing
 testing
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Technological Context




                        12
    Trends of Interest to Us
Embedded systems and chip or core
multiprocessors (CMPs)
Importance of low power in high-
volume and high-performance devices
and systems
Feature Size Reduction
Design productivity and time-to-market
Wiring delays dominate gate delays

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Prevalance of Mobile Devices
                 Cell phones sales exceeded
                 PCs by only a factor of 1.4 in
                 1997, but the ratio grew to
                 4.5 in 2007.
                 In 2004, there were
                 approximately one PC, 2.2
                 cell phones, and 2.5
                 televisions for every eight
                 people on the planet




                                         14
            Power Trends




In CMOS IC technology
 Power  Capacitive load  Voltage 2  Frequency
                                               15
                    The Power Wall
   We can’t reduce voltage further
   We can’t remove more heat
   Hence the move to chip multiprocessors (CMPs)




     Constrained by power, instruction-level parallelism, memory latency



                                                                           16
IC Types and Requirements Determined
     by Portable/Consumer Market

Three major types (as identified by ITRS
2005)
  SOC
     Low-power paramount
     Need SOC integration (DSP, MPU, I/O Cores, NoC, etc.)
  Analog/Mixed Signal
     Migrating on-chip for voice processing, A/D sampling,
     and some RF transceiver functions
  MPU
     Specialized cores to optimize performance for low-power
     use.


                                                             17
        Course Topics and
          Organization
Background in VLSI Testing (first part of the
course – by me)
  Basics
  Fault Modeling
  Coverage Analysis
  Test Generation
  Design for Testability
Current topics (presentations and discussions
by all) (second half of the course)
Individual Research Projects (second half of
the course)
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