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EE314 CMOS RF Integrated Circuits
( Stanford University: Dr. Hamid Rategh )
Wide-Band High-Performance LNA Project Report
Michael Min Sun aliensun@stanford.edu
Ming Tao Chien mtchienb@stanford.edu
Winter 2006
Single- Ended Source-Degenerated Common-Source
Low-Noise Amplifier
Achieved Specifications
Specs Results
Pdc(mw) <13 12.0937
IIP3(dBm) >-5 11.01
Vdd(v) <2.5 1.5
R(kΩ) <200 101.6
frequency 1.8GHz 2.0GHz 2.2GHz
|S11|(dB) <-10dB -10.1445 -13.6927 -14.4193
|S21|(dB) >10dB 11.2055 10.7594 10.2263
NF(dB) minimum 0.690129 0.769082 0.939602
1
Hspice LNA Netlist
** Subcircuit Name
** | Input Pin
** | | Output Pin
** | | | Vdd Pin
** | | | | Vss Pin
** | | | | |
.subckt lna in out vdd vss
***** Transistor Noise model*****
XMn1 o g1 sub sub nnmos L=0.25u W=300u nf=120 sx=1 dx=1
XMn2 g2 g2 sub sub nnmos L=0.25u W=21u nf=8 sx=1 dx=1
***** Passive *****
** Source and Substrate Inductance connected to Vss through Bondwire
xLs1 vss sub sub pin np=2 nb=2 lb=1m
xLs2 vss sub sub pin np=2 nb=2 lb=1m
**Gate, Drain, and Output inductance connected to Pin through Bondwire
xLg in g1 sub pin np=1 nb=1 lb=3m
xLd vdd o sub pin np=1 nb=1 lb=7m
xLo1 out o sub pin np=2 nb=2 lb=6m
xLo2 out o sub pin np=2 nb=2 lb=4m
**Bias Resister and Ac blocking Resistor
Rbias o g2 1.6k
Rb1 g2 g1 100k
.ends lna
2
LNA Schematic
Vdd 4mm
8 6
7
7mm
R=1.6K 4mm
Output
6mm
XMn2 8
21/0.25
nf=8 7.678mA 9
6mm
R=100K XMn1
300/0.25
nf=120
3mm
Input 5
Sub
1mm 1mm 1mm 1mm
1 2 3 4
Vss
Package Layout
10 9 8
7mm
6mm 6mm
4mm
1 7
1mm
4mm
2 6
1mm 3mm
1mm 1mm
3 4 5
3
I. Design Heuristic
It’s a real challenge to design a wide-band (1.8GHz- 2.2GHz) low-noise
amplifier (LNA) with a noise figure (NF) less than 1dB since it requires a clear
understanding of low noise techniques subject to other constraints across the
entire band. In order to minimize the noise, we chose the single-stage
without cascode architecture. Therefore, a systematic and iterative design
strategy is needed to compensate the coupling effect between input and
output. Our design heuristic combines the ideas of gm/Id and classical 2-port
noise theory. We use gm/Id as a merit variable that we can use to
characterize the 0.25um technology and obtain key parameters such as
transit frequency (fT), current density, plotted as a function of gm/ID for a
w=100um device cell. This idea removes the errors associated with
estimating intrinsic device capacitances and device width for a specified
current and transconductance. To start the design, the gm/ID charts for fT and
current density also showed the design sweet spot and the limitation of the
0.25um technology.
We know from the classical 2-port noise theory that to obtain minimum
noise figure, there is a certain input impedance match criteria. Unfortunately,
the input impedance that yields a noise match does not yield a power match.
Therefore, a trade-off has to be made to obtain the best noise figure while
satisfying S11 specification at the same time. However, we have to have the
correlation coefficient of gate noise and drain noise in order to establish the
2-port analysis which is fairly impractical.
We started our hand calculation assuming input power match perfectly at
2Ghz(center frequency) and the drain noise and gate noise are uncorrelated,
then found the gm/id the give us the best noise figure. Secondly, we
implemented the design with ideal elements to verify our design and loosen
the input power match constrain to get better noise figure. Finally, we used
the practical elements and tried to optimize the noise figure subject to power
dissipation and package constraints. The four equations that initially guided
us are gain (S21), input impedance, Bandwidth requirement (Qmax), and
noise figure equations. We make many approximations in order to obtain a
starting circuit. Therefore, we use systematic and iterative design strategy to
tune our design on the fly.
II. Hand Calculation
Since we were designing a wide-band LNA with specification across
1.8GHz to 2.2GHz which means the bandwidth B is 400MHz. We chose to set
4
f0 =2GHz and over-design the S11, S21 at this frequency since we anticipate
the worst case will occur at 1.8GHz or 2.2GHz. Equation (1) indicates that
fT/f0 must be big enough to support S21. From the fT vs. gm/id chart, we
know for 0.25 technology it’s not hard to achieve fTf0 >= 4 to support
|S21|>10dB when RLoad=Rsg. Considering the wideband requirement will be
hard to reach if we use more impedance transform circuits, we decide to set
RLoad = Rsg = 50Ω and fT/f0=5. And we also kept in mind to check if Q of the
serial RLC < 5=f0/B.
g m RLoad f
S 21 T (1)
0 C gg Rsg f0
I tried to estimate what gm/id will give me the lowest noise figure. We
simply assume the total noise sources of the LNA are device induce gate noise
and drain noise. By using noise model in textbook, page 358, and assuming
the induce gate noise and drain noise is uncorrelated, we obtain equation (2)
and found out that for gm around 40ms-55ms the noise figure is around
1.14dB which is close to the bottom of the bowel. Then I chose Pdc=10mw to
1.2 * (2 / 3) T Ls 50
g m (T Ls 50 Rp) 2
F 1 (2) Rs W
50 * 5g m 4 * 50 ( fT / f 0 ) 2 Rp 1( gate resistor )
3n 2 L
Assume Rp small due to large number of finger
n number of finger
preserving 3mw for later adjustment and prepare to consume more power
from the discrepancy of Id due to channel length modulation. And I picked
Vdd=1.5 for the starting design to have gm = 48ms which is around
40ms-55ms (check Q=2<5 OK!).
Now since I have fT, gm, I know Cgg which is Cgs+Cgd+Cgb (This is a
better approximation of Cgs since the other parasitic will also affect Zin(jω)).
I can start to design Ls and Lg from equation (3) by assuming r0 is big in
equation (4). We get Ls=0.8nH and Lg=7.4nH. However, from equation (4),
I anticipated that we have to final tune the circuit the have the desire S11
since ZL will eventually alter Zin(jω). We have to iteratively tune the Ld,and Ls
& Lg to reach the specification.
1
Z in ( j ) j ( ( L x L g ) ) 2f T Ls (3)
C gg
1 r0
Z in ( j ) j ( ( Lx Lg ) ) 2f T Ls ( ) (4)
C gg r0 jLs Z L
Finally, the output can be model as figure (1). We designed Ld by roughly
estimate the Capacitor at the output and set the Ld to resonate out the Cdtot
at f0 in order to deliver most current to the RLoad to have bigger S21 at f0.
5
I
50Ω
resonate out
Figure (1)
All the calculation above is programmed in an excel spreadsheet to
accelerate the iterative design process (in the appendix). By doing so, we
can approximate our design performances faster than using Hspice only, and
the most important thing is the design parameter will be only 15% off.
During the whole design, we were not focusing on IIP3 specification. We
know the non-linearity come from non-linearity of gm so we can always have
a higher VoD (transistor over drive voltage) and a smaller Q (cause smaller
input swim) to enhance linearity. Nevertheless from equation (5) in textbook,
page 392, in order to have IIP3<-5dBm, we must have |c1/c3|<0.024 which
is very unlikely.
2 c1 1
IIP3 (5)
3 c2 Rs
III. Implementation and Fine Tuning
We decided to use a single-ended without cascade source-degenerated
common-source amplifier because single-ended circuit generates less noise
than differential circuit does respect to the same power consumption. After
we finished the ideal element design step, all values of elements are feasible
to be realized with bondwires (ranged from 1nH to 7nH). It’s an advantage to
utilize the inductance in the bondwire since other on-chip inductors have poor
Q which will introduce additional noise from their finite resisters. To further
reduce the noise, we decided not to use the commonly used cascode
architecture since cascode will attribute considerable induce gate noise
especially in RF. Turns out that most of the time ro is much bigger than RLoad=
50Ω so taking off cascode won’t effect S21 much. However, now the
impedance at the output will couple with the input impedance as equation (4)
and we will also have miller effect at the input. All of the above effect will
cause our hand calculation deviate from the reality more, but we can always
alter Ls to get the Rin≈50 and alter Lg+Ls to resonate out the additional
capacitor cause by the miller effect.
To compensate the coupling from the output, we use a systematic
strategy to achieve desired S21 and S22. We first used the parameters from
6
hand calculation for Hspice simulation to get the Zin_real and Zin_imaginary
across the entire band. Then we use equation (6) and (7) to compensate the
offset, which is usually within 15%. And we can use the systematic method to
achieve almost any desire S11 and S21 at certain frequency.
Ls (50 Zin _ real ( f 0 )) / wT (6) L g Zin _ imaginary( f 0 ) / 0 Ls (7 )
When moving to practical elements, the strictest constrain come from the
size of Ls which was 1.05nH in the ideal elements design. In order to have
such a low value we needed at least four bondwire. We also had to make sure
the substrate connected to Vss with less effect with inductance and
resistance from bondwires to have less substrate thermal noise and avoid
positive feedback through substrate. Since we have only 12 pads, we decided
to connect source to substrate and share the same four bondwaire to Vss.
Finally, we used 10 bondwire. Two set of 2-adjacents connections to Vss were
used by source and substrate with total 1.414nH inductance. Two-set of
2-adjacents connections to output were used to minimize the unwanted
resistor in the bondwires. The gate input inductance and the drain inductance
each used one bondwire to realize the inductance separately.
After using practical elements to design the circuit, we constructed a
systematic method to search for the bottom of the noise figure bowel surface
by changing two key parameters which is gm/id (relate directly to fT) and Id.
Firstly, we chose a Vdd<=2.5 and used the Pdc<=13mw constrain to get Id.
Then we systematically sweep gm/Id from 5 to 10. (Gm/id relates directly to
fT so is equal to 4f0 to6.5f0. And fT can’t be smaller than 3.16 to satisfy S21.)
We successfully found the minimum noise figure respect to different Id. A
graph of noise figure vs. gm/id subject to Id=6mA is shown in figure (2).
Figure (2)
The final task was to consider the bondwires’ values respect to the
package constrain and tried to minimize the die size. However, there are still
many effects will occur due to packaging such as pin inductance, bondwire
design in 3D, etc. I hope to learn more from the lecture. The package
7
diagram and package practical analysis is in the appendix.
IIII. Result and Conclusion
We believed that we did our best on reaching NFmin=0.69 in such a short
time. All of our successes realized on the greatness of gm/id technique and
the systematic strategy on finding the minimum noise figure respect to all
constrains. The process of finding minimum noise figure is also interesting. At
first we assume the noise is uncorrelated and almost perfect input power
match so we estimated NF=1.14 which is big. But after we loosened the input
power match constrain, we achieved NF=0.5536 with ideal elements.
However, after using bondwires to replace ideal elements, minimum noise
figure increased to 0.69 (dB) due to the parasitic resistor on the bondwires.
Lecture note of LNA, page 22, equation (7) showed that the minimum noise
figure equals to 0.739(dB) which is very close to 0.69 (dB) that we achieved.
Table (1) shows the whole design results from hand calculation, design
Fm in 1 1.16 * 1.2 * 2 / 3 1 (8)
T
with ideal element, to the final practical design. The design procedure
excel spread sheet is in appendix. We also did some simple robustness
analysis as varying the resistors’ values showed in the appendix.
We are very happy with the performance of the LNA since this is our first
LNA project. The most exciting moment is the moment we think of a
systematic strategy to sweep for the best noise figure respect to different
gm/id and maintaining the S11 and S21 in specification at the same time. We
will remember this experience and try to have a feasible systematic strategy
in every future project.
Table (1)
Ideal Element Final Result
Desire Hand
Spec Calculation 1.8GHz 2GHz 2.2Ghz 1.8Ghz 2Ghz 2.2Ghz
Pdc(mw) 13 10 11.5485 11.5485 11.5485 12.0937 12.0937 12.0937
|S11|(dB) <-10 -24 -11.3813 -13.5625 -10.7292 -10.1445 -13.6927 -14.4193
|S21|^2(dB) >10 13.9 12.3545 11.3907 10.2466 11.2055 10.7594 10.2263
NF(dB) min 1.476 0.553688 0.60789 0.744209 0.690129 0.769082 0.939602
IIPS(dBm) >-5 11.2* 10.29 10.29 10.29 11.01 11.01 11.01
*using equation (5) and assuming C1 =C3
Appendix
8
LNA Performance
Performance Sensitivity to Rbias
9
Die Size Calculation
10
The goal is to achieve minimum die size under the constraints of LNA circuit
layout and physical bond wire length. We didn’t include any in-chip passive
element in our LNA design, so circuit area is extremely small; focus should be
put on the satisfaction of bond wire interconnection.
There are 4 wires of 1mm minimum length (2 by 2 adjacent), therefore, we
place our die in the bottom-left corner, as close as possible to the border.
Assume
L1=0.1mm (Chip to Pad)
L1
L2=0.4mm (Ground plane to Chip)
L2
L3=0.5mm (Pin to Ground plane)
L3
The rest 6 wires are two pairs of adjacent wires of length 4mm and 6mm,
other two wires are 3mm and 7mm respectively. We design our ship in shape
of rectangle. Then place the three longer lines (6mm x 2, 7mm) in the upper
side, the three shorter lines (4mmx2, 3mm) in the right-hand side. In this
way, both die length and width can be reduced to the minimum.
Die width= 8-(6-0.5-0.1)-(0.4) = 2.2mm
Die length=8-(0.4)-(4-0.5-0.1) =4.2mm
Die size= 2.1mm x 4.2mm = 9.24mm²
(Note)
13.8% of package area
Gross die number, 3150 (8inch wafer)
11
Hand Calculation Design Excel Spreadsheet
Power(Constrain) Vdd(w)< 2.5000E+00 Pdc(w)< 1.3000E-02
Gain(Constrain) S21(db)> 1.0000E+01 → ft/f0 > 3.1623E+00
→ ft(Hz)> 6.3246E+09
Freq f0(Hz)= 2.0000E+09 ft/f0 = 5.0000E+00
→ ft(Hz)= 1.0000E+10 → gm/id= 7.9856E+00
→ Vgs= 7.6155E-01
→ Vdd> 7.6155E-01 → Id< 1.7071E-02
Power Pdc(w)= 1.0000E-02 Vdd(v)= 1.5000E+00
→ Id(A)= 6.6667E-03
Id(A)
→ (Mn1)= 6.1000E-03
width I/w= 2.0168E+01 → w= 3.0245E-04
gm gm= 4.8712E-02
Bandwith_check Bandwith(Hz)> 4.0000E+08 → Q< 5.0000E+00
→ gm> 2.0000E-02 OK
Q= 2.0529E+00
Rsg= 50
Ls= 7.9618E-10 Lg= 7.3761E-09
resonate out
Ld= with Cdtot
Table (2): The values in the gray blocks are the design choices
12
