Lab Exercise - DOC by T08G2Yz


									                                                     Lab 4

 How to Use Xilinx ISE 12 Project Navigator and Floorplanner to investigate look-up tables (LUTs) and


Developed by Craig Kief, Engineering Faculty at University of New Mexico, Albuquerque, New Mexico.
Funded by National Science Foundation (NSF).

Lab Summary:

This lab will present design entry and simulation of registers and buffers. The student will be able to take the
mystery from FPGA design. It will show the difference between a clocked register and an unclocked buffer.
It will also investigate how the logic is created in the Look-Up Tables of the fabric of the Spartan Device.

Lab Goal:

The goal of this lab is to continue in the learning and use of the Xilinx design tools. The goal of the lab is to
introduce student to the “inner” workings of an FPGA through the use of an FPGA through the use of the FPGA
design tool called FPGA Floorplanner.

Learning Objectives

1.   Create a simple project in Xilinx® ISE 12 using the free software ISE WebPACK.
2.   Use the Xilinx® ISE 12 Schematic Editor to enter a design in Xilinx® ISE 12
3.   Compile and simulate the design. Investigate the implementation on the FPGA.
4.   Download the design to the FPGA board.

Method of Evaluation: Your grade will be determined by your instructor.

Time Required: 1 hour

Lab Preparation
    Read this document completely before you start on this experiment.
    Print out the laboratory experiment procedure that follows.

Equipment and Materials
Access to Xilinx software

 Software needed                                                                  Quantity
 The following items from the Xilinx:                              1
     free software ISE WebPACK
Additional References:
 Xilinx ISE 12 Software manuals found on Xilinx web site: and at the Digilent
  Corporations website at

Lab Procedure


Registers and Buffers serve a unique role in the digital world and as such, they are developed differently in
VHDL. This tutorial will explain what these devices are and the differences (and similarities) between the two
of them. The tutorial will then show how each of them is created in VHDL. The tutorial will display the RTL
created schematic associated with each. Although the RTL schematic provides a convenient method for
investigating the flow of designated systems, it really isn’t completely accurate in how the circuitry is actually
developed. The actual circuitry is created using items called Configurable Logic Blocks or CLBs. These internal
sections of the FPGA will also be investigated in an attempt to remove the “black box” magic of FPGAs and to
actually show the student how the hardware is dynamically configured using the supplied VHDL.
A buffer is nothing more than a repeater. It helps improve fan-out. Fan-out is the ability to drive many outputs
off of a single input without excessively loading the circuit. What you will notice is that the buffer’s output
changes as soon as the input changes. By comparison, a register is a one bit storage element. Since it stores a
single bit, it is the building block for things such as memories. It also changes values based on clock edges.
Figure1 shows the inner workings of the logic portion of the Spartan 3E FPGA. It is important to have
knowledge of the FPGA you are working with. If you are doing an extensive FPGA project, I highly
recommend you invest the time required to read the manual about the specific FPGA you are using and learn as
much as you can before you attempt to write the VHDL for your project. The main working components of the
FPGA are very simple. They consist of a D-flip flop (register), some control logic and a look-up table (LUT).
The LUT can be thought of as a file cabinet of basic function. The input control lines to the LUT determine
which function will be accomplished.

Figure1. Spartan 3E Slice
These functions consist of basic digital logic equations (such as AND, OR, XOR, etc.) and the average FPGA
consists of tens of thousands of these LUTs.

Figure2. Logic Placement in Spartan 3E
Figure 2 shows a top down view of the Spartan device. There are two main parts to the FPGA. These parts are
the Complex Logic Blocks (CLBs) and the Input/output Blocks (IOBs). Figure 1 shows a slice. Each CLB in the
Spartan 3E contains four slices and each slice contains two Look-Up Tables (LUTs) to implement logic.

Figure3. CLBs and Slices
Figure 3 shows the placement of the CLBs and Slices on the Spartan 3E. The number of slices contained in a
CLB is different depending on the family of FPGA chosen however, the general concept remains the same.
To begin this tutorial, start the ISE Project Navigator. Figure 4 shows the first screen that appears when you
launch Project Navigator.

Figure4. Starting ISE – New Project
This is where the location of the project and the project name are declared. The only recommendation would be
to not put spaces in the directory or the project names. Avoid directories such as “My Documents”.

Figure5 – ISE Project Selection
If you have recently performed tutorial one or two then these values will automatically be filled in. Even though
you can change parameters at a later time, getting them correct the first time makes it easier. Figure 5 shows
you the correct settings.

Figure6. Adding files
There are three main files associated with this tutorial. They should now be loaded into this project. By right
clicking into the sources pane, it is possible to add a copy of the project files. The project files are included at
the end of the tutorial but can also be downloaded from the wiki. In the design pane, right click and select to add
files. Add the three files shown in Figure 6. It is important to begin to look at this pane and the placement of the
files. The files should always show in a tree type of listing. By that, it means there should be a parent child type
of listing. The UCF should fall below the design files. It is very important to now spend time reviewing the
HDL to allow you to have the ability to understand how the code is developed. The fact that all three project
files show up with a green checkmark is a positive sign that at least the Xilinx software understands the design
and building of the files.

Figure7. Source file
If you double click on the regBuffer.vhd file shown in figure 7, you will open it up and it will allow you to be
able to contents. One key to proper HDL design is in the file naming. For HDL you need to build a module,
test a module, build a module, test a module, then build a system and test a system. Think Black box / plug-and-
play for your files. At this point in your learning process you will see that most of your projects will only
consist of one design file. That quickly changes. It is very common to see large VHDL FPGA projects with
tens or hundreds of design and test files. To organize this properly, use intelligent naming conventions. If you
have a module called an “adder” then name your VHDL file something intelligently like adder.vhd. Next,
create a tester module (called a testbench). An excellent convention would be to name your tester application
“adder_tb.vhd”. Later when it is necessary to go into the folder of various files, it will make life easier to find
the source file and it’s associated test file.

Figure8. Top Level View
By looking at the tree type of structure, it is possible to see the hierarchy of how files fit together. In figure 8,
the “simulation” radio button is pushed. This shows that at the top level, chip and chip type are displayed.
Below that is the testbench called regBuffer_tb. A testbench is not synthesizable code. It cannot be taken
down to the hardware. Its only purpose is to stimulate your design to perform testing. Always make sure the
testbench is highlighted before attempting to run the simulator. First, highlight the reBuffer_tb.vhd file and then
double click on the “Simulate Behavioral Model” button. Figure 9 is a snapshot of the resulting simulated
waveform. As can be observed, the buffered output is not controlled by the clock. The bufferout signal drops as
soon as the input drops. However, the register out signal is only effected by the combination of the input signal
and the clock.

Figure9. Simulation Results
In figure 8 (which was created by clicking on “Simulate Behavioral Model”) you can see how the testbunch is
shown higher than the Unit Under Test (UUT). If both of these files were on the same level, there would be
something wrong in your code. I would strongly recommend that a little time be spent reading through the
comments in the code for this project. A lot of time has been spent on these comments and they are very good
for learning VHDL. Also make sure you highlight the correct files to do the actions you desire.

Figure10. Launching RTL schematic
By double clicking on the “View RTL Schematic” logo shown in Figure 10, the RTL viewer is launched. This
viewer allows a designer to see how the Xilinx software believes the design should look. This is an excellent
debugging tool. In larger designs, often a signal will show up one clock pulse before or after when you think it
will arrive. This view will help you understand why.
Highlight the regBuffer.vhdl file and double click on “View RTL Schematic” under “Synthesize”. Choose the
“Start with a schematic of the top-level block” option. You will be presented with the black box shown in
Figure 11. The schematic tool is an excellent product for visualizing the circuit that the Hardware Description
Language (HDL) creates. Having read the previous section, you are aware that the circuit is actively created
with registers and LUTs however; this Register Transfer Level (RTL) view provides an excellent medium for
understanding and debugging your circuits.

Figure11. RTL Black Box
The first image that is presented is shown in Figure 11. This shows what the overall inputs (left) and outputs
(right) are developed as.

Figure12. Circuit Implementation
By double clicking on the black box in figure 11, figure 12 is presented. As shown, the registered output goes
through D-flip flop (fd). This is because the registered output is driver by the clock but, the buffered output is
not. As a result, its operation will be eratic. It is always good practice within a circuit with a clock
(synchronous) to drive all outputs based on the rising edge of the clock. Close the RTL view.
Next, this tutorial will explore a little more about what was discussed previously in the “Implement Design”.
Expand the “Place & Route” section.

Figure13. View of a slice
Double click on the “View / Edit Routed Design” selection. This will bring up the Xilinx FPGA editor tool.
Highlight the regist E17 list. Click on the circle with the red square at the top of the screen “Zoom selection” or
hit F11. It should highlight it as shown in Figure 13. Next, instead of a schematic view, it will be important to
see how the design is created with the slices. Double click on the red square. This will bring up figure 14. If you
zoom in enough, the register is visible.

Figure14. View of how register creates FF
As shown here, the register can be instantiated as several difficult items.

Figure15. Another view within a slice

Figure 15 is another view of slice information. The important thing to realize here is that there is no “black box”
magic about FPGA projects. If necessary, the design can drill down to the exact circuit for every item described
in the VHDL. What you should now do is to repeat this procedure with a simple circuit such as AND and OR
gates to see how the circuit is developed using combinations of registers and LUTs.


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