FPGA_TDC_poster09 by lanyuehua


									 On-Chip Processing for the Wave Union TDC Implemented in FPGA
                                                                                      Jinyuan Wu
                                                             Fermi National Accelerator Laboratory, Batavia, IL 60510, USA

                          The Wave Union TDC                                                                                                                                                                          An FPGA TDC with 20ps
                                                                                                                               Wave Union
                                                                                                                                                          0: Hold          1: Oscillate
                                                                                                                               Launcher B
                                                                                                                                                                                                                      or 10ps RMS Resolution
                                                                                                                                                                                                                      There are two major issues in the delay chain
                       Wave Union                         0: Hold           1: Unleash                                                                                                                                based FPGA TDC due to uneven internal delay in
                       Launcher A
                 In                                                                                                                                                                                                   the carry chain. (1) The bin widths are uneven and
                                                                                                                                                                                                                      depend on temperature and power supply voltage,
                                                                                                                                                                                                                      which must be calibrated as frequently as possible.
                                                                                                                                                                                                                      The auto-calibration functional block developed in
                                                                                                                                                                                                                      this work provides semi-continuous calibration that
                                                                                                                                                                                                                      converts the TDC measurements from bins to
                                                                                                                                                                                                                      picoseconds. (2) In many applications, the TDC
                                                                                                                                                                                                                      resolution is limited by the “ultra-wide bins”,
                                                                                                                                                                                                                      corresponding to the carry chain crossing at the
                                                                                                                        CLK                                                                                           boundaries of the logic array blocks. The apparent
                                                                                                                                                                                                                      widths of these ultra-wide bins can be several times
                                                                                                                                                                                                                      bigger than the average bin width. The “wave
                                                                                                                                                                                                                      union launchers” described in this paper are
                                                                                                                                                                                                                      designed to make multiple measurements with a
                 CLK                                                                                                                                                                                                  single delay chain structure, effectively to sub-
                                                                                                                                                         The “wave union launchers” are designed to
                                                                                                                                                         make multiple measurements with a single                     divide the ultra-wide bins in each raw
                                                                                                                                                         delay chain structure, effectively to sub-divide             measurement.        Several TDC schemes with
                                                                                                                                                         the ultra-wide bins in each raw measurement.                 resolutions in 20 to 10 picoseconds range
                                                                                                                                                         A wave union launcher creates a pulse train or               implemented in today’s low cost FPGA have been
                                                                                                                                                         “wave union” with several 0-to-1 or 1-to-0 logic             tested.
           1                                                                                                                                             transitions for each input hit.

                 Implementation Details

                                         The Wave Union
                                         Launcher A

                                                                                                                                    The Automatic Calibration Block

                                          The Wave Union
                                          Launcher B


                                                                                                                                              In (bin)                Out (ps)

                                                                                                                                                                                            After arrival of the input, the wave union launcher B starts to oscillate
                                                                                                                                                                                            launching a wave union into the carry chain. The carry chain/register array
                                                                                                                                                                                            structure takes 16 snap shots of the oscillation bit patterns in 16 clock cycles
  The “wave union launcher A” generates a pulse train with                                                                                     0                                            at 400MHz. The phase of the oscillation is determined by the arrival time of
  three logic transitions of which two are encoded.                                                                                                                                         the input signal. If the drift of temperature and power supply voltage is
                                                                                                                                                                                            sufficiently slow, it is reasonable to assume that the oscillation frequency is
  The “wave union launcher B” is simply a ring oscillator                   A DNL histogram is booked in the FPGA internal memory. Once all hits are booked into the                        stable and can be measured to a good accuracy after long time. Then in the
  enabled by the input and after the input level turns from 0 to            histogram, the lookup table (LUT) is integrated from the DNL histogram so that it outputs the                   16 snap shots, the locations of the logic transitions can be utilized to compute
  1, a pulse train with unlimited length and logic transitions is           actual time of the center of the addressed bin. The outputs of the LUT are the TDC times                        the arrival time of the input signal to a higher resolution through the
  generated.                                                                calibrated to the temperature and power supply condition during booking the previous 16K hits.                  processing block “SumHitD”.

                      Test Result                                                                                                     Remarks on Coarse Time Counters
                      Data Output                                                    RMS 10ps
 Two NIM
                      via Ethernet
  inputs                                                                                                                                                                              000                                                           Coarse
                                                                                                                                             Coarse                                   001                                                            Time           Coarse Time
                                                                                                                                              Time                                    011                                                           Counter
                                                                                                                                             Counter                       Gray       010                       In
                                                                                                                                                                                      110                                                                           Fine Time
                                                                                                                                             Coarse                                   111
                                                                                                                                              Time                                    101
                                                                              0           1       2

                                                                                  The left-most peak (which partially rolls
                                                                                  over to the right edge) corresponds to the                                                                                    CLK
                                                                                  time difference of two input NIM signals                                                                                                                                          Data Ready
 BNC adapters
      Adapter                FPGA with
                                                                                  without any BNC adapters. The second                                                                                                           Hit Detect Logic
 to add delays
to add delay @                8ch TDC                                             peak from left corresponds to one BNC
 @ 140ps step.
  140ps step.                                                                     adapter inserted into one of the NIM
                                                                                  signal and the third peak corresponds two                                                                                   While the fine time is being encoded, a hit valid signal is being
                                            Wave Union TDC B                      BNC adapters inserted, respectively, as            Double counters driven by both edges of the                              generated by the hit detect logic. It is used to enable latching
                                            Wave Union TDC B                      shown in the photograph of the module.             system clock and the Gray code counters are                              of the coarse time. The uncertainty of the relative timing
                                NIM/                                +
                                            Wave Union TDC B
                                LVDS        Wave Union TDC B                      As expected, the separation between                popular choice for TDC coarse time counters, but                         between the hit and the CLK is confined in the register array
     LeCroy 429A                                                        -
                                            Wave Union TDC B                      peaks is about 140ps.          Each peak           they are only necessary for one type of TDC                              and all other signals are derived from the output of the register
     NIM Fan-out                NIM/        Wave Union TDC B                      contains 16K events and the RMS                    architecture found in ASCI TDC. For FPGA TDC,                            array. Their timing is well-defined by the CLK and they are
                                LVDS        Wave Union TDC B                      resolution of each peak is about 10ps.             plain binary counter is sufficient.                                      staged into the process pipeline.
                                            Wave Union TDC B

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