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CMOS transconductance amplifiers, architectures and active filters: a tutorial E.Sanchez-Sinencio and J.Silva-Martinez Abstract: An updated version of a 1985 tutorial paper on active filters using operational transconductance amplifiers (OTAs) is presented. The integrated circuit issues involved in active filters (using CMOS transconductance amplifiers) and the progress in t h s field in the last 15 years is addressed. CMOS transconductance amplifiers, nonlinearised and linearised, as well as frequency limitations and dynamic range considerations are reviewed. OTA-C filter architectures, current-mode filters, and other potential applications of transconductance amplifiers are discussed. 1 Introduction (or by using bipolar transistors) and about two octaves for MOS transistors operating in strong inversion. An operational transconductance amplifier (OTA) is a volt- The IC pioneer works on transconductors using BJT- age controlled current source (VCCS). The authors present JFET and CMOS were reported in 1980 [3, 41, 1981 [5]and an updated version of a tutorial paper published in 1985 1984 [6],respectively. In 1985 an invited tutorial paper on [l]. One of the first papers on OTAs in the literature OTAs [l] served to motivate a number of researchers to appeared nearly 30 years ago [2]. T h s paper described a investigate new CMOS OTA architectures and their appli- bipolar OTA. At that time the emphasis was on amplifiers cations. For readers not familiar with OTAs, we suggest with feedback, such as op-amps. Thus the commercial they read [l] to understand the background needed to take OTAs were not meant to be used in open loop mode. The advantage of this tutorial. A number of significant contri- maximum input voltage for a typical bipolar OTA is of the butions have been reported since 1985, including OTAs for order of only 30mV, but with a transconductance gain tun- open loop applications such as continuous-time filters, mul- ability range of several decades. Since then, a number of tipliers, nonlinear circuits and closed loop applications researchers have investigated ways to increase the input mainly for switched-capacitor circuits. The importance of voltage range and to linearise the OTA. Some of the key the OTA is reflected by its inclusion in the textbooks [7-91. attractive properties of OTAs are their fast speed in com- parison with conventional low output impedance op-amps, 2 Transconductanceamplifiers: topologies and their bias dependence transconductance programma- bility (tunability). The wideband of the OTA is due in part An ideal transconductance amplifier is an infinite band- to the fact that their internal nodes are low impedances. width voltage-controlled current source, with an infinite However, the internal low impedance and parasitic capaci- input and output impedance. As shown in Fig. la, the tance still cause a non-zero transconductance phase shift, simplest single input real transconductor is a MOS driver known as ‘excess phase’ When the OTAs are con- transistor M1 operating in the saturation region. One of nected in a system in closed loop, the excess phase makes several drawbacks of this simple transconductor is its rela- the actual frequency response deviate from the ideal case, tive low output impedance. Several alternatives have been especially for high-Q systems. In the extreme case, the sys- suggested to alleviate this problem. Figs. 1 &d show a tem may become unstable if the excess phase is not group of cascode transconductors with lugh output imped- reduced. The main characteristics of a practical OTA are: ance. Another useful simple transconductor is reported in (i) limited linear input voltage range, (ii) finite bandwidth, [lo]. It is often the case for Figs. l b and c that M1 operates (iii) finite signal to noise ratio (SIN), and (iv) finite output in the ohmic region [ll-151. This provides better linearity, impedance. The SIN is a function of the OTA architecture but the transconductance is reduced in comparison with among other factors. The output impedance can be M1 operating in saturation. The amplifier A further increased using cascode structures at the expense of increases the output resistance of the circuit shown in reduced output signal swing. Their programmability is Fig. IC; a simple MOS inverter or a bipolar inverter could caused by the transconductance C bias dependence; this , ) g replace the amplifier. Also, M2 in Figs. lb and c can be dependence allows several decades of tuning for transcon- replaced by a BJT. The typical folded cascode structure is ductance with MOS transistors operating in weak inversion illustrated in Fig. Id. A summary of the properties of these structures, when all transistors operate in the saturation 0IEE, 2000 region, is given in Fig. 2. If a positive simple g, is required, IEE Proceedings online no. 20000055 the circuit of Fig. le is a possible implementation. Fig. lf DOL lO.lO49/ip-cds:20000055 represents the symbol for the OTA with differential inputs, Paper fmt received 21st July and i revised form 4th November 1999 n along with the ideal small signal equivalent circuit [16]. The authors are wt the Analog Mixed-Signal Center, Texas A&M University, ih Note that g, is a function of the amplifier bias current, labc. College Station, Texas 77843-3128, USA For the case of OTAs using MOS transistors in saturation IEE Proc.-Circuits Devices Syst., Vol. 147, No. 1, February 2000 3 U a b C d e f Fi .1 Single input circuits a 8egative simple transconductor b Cascode transconductor c Enhanced transconductor d Folded-cascodetransdonductor e Positive simple transconductor f OTA symbol representation and equivalent model Structure/ %"t Min V D D * Figure Simpleila 1 - g,, Cascodellb gm2 gddgds2 Enhancedk Agm, gdsIgdr2 Foldedld gm2 gdslgds2 Fig. 2 Properties of simple transconductors * The bottom devices of the cdscode pairs have an aspect ratio of (W/L),/( W/L)2= d. is a technological parameter determined by the mobility, and the gate k oxide; Vra,,,8 the saturation voltage for the IB current source is a b C e Fig.3 Drfferential OTAs a Smple differential OTA b Balanced OTA c Conventional fully differential OTA without CMF d Fully differential OTA with inherent CMF e Pseudo differential OTA, CmA= G m ~ 4 IEE Proc.-Circuits Devices Syst , Vol 147, No. 1. February 2000 the g,,s are proportional to dIObc;for MOS transistors oper- these topologies, the signal is referred to differential signal ating in weak inversion or bipolar transistors the g,s are paths instead of to the commonly used analogue ground. directly proprtional to Iabc. observe that the ideal Also The differential circuits are fully symmetrical, as shown in OTA has an infinite output impedance; in practice the out- Figs. 3c and d, and their main advantages are due to this put resistance Routis as shown in Fig. 2. The circuits of characteristic. The supply noise is injected to both OTA Figs. la-c can be modelled by the symbol of Fig. If when outputs with the same amplitude and same phase, hence one of the inputs is grounded. A non-ideal OTA macro- they can be considered as common-mode noise. If the fully- model [171 will have finite input and output impedances, differential transconductor presents nonlinear characteris- and g, will have a single pole model to be discussed later. tics, the output currents, for v2 = v; and v1 = vy, can be Next, we discuss the basic transconductor (OTA) topolo- expressed by the following series expansions: gies with differential inputs. Fig. 3a shows a basic differen- tial input OTA with one current-mirror; in Fig. 3b a balanced OTA with three current mirrors and a single out- put is shown. Fig. 3c illustrates a fully differential OTA; the common-mode feedback [18] is not shown. Fig. 3d is a and really symmetric architecture, which has inherently com- mon-mode feedforward (CMFF) [19, 201. Also note that to z+ - 2' 0 2 = IB1 0 - + Q(W2 - v1) + m(v2 - Vd2 obtain very high output impedance, the amplifier A in + Q(V2 - + .. . (2) Fig. IC might be substituted by the OTAs of Fig. 3a or where IBI is the amplifier bias current. It is evident from Fig. 3b with the proper frequency compensation to guar- these expressions that an inversion of the dlfferential input antee stability. The complexity of these structures is also signal produces an inversion on the odd-order terms, while accompanied by an improvement in offset reduction and it has no effect on the phase of the squared components robustness, but not necessarily with an improvement for (even-order distortions). The even harmonic distortion high-frequency applications. Thus trade-offs between speed components appear at the outputs with the same amplitude and accuracy should be established for each particular and same phase, and they ideally cancel each other when application. Note that the circuits in Fig. 3 do not have the differential output current is processed. In practice, very high output impedance. To accomplish that, the OTA process parameter tolerances and temperature gradients output branches should be replaced by the architectures introduce transistor mismatches, avoiding the complete illustrated in Figs. 1 M . To yield an improved perform- cancellation of common-mode signals. An additional ance, the simple current mirrors of Fig. 3 are often substi- advantage of fully differential systems is that the output sig- tuted by enhanced current mirrors (see [Iand [21], Chap. nal swing is larger. According to eqns. 1 and 2, the funda- 6). mental output component at each output is given by - q $ d , A suitable architecture for low voltage power supply is while the differential output (iod io, - io2)is -2a1vLd, = where the pseudo-dlfferential transconductance [19, 20, 221. It vid = q - vl. The main advantages of a fully differential consists of two single input transconductors (see Figs. l a 4 , topology are due to its symmetry, making the structure less and it looks like a differential pair, with the tail current of sensitive to common-mode signals. However, mismatches the differential pair substituted by a short-circuit. This con- in the N-type and P-type current sources might push both figuration needs to have a common-mode circuit to drasti- OTA outputs to the supply rails, and due to the differential cally reduce the common-mode voltage gain. One approach nature of the system this effect is neither detected by the [19] consists of using an additional, two (equal) output next stage nor corrected. To overcome t h s shortcoming, a current transconductor, with non-differential inputs as common-mode feedback loop (CMFB) that controls the depicted in Fig. 3e. Note that the transconductor B does operating point is commonly used. The design of the not have a differential output, but has two equal outputs CMFB [181 is not straightforward because the main signals which are added to the pseudo-differential transconductor are differential and the common-mode signals must be such that common-mode signal can be rejected. T h s struc- detected and suppressed with simple and fast circuitry. The ture utilises a common-mode feedforward (CMFF) circuit circuit must present a very small impedance for the com- implemented by the double input transconductance ampli- mon-mode signals but be transparent (very high imped- fier B. The performance of single-ended structures can be ance) for the differential ones. The basic concept of the further improved by using fully differential topologies. In CMFB loop is shown in Fig. 4. The output voltage for this Ta 21B b Fig. 4 CommonrnoakJebUckbmic circuit concept a Basic common-mode detector b CMOS CMFB implementation IEE Proc.-CircuitsDevices Syst., Vol. 147, No. I , February 2000 5 circuit is taken across the drains of the transistors M,. be made small, such that io yields: Fig. 4a shows conceptually a basic OTA with a common- 03 03 mode detector implemented by two resistors. Practical solu- tions can be found elsewhere [18, 22-26]. The common- i=l i=l mode signals are sensed by averaging the OTA outputs, M M and compared with the AC ground (AC GND in Fig. 4) by the additional differential pair composed by the M , 2=13=1 transistors, and the resulting current is used to adjust the bias current of the main OTA. The common-mode open Thus a basic linearisation idea consists of attenuating the loop impedance (Rcmfb l/g,,fh(s)) is determined by the = input signals by a factor k. This attenuation yields a line- small-signal transconductance of the common-mode loop. arised approximation that can be expressed as Transistors Mc, compare the common-mode voltage with the AC ground, and transistors M, mirror the resulting iO(Vl,V2) 2 k g m ( v 1 - .2) (7) current to the OTA outputs. As a result, the common- There exist several practical techniques to implement the mode transconductance is determined by transistors M . , attenuation factor. The concept is illustrated in Fig. 5a. The The parasitic pole of the common-mode loop is associated circuit in Fig. 5b is often used for commercial discrete with the current mirror, transistors M, in Fig. 4, and OTAs. Figs. 5c-e refer to attenuation to the driving transis- reduces the loop gain at higher frequencies. This yields: tor M1 in Fig. 1 and to M1 and M2 (differential pairs) of Scm Fig. 3. The use of floating gate techniques ([21], chaps. 5 gcmfb(S) (3) and 6) as depicted in Fig. 5c yields a capacitance divider, (1 + s-) S?nP where C, and chiaT are the capacitances associated to the , where the subscript refers to parameters of M,. The fac- input signal vI and the bias voltage, respectively. Fig. 5d shows a bulk driven transistor [27-301 attenuation tech- tor 3 appears due to the connection of three transistors in nique, which can operate at low and medium frequency node A. The operating point of the OTA outputs (vol + ranges. An active attenuator [31] with good linearity is illus- vO2) is forced by the CMFB to be around the analogue trated in Fig. 5e. In these linearised schemes, the OTA ground (i.e. an appropriate DC bias voltage). Note in deals with an attenuated version of the input signal. To eqn. 3 that due to the parasitic pole the common-mode compensate this attenuation, the transconductance gain transconductance is reduced at hgher frequencies, hence must be increased by the same factor, increasing both increasing the common-mode impedance and being less power consumption and silicon area. If the noise contribu- eficient for the rejection of common-mode signals. For the tion of the attenuator is negligible, the input referred ther- common-mode feedback loop two poles should be consid- mal noise of the transconductor (attenuator and OTA) ered. The dominant pole is associated with node V l (and O increases by the square root of the attenuation factor. and VO2), the non-dominant pole is associated with node A. Similarly to the typical differential loops, the phase margin must be larger than 45", otherwise common-mode oscilla- tions could appear in the system. As a rule of thumb, the common-mode gain-bandwidth product (gcm/CL) must be smaller than the non-dominant pole (g,d3Cgsp)obtained in b eqn. 3. Ideally the bandwidths for both differential and a common-mode gains should be comparable. Q 3 Linearisationtechniques The structures discussed in the previous Section are nonlin- ear, which means that they have a very small input voltage range yielding say 1% total harmonic distortion (THD). A solution to this problem requires techniques to linearise the Fig. 5 Attenuation implementation transconductor. There are three types of linearisation tech- a Conceptual; io = a,(kV) + uZ(kv)' + a3(kV3 + ... niques reported in the literature, i.e. (a) attentuation, (b) b For discrete OTAs, k = R2/(R,+ Rz) c Using floating gate techniques k E Cj(C,+ Cbm) nonlinear terms cancellation, and (c) source degeneration. d Using a bulk-driven transistor k = y, 0.2 < y < 0.4 e Active attenuation k = 1 - l/d(l + W,&/W&,) for VT, = V,, The ideal output current of a differential input transcon- ductor is More elegant techniques exist to linearise transconduc- iO(V1,VZ) = (U1 - v2)gm (4) tors by means of an optimal algebraic sum of nodnear where vI and v2 are the positive and negative input signals terms [7, 21, 32-39] yielding ideally only a linear term. of the transconductor. In reality, since the transconductors Fig. 6 illustrates the conceptual ideas of this linearisation use MOS transistors for their implementations, they are technique. This can be done in practice by interconnecting nonlinear devices. For simplicity of the discussion we will several transconductances, which ideally will cancel the assume only nonlinearities of practical interest. In general, nonlinearities yielding only a linear relation between the we can assume that io(vl, v2) is given by input voltage and the output current. In fact, the same M M 0000 techniques to obtain multipliers [32] of the type of k x are ,y applicable to linear transconductors, where k, is a multipli- cation constant and one of the inputs x or y becomes a DC constant. Practical implementations of Fig. 6 are shown in (5) Fig. 7. The transconductance [11, 33, 341 of Fig. 7a must From this expression we can infer that in order to have a operate its bottom transistors in the ohmic region, and the linear transconductor one option is that the input voltage top driving transistors in saturation. For proper operation 6 IEE Proc -Circuits Devices Syst.. Vol. 147, No. I , February 2000 of this transconductor the input signals should have a suit- able DC bias voltage. Furthermore, a variation of this transconductor can be obtained by applying the input sig- nals to the bottom transistors with appropriate DC gate bias for all transistors, to keep top and bottom transistors operating in saturation and ohmic regions, respectively. The transconductor [39] of Fig. 76 is an example of the implementation of structure of Fig. 6b; the floating voltage a b source (V,) can be implemented in several practical ways Fig.8 g, linearisation schemes via source degeneration ([21], Section 7.22) including a simple source follower. Linearisation techniques employing source degeneration [23, 41451 are often used. Figs. 8a and b illustrate two pos- sible implementations. Although both topologies realise the same transconductance, they present different properties. Fig. 8a, the noise contribution of the current sink is divided in both branches appearing at the outputs as common- mode noise. For the structure in Fig. 8b, the noise of each current sink is injected to a single output, appearing as a vA differential noise current. On the other hand, the voltage drop at the resistors of Fig. 8a reduces the common mode swing of the input signals; this is particularly critical for low-voltage applications. For the source degenerated struc- v2 ture, the output current is related to the input voltage by the following relationship [44]: (4 - +N ) Vid (8) where N (= G,R) is the source degeneration factor. T h ~ s expression can also be used for the conventional differential pair with N = 0. From this equation, the small-signal transconductance and the third harmonic distortion can be found; the resulting expressions for the elementary differen- tial pair and source degeneration structure are given in b Fig. 9. While the linearisation scheme reduces the small Fig. 6 General tranrco&Ctmce lineurkation by nonlinear t e m .YZM? cmcel- signal transconductance by 1 + N , the third harmonic dis- hlion tecvlrques tortion is reduced by the square of the same factor. Note a Using single multipliers by a constant ( , v ) b Using single-quadrantdevlces; V, = -Vz that increasing the source degeneration factor the harmonic distortion is reduced even if the saturation voltage is lim- ited. This additional degree of freedom is an important advantage of these structures. The derivation of the input referred noise is tedious, especially for source degenerated topologies. The results for Fig. 8b are given in Fig. 9. In those expressions, gnIp and g , are the small-signal transconductance of the transistors used as P-type and N- type current sources, respectively. For a lossless integrator and if the input referred noise density is integrated up to the unity gain frequency, the linearised integrator's dynamic range can be approximated as follows: , a , '"'y 0 ' i" where the noise factor NFsd is l V A 1 These expressions apply to the simple differential pair b based OTA with N = 0. The source degeneration OTA Fig. 7 Trun~codctmce noise factor is larger than that of the elementary differential a Based on Fig. 6a. Note that the input signal might need a DC bias based OTA, mainly due to the noise contribution of the N- b Based on Fig. 6b; VA = 2 V , type current sources, and can be maintained at low levels if IEE Proc-Circuits Devices Syst.. Vol. 147. No I , February 2000 7 I I I I Parameter Differential pair Source degeneration Small-signal G,,,d =% l+N transconductance I Third Harmonic Distortion I HD3=-?-[zl2 1 W33) Input referred thermal noise density 1 32 VDSAT :E['+%) 1 - 71kT 16 ,+ Current consumption* 21, 2(1+ N)I, Transistor dimensions* W - (I + N)-W L L the small-signal transconductanccs.of the current sources degeneration factor (N). Scaling up both transistor dimen- are reduced. Although the noise factor is slightly larger, the sions and drain currents compensates this reduction. The linear range is increased by a factor (1 + N). More detailed benefits of the source degenerated structures are seen in discussions on noise are given in [4&48]. Regarding opti- terms of higher power consumption and additional silicon mal dynamic range see [49]. In general, the source degener- area. Sometimes, the bandwidth (BW) of linearised OTAs ation reduces the small-signal transconductance by the is also severely limited, especially if many additional nodes are introduced. The BW issue will be discussed in Section 4. 66 What follows is a discussion on the implementation of the resistors R of Fig. 8. These realisations involve MOS transistors either operating in the ohmic region or in sat- uration. Three popular implementations of the R for the linearised OTA are illustrated in Fig. 10. The advantages and disadvantages are summarised in Fig. 11. Observe that I a combination of these linearisation techniques can be a b implemented in a circuit, Of course each addition of a line- arisation scheme will improve the overall performance at the expense of a reduction of the transconductance gain. The authors in [44] use two source degeneration techniques I I I and current addition to partially increase the linearised transconductance gain, yielding a well linearised OTA. Other authors have combined resistors with parallel combi- nations of transistors operating in triode and saturation regions [50, 511. In real OTAs the transconductance gain has a finite bandwidth. This can be modelled as a first-order low-pass, i.e. G = G,d(l + s/Bw). For open loop applications the , I I resulting excess phase = wIB W can be compensated by C either connecting two OTAs in parallel [17] with one of the Fig. 10 Active source degenerutwntopologies OTAs with reverse input polarity; another approach for a, b Transistors biased on triode region c With saturated transistors integrators consists of adding a resistor [42] in series with ~~ Reference/Figure Transconductance Properties gml Low sensitive to common-mode input Ref [43]/Fig. 10a 7 1 + 1 signals. The linear range is limited to 4/33 V,,<VDSAT, THD - 50 dB. and M l = M 2 . M 3 =M 4 gm1 Highly sensitive to common-mode input Ref [34]/Fig. 10b signals. For better linearity large VGS3 l+g,lR voltages are required. Large tuning range if -vT) V, is used. gm1 Low sensitive to common-mode input Ref[40l/Fig. 1Oc signals. Limited linearity improvement, Ml=M2=M3 HD3 reduces by -12 dl3. More silicon area is reouired. Fig. 11 Properties of OTAs using source degenerutwn 8 IEE Proc.-CircuirsDevices Syst., Vol. 147, No. I . Februury 2000 the integrating capacitance. These techniques are illustrated capacitance voltage divider. For high-frequency applica- in Fig. 12. The RC compensation shown in Fig. 126 con- tions, a number of parasitics [55] and finite OTA band- sists of replacing R by a transistor operating in the triode width can affect the filter performance. For instance, for a (also called ohmic) region. Note that changing g, requires second-order bandpass filter, the actual quality factor Q, is adjustment of R in Fig. 12b. Another particular case of limited by the finite output impedance (or equivalently the phase compensation consists of connecting an optimal finite voltage gain) and the excess phase (&) of the value capacitor [42] in parallel with the resistor associated transconductance amplifier. Assuming equal OTAs in the with the source degeneration linearisation technique filter, Q, can be expressed as a function of the desired Q, (Fig. loa) discussed earlier. the DC voltage gain ( A f i )and the excess phase (@E), that is: V . M Qa = Q (11) 1+ 2 (&- $ E ) Q For the fully differential version the performance benefits are significant at the expense of increased power consump- tion and silicon area. Also the use of common-mode feed- Fig. 12 PIme rompmution technips for integrutm back circuits [I81 is often needed, although under some (I Active conditions, typically with all lossy integrators filters, t h s 6 Passive CMFB can be avoided [19, 561. Current-mode filters might be generated based on OTA- C filters. Assume in the OTA-C version that every OTA with a load Z at the output will be substituted by an input load 2 followed by the OTA. In this last case the signals at the output and input are current. In the practical imple- mentation of current-mode (CM) fdters [20, 57, 581 the transconductance is of the type shown in Fig. 1, thus they are pseudo-differential types, which usually involve cross- coupled connections to enhance their common-mode per- formance. The current-mode filters frequently operate at very hgh frequencies, but often suffer high-sensitivity and good layout transistor matching becomes a vital task. Tuning: Critical IC fiters are frequently based on reso- nant loops. For the two-integrator loop shown in Fig. 13, the resonant frequency and the filter bandwidth are given in Fig. 14, where the load of each integrator consists of a capacitor and an OTA with a finite output resistance. l/gol, l/gO2and I/go3are the finite output resistances for OTA1, w OTA2 and OTA3, respectively. In the case of resonant loops cgn13 = 0), the pole frequencies are not very sensitive to the OTA finite DC gain. Notice that even if the OTA "in DC gain (gml/gOl) only around 50, the frequency error is is typically below 1%. The non-dominant pole (up,,,) intro- b duces excess phase in the integrators; fortunately, the reso- Fig.13 Two-integer bipmls nant frequency has low sensitivity to these effects too. On a Single-ended the other hand, both OTA finite DC gain and non-domi- h Fully differential nant poles affect the fdter bandwidth (see eqn. 11). For narrow-band applications gm3 must be reduced, therefore 4 Transconductance and current-modefilters the factor (go, + g02)/gm3 increases, leading to large band- width errors (see Fig. 14). Usually cascode output stages There are two common techniques [8] to implement OTA- reduce these errors. The effects of the non-donlinant poles C filters: (U) cascade of biquads [l, 8, 52, 531, (b)RLC emu- are quite important for high-Q fdters even if the second lation either by implementing the equations describing the pole is placed at very high frequencies. As an example, for passive prototype [54] or by direct simulation of compo- U,,,,, = 1 0 0 9 and Q = 10 the bandwidth errors are in the nents ([6, 81 and [21], chap. 10). The two-integrator loop range of 20Yn [59]. biquad is one of the most popular structures. The single- Among the effects previously discussed, both tempera- ended and the fully differential versions are shown in ture variations and process parameter tolerances affect the Fig. 13. The structure provides a lowpass (LP) output at precision of OTA-C fdters. The main characteristics of v02; if a bandpass (BP) is required the input OTA &bo) is OTA-C filters are determined by the integrator's time con- injected instead to node vO1 into the node vO2.Many other stant C/g,. Typical tolerances for both C and g,n are in the combinations yielding different types of filters are possible range of +30%, and these variations are uncorrelated, lead- and are well documented in the literature [l, 7, 8, 211. The ing to very large variations in the filter characteristics. The biquad in Fig. 13 has suitable properties for high-frequency accuracy of the OTA-C filters can be further improved by applications. For the single-ended biquad observe that one employing on-chp master-slave automatic tuning schemes could save an OTA by injecting the input signal to the pos- [ 3 4 , 21-25, 43, 59441. The basic idea behind these tech- itive terminal of the OTA (gml), this will cause a feed- but niques is to extract the most important filter characteristics forward path through the input capacitance of the OTA from a piece of additional hardware (the master system) &,pzl) and the capacitance C,; this creates an undesirable and to lock them to stable and very well controlled external IEE Pror -Circuits Devirer Syrt , Vu1 117, No 1. February 2000 9 rig. 14 OTAfinite parameters efftssfor byuad (Fig, 13a) on the resonantfrequency and bmdvulth conductance, respectively wP1,* and go],* are the non-dominant pole and output references, assuming a good matchmg between the master 5 Transconductance applications and slave systems. Very often accurate clock frequencies already available in the system are employed. Most of the Analogue multipliers play a very important role in several automatic tuning loops are based on phase locked loops. A applications as mixers in communications, analogue multi- voltage controlled oscillator is employed; for a two integra- plication for signal processors, adaptive schemes, program- tor loop-based oscillator the oscillating frequency is given mable neural networks, and automatic control systems. by g,/C. This frequency is tracked to a clock frequency Most of the high-frequency analogue multipliers are based generated by an external crystal, as shown in Fig. 15a. on the popular Gilbert cell. It is based on two differential From the error voltage the OTA small-signal transconduct- pairs biased by a third differential pair worlung as a voltage ance is controlled; for most of the differential pair based controlled current source. In fact, the Gilbert cell can be OTAs the bias current is adjusted. For efficient tuning it is considered as an array of OTAs [32]. In the same paper, a very important to minimise the mismatches between the number of different CMOS multiplier implementations are master system and the main fdter. Because OTA-C fdters also discussed. A shortcoming of several analogue multipli- ers is the temperature dependence of the multiplication are sensitive to parasitic capacitors, the parasitics must be coefficient. Using an additional OTA can efficiently com- considered when the master system is designed. Another pensate these effects [65]. tuning scheme employs a second-order bandpass filter, as Other nonlinear operations [66] that generate arbitrary shown in Fig. 1%. In this tuning scheme the centre fre- piecewise linear functions can also be implemented employ- quency of the BPF is tracked to the external frequency. For ing OTAs. As we discussed in previous Sections, for the narrow-band filter applications the filter bandwidth must tuning of OTA-C filters a control structure is employed. also be tuned. For this purpose, several approaches for Q- Based on these systems the realisation of automatic gain tuning and simultaneous frequency and bandwidth tuning control systems is straightforward [67]. The OTA-based have been addressed [22, 24, 59441. A Q-tuning technique amplifier is composed of two transconductors. The voltage yielding precision better than 1% for band-pass biquads is gain is very well controlled because it depends on the ratio reported in [MI. In contrast to other Q-tuning techniques, of transistor dimensions and the ratio of bias currents. in [64] no envelope detector circuits are involved. The Q- Both parameters can be controlled precisely in current tuning technique involves a pseudo least mean square CMOS technologies. By using a control loop driving the (LMS) implementation. bias current (transconductance) of one of the OTAs, effi- cient and low-distortion AGC systems can be realised. external clock OTA-C oscillators have also been proposed [21, 671. OTA-C filters have been used in many practical applica- frequency tions. Usually, high-performance filters for intermediate fre- quencies, video [4, 10, 15, 23-25, 45, 61, 68, 691, and disk oscillator filter drive read channels [26, 701 employ this technique. In most of these papers several interesting circuits, including auto- a matic tuning systems, are reported. The demand for hgher frequency applications is moving toward faster continuous- frequency time filters in the range of lOOMHz and beyond, as noted in several recent published works [22, 71-75]. Nevertheless, some challenges still remain before continuous-time fdters can be highly competitive at such high frequencies. Although many efficient tuning strategies have been b reported, most of them are not efficient above 100MHz. Fig. 15 Typicalfrequency tuning schemes Also, most of the linearisation schemes introduce parasitic a Based on a VCO 6 Based on a VCF poles, reducing their frequency response. 6 Conclusions The matching between the main filter and the tuning sys- tem is better if both systems are located very close to each A brief summary of the operational transconductance other and are as identical as possible. For high frequency amplifier has been given. Trade-offs of structures, technol- applications, signals generated by the tuning system are fed ogy implementation (CMOS, bipolar or BiCMOS), and through the substrate and parasitic capacitors and appear speed are very much application dependent. Several of the at the output of the main filter, reducing the filter signal to design issues for hgh-performance continuous-time filters noise ratio. Shielding both the main filter and automatic have been addressed. There are still many open problems in tuning system reduces these signals. Other techniques use frequencies higher than 100MHz, and it is very challenging frequencies in the filter stop band to reduce these effects for frequencies of around a few gigahertz [76] where other [25, 591. non-conventional process technologies are employed. IO IEE Proc -CircuitJ Device5 Syst , Vol 147, N o I . February 2000 7 Acknowledgment 29 DIELACHER, F., HAUPTMANN, J., REISINGER, J., STEINER, R.R., and ROJER, H.: ‘A software programmable CMOS telephone circuit’, IEEE J. Solid-State Circuits, 1015-1026, 26, (7), pp. 1991 This paper was partially supported by the Mixed-Signal 30 BLALOCK, B.J., ALLEN, P.E., and RINCON-MORA, G.A.: Group, Texas Instruments Inc., Dallas, TX, USA. ‘Desipng 1-V op amps using standard digital CMOS technology’, IEEE Trans. Circuits Syst. 11, Analog Digit. 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