ARGOS-GG

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					                              Broadband FFT Spectrometer
                                       ARGOS
                                        First results




ETHZ
Institute of Astronomy
Christian Monstein
Scheuchzerstrasse 7
CH-8092 Zürich
monstein@astro.phys.ethz.ch                             ARGOS-GG.ppt, 14.04.2005
                                            Content
•   Specifications, block diagrams
•   FPGA, VHDL, resource table
•   Schedule, cost, additional information
•   KOSMA block diagram, measurement methods
•   Gornergrat impressions
•   Measurements in the laboratory
•   Spectrum results
•   Software, GUI
•   RF-overview Gornergrat 3100m, Bleien 420m and Diavolezza 3000m
•   Conclusions

               FPGA = Field Programmable Gata Array
               VHDL = Very High Speed Integrated Circuit Description Language
               KOSMA = Kölner Observatorium für SubMillimeter Astronomie
               GUI = Graphical User Interface
               RF = Radio Frequency
                                         Specifications
Parameter                                         Value                          Comment


2 x AD-conversion                                 2 x 1GS/sec                    Interlaced 500ps → 2GS/s
                                                                                 Rate : programmable
Input resolution                                  8 bit voltage                  → 48.1 dB power

Max number of channels                            16’384                         fixed

Channel spacing                                   61.035KHz                      At full sampling rate

Conversion time                                   16.384µsec                     → 1 single integration step

Internal data width                               18 bit                         Twiddle factors etc.

Minimum accumulation time                         1ms (64 integrations)          At PC duty cycle ≈ 50%
Maximum accumulation time                         70’000 sec (≈ 1 day)
Windowing                                         Programmable filter            Kaiser, Hanning, etc.

Output data                                       PCI interface 32bit x 33 MHz   Internally 36bit

              PCI = Peripheral Component Interconnect (local bus standard)
              AD = Analog Digital Converter
                             Block diagram AC240
                                        Opt.                Opt.
                                       DRAM                SRAM


                                        Digital processing Unit
    Additional digital l/O                       FPGA
    from/to telescope
    Analog output                         Xilinx Virtex-2 pro
                                               XC2VP70




                                                                          2 x 128 bits
                                      Δt=0.5nsec

             Preamp                   ADC 1
 Ch1                                                  Demux 1
              1GHz                    1Gs/s
                                                      8 bits x 16
                             Cross     8 bit
                             Point
             Preamp          Switch   ADC 2
 Ch2                                                  Demux 2
              1GHz                    1Gs/s
                                                      8 bits x 16
                                       8 bit


                                       Time                            PCI               PCI
Ext           Trigger                              Controller
                                       Base                         Interface            Bus
trigger

Ext
clock
PCB AC240 with FPGA
                      Block diagram AC240

                                                                            1 Gs/s
                                                                            complex
          even
                                      16 k FFT
                                      Pipeline                    Post
                          Σ                                    Processing
2 Gs/s                               complex input                Unit
real                                complex output                          Redundant
                                                                            data
                      j
          odd

                          1 Gs/s
                          complex                    1 Gs/s
         2 x 1 Gs/s                                  complex
         real
32K FFT with 2Gs/sec throughput




        125MHz   125MHz
            Overview of AC240 FDK core
                DDR S DRAM                      DDR S DRAM                        ort RAM
                                                                            Dual P S
                Extension (512MB)               Extension (512MB)           Extension



                   DDR Controller A                DDR Controller B                ort
                                                                             Dual P Interface
                WR Buffer      RD Buffer        WR Buffer       RD Buffer



I/O Extension

                                                     User-Defined
                                                                                                Local
                                                     Processing Block                           Bus
Data Link




Data Link




                                      Trigger               MAC100              MAC100
VHDL design with MENTOR tool




                     Design Entry : HDL Desinger 2004.1a
                     Simulation   : ModelSim 5.8c
                     Synthese     : Precision RTL 2004.a1
                     Place & Route: Xilinx ISE 6.2i
Utilization FPGA resources




    • No use of internal Power-PC (gray area) foreseen
    • Purple = input structure and programmable window
    • Yellow = pipeline #1, green = pipeline #2
    • Violet = output structure
    • horizontal structure = Block-RAM and multipliers
Xilinx FPGA Virtex II XC2VP70-6
           resources

 –   Slices       29‘247    88.4%
 –   Flip Flops   38‘272    57.2%
 –   Block-RAM    300       91.5%
 –   Multiplier   192       58.5%
 –   fmax         138 MHz   (required: 125 MHz)
                              Schedule

                                              Planned       In fact

1. Start of KTI-project:                      2003-11-01   2004-11-01

2. Decision system architecture:              2004-03-18   2004-03-18

3. Preliminary tests of 1st implementation:   2004-08-30   2004-09-30

4. System ready for Radio Astronomy:          2004-12-20   2005-03-18

5. Scientific analysis, fist results:         2005-03-07   2005-04-05

6. End of project, closing report to KTI:     2005-04-02   2005-05-31
                          Costs
Acqiris sampler 2Gs/s AC240                                   20’000 Euro
Option FFT (Bitfile)                                           4’000 Euro
PCI-interface IC414                                            1’400 Euro
Blanking panel XB200                                             100 Euro
3-slot crate CC103                                             2’500 Euro
Driver (Win/Linux) free of charge                                  0 Euro
Standard-PC with one free PCI-slot                             2’000 Euro

FFT – spectrometer                                            30’000 Euro


Some statistics to remember….:

1,8 Euro per FFT-channel or
33KHz bandwidth for every single Euro

               Actual prices to be negotiated with Acqiris!
Additional information
           Project management & tests: ETH Zurich:
                      - Prof. A. O. Benz
                        - Chr. Monstein
                      - Hansueli Meyer

         Algorithms: FHS (Fachhochschule Solothurn):
                       - Bruno Stuber

   VHDL design: ZMA (Zentrum für Mikroelektronik Aargau):
                    - Prof. K. Schenk
                       - D. Zardet

              Industry: Acqiris company Geneva:
                  - Dr. V. Hungerbühler et. al.



 Additional information:
 http://www.astro.phys.ethz.ch/instrument/argos/argos_nf.html
 http://www.acqiris.com
                           Block diagram KOSMA
                                                     AOS LRS
                     Positioning                   1000MHz/1450
                        unit

  Receivers                                          AOS MRS          KOSMA                         KOSMA
                                                    300MHz/1800        DSP                          control
200…900GHz

                                                     AOS HRS
                                                    59MHz/2048
Local oscillator            IF
     unit                  unit

                                                     ETH-FFT        Digital
                              IF = 350MHz±150MHz    1GHz/16384       I/O         -Data ready
                                                                                 -Wobbler control



                                                     PC Win XP
                                                   Argos,FTP, VNC
                   Intranet
                                                                                                         To
   Laptop LINUX          PC Win XP                                                                       Internet
        IDL              Office, VNC
                                                                          Printers
KOSMA measurement methods
         Measurement                  Mirrors involved          Local
            Mode                                               oscillator
                            Secondary               Tertiary

Continuous recording          fixed                  fixed      const

Beam switched (wobbler)        √                     fixed      const


Beam switched (telescope)     fixed                  fixed      const

Dual beam switched             √                     fixed      const
(reference = sky)
Dual beam switched             √                         √      const
(reference = hot load)
Frequency switching           fixed                  fixed         √
KOSMA 3m-parabola
KOSMA Control room




    Ilona Miller
KOSMA clock generation
ARGOS, IF-units & AOS
Allan time hot noise source



                     Data: 3.6 GByte in total,
                     (extraction of Saturday,
                     02.04.2005.
                     Used for analysis
                     08:15 - 21:00)
                     FPGA: 52.8°C ±0.2K
                     Place : Library SEC
           [sec]     Range: 50mVpp
Channel test 10MHz comb
Receiver temperature 230GHz




Birdies < 200MHz and > 500MHz are out of KOSMA-IF (red shaded area)!
DR21K 12CO 2→1




 Some single spectra 15sec each
 ↑ = source - reference
 ↓ = reference - source
      DR21K 12CO 2→1




Ti = 90sec   230.537994GHz   Ti = 179sec
BW = 61KHz                   BW = 47KHz
       DR21K 12CO 3→2




Channel width 60KHz   Channel width 560KHz
Ti = 200sec           Ti = 400sec
    ORION A            12CO   2→1




Channel width 240KHz     Channel width 560KHz
Ti = 10sec               Ti = 20sec
  AFGL 2591            12CO   3→2




Channel width 240KHz     Channel width 560KHz
Ti = 160sec              Ti = 320sec
 IRC 10216 12CO 2→1 Observation 3h




SNR with BW=240KHz, Ti=3420sec   Ta with BW=560KHz, Ti=5700sec
Sun in absorption   12CO   3→2
12CO   2→1 Line
Dual beam switched mode




        Tamax ≈ 1Kelvin
Frequency switching 12CO 2→1




       Fo = 230’537.994MHz ± 10.5MHz
Ozone in the atmosphere




                AOS saturated
ARGOS-GUI Windows XP
ARGOS on-line graphics



 Sky noise                  Zero noise




              The ADC-range has to be adjusted such
              that peak amplitudes don’t strike maximum
              values but, the ADC should be set to
              maximum gain while observing a hot load.




 Comb noise
Base band overviews DC-1GHz
     Time- & frequency domain
       Gornergrat 3100m asl




10sec base band dc-1GHz   30sec IF (230GHz - RX)
Time- & frequency domain during
   VP Diavolezza 3000m asl




Radar pulse 1028...1030MHz       Echo of ionosphere sonder 16…30Mhz
using an L-band down converter   while doing Jupiter/Io observations.
                             Conclusions
                Parameter        FFT using AC240                   AOS

Dynamic range                         ~ 48dB                     ~ 24dB

Number of channels                2^14 = 16’384               1’000 … 2’048

Observation bandwidth                  1GHz                  50MHz …. 1GHz

Channel bandwidth                     61KHz                  50KHz … 1MHz

Allan time                      >2’000sec (±0.2°C)             50 …200sec

Output digits                          36 bit                     12 bit

Integration on board           16.384µsec … ~ 1day           10ms … 100ms

Frequency stability                 Very good          Regular calibration necessary

Lifetime                             Very high                     High

Shock resistance                Very high, no optics               Low

Electrical power & cooling           100 Watt                  comparable

Weight                                 7.8kg                   comparable

Price                              ~ 28’000Euro                >30’000Euro

				
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posted:8/25/2012
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