Layout Generation

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					            Analog Design Flow
        Analog/Mixed-Signal System Level Abstraction

Input    Stage 1   S/H      Stage 2   S/H    …    Stage N




Circuit Level Description
                                        Chip Implementation
   And Optimization
 Automated Analog Design Flow
Circuit Requirements
  (Topology, Gain,                     Circuit
   BW, DR, etc.)                     Optimization
                 Circuit Schematic                  Sized Circuit    Optimized
                  With Parasitics                    Schematic        Circuit
                                      Parasitics                     Schematic
                                      Estimation



                                     Simulation
                                        And
                                     Verification
   Sized and Verified
       Schematic
                                      Layout                        Circuit
                                     Generation                     Layout
             Parasitics Estimation
Sources of Parasitics:
   • Device Capacitances
      Simulators may under/over estimate these capacitances due to a lack
      of knowledge about layout
   • Interconnect Capacitances
      Very difficult to predict these capacitances if automatic routing is to be
      used. However, for baseband applications, these parasitics should be
      negligible compared to device parasitics
   • Interconnect and Via Resistances
      Also very difficult to predict but should be negligible compared to
      device parasitics

Solution:
   • If layout is automated, the device parasitics can be
     predicted and the circuit can be fully optimized without
     having to layout, extract, simulate, etc.
                  Analog Layout
Transition from Schematic to Layout:
   • Manual process
      - Much of current analog layout is done manually
         by drawing rectangles to represent layers.
   • Signals are parasitic sensitive
      - Signals are sensitive to parasitics, necessitating
         device matching and path symmetry.
      - Sensitivity also necessitates extraction and
         simulation to verify layout
   • Usually requires redesign for each new process
      - Analog schematics typically change with process
          therefore layout changes as well.
     Time consuming process               Automate!
                        Layout Options
                         Cadence Relative
    Cadence P-Cell                                Cadence
                          Object Design
      Generators                                   Router
                          For Placement
                                                                  Cadence Layout

    Neocell Module                Neocell Place
      Generators                   And Route


•     Parameterized-Cells (P-Cells)
      +    Direct control over generators and placement
      -    Several tools are used in the flow
•     Neolinear’s Neocell
      +    Single tool solution
      +    Neocell is now part of the Cadence tool set
      +    Neocell could potentially be used for placement and routing of P-Cells
      -    Some user interaction is still required
                   Cadence P-Cells
Parameterized cells allow devices to be changed based on
   width, length, resistance, etc.
   Active Component Arrays

       W=2.5µm
                       NMOS
       L=0.25µm
                       P-Cell
       M=5




   Passive Component Arrays

                      Capacitor
         C=900fF       P-Cell
                 Layout with Neocell
Neocell allows user to apply constraints to schematics
    •   Constraints define proximity, matching, location, orientation, grouping,
        and merging of devices, wires and pins.
    •   In order for a layout to be generated without user guidance, the
        constraints for a given topology must be set.




                                        Neocell places and routes using constraints
 Constraints applied to Schematic
               Neocell Example




Devices generated automatically, placement done manually,
       routing done automatically… time ~ 1 hour.
    Neocell Example

                   M4,
          M3       M11,   M10
                   M12
M17 M16                         75μm
                   M7
                   M9
M0,M2              M6,
                   M8,
 M14
                   M13

           104μm

				
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posted:8/25/2012
language:Latin
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