Analog Design Flow
Analog/Mixed-Signal System Level Abstraction
Input Stage 1 S/H Stage 2 S/H … Stage N
Circuit Level Description
Automated Analog Design Flow
(Topology, Gain, Circuit
BW, DR, etc.) Optimization
Circuit Schematic Sized Circuit Optimized
With Parasitics Schematic Circuit
Sized and Verified
Sources of Parasitics:
• Device Capacitances
Simulators may under/over estimate these capacitances due to a lack
of knowledge about layout
• Interconnect Capacitances
Very difficult to predict these capacitances if automatic routing is to be
used. However, for baseband applications, these parasitics should be
negligible compared to device parasitics
• Interconnect and Via Resistances
Also very difficult to predict but should be negligible compared to
• If layout is automated, the device parasitics can be
predicted and the circuit can be fully optimized without
having to layout, extract, simulate, etc.
Transition from Schematic to Layout:
• Manual process
- Much of current analog layout is done manually
by drawing rectangles to represent layers.
• Signals are parasitic sensitive
- Signals are sensitive to parasitics, necessitating
device matching and path symmetry.
- Sensitivity also necessitates extraction and
simulation to verify layout
• Usually requires redesign for each new process
- Analog schematics typically change with process
therefore layout changes as well.
Time consuming process Automate!
Cadence P-Cell Cadence
Neocell Module Neocell Place
Generators And Route
• Parameterized-Cells (P-Cells)
+ Direct control over generators and placement
- Several tools are used in the flow
• Neolinear’s Neocell
+ Single tool solution
+ Neocell is now part of the Cadence tool set
+ Neocell could potentially be used for placement and routing of P-Cells
- Some user interaction is still required
Parameterized cells allow devices to be changed based on
width, length, resistance, etc.
Active Component Arrays
Passive Component Arrays
Layout with Neocell
Neocell allows user to apply constraints to schematics
• Constraints define proximity, matching, location, orientation, grouping,
and merging of devices, wires and pins.
• In order for a layout to be generated without user guidance, the
constraints for a given topology must be set.
Neocell places and routes using constraints
Constraints applied to Schematic
Devices generated automatically, placement done manually,
routing done automatically… time ~ 1 hour.
M3 M11, M10
M17 M16 75μm