Docstoc

2008Tables_CROSSCUT

Document Sample
2008Tables_CROSSCUT Powered By Docstoc
					  ORTC
  INDEX               2008 CROSS-CUT ITWG TABLES:
                      Environment, Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulation
 2007 ITRS
 Chapters
                      Link to file for System Drivers, Design, Test & Test Equipment, RF and AMS for Wireless, and Process
                      (PIDS)

                      Link to file for Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Pro
                      Interconnect, Factory Integration, and Assembly & Packaging
                      Link to the 2008 Update Overview
                      Link to the 2007 ITRS chapters

                      Environment, Safety, and Health
TEXT                 Table ESH1
             UPDATED Table ESH2a
             UPDATED Table ESH2b
                     Table ESH3
                     Table ESH4a
                     Table ESH4b
             UPDATED Table ESH5
                     Table ESH6

                      Yield Enhancement
TEXT                 Table YE1
TEXT                 Table YE2
             UPDATED Table YE3
             UPDATED Table YE4
             UPDATED Table YE5
             UPDATED Table YE6

             UPDATED Table YE7

             UPDATED Table YE8
             UPDATED Table YE9


                      Metrology
TEXT                 Table MET1
                     Table MET2
                     Table MET3
                     Table MET4a and b
                     Table MET4c and d
             UPDATED Table MET5a
                     Table MET5b
                     Table MET6

                      Modeling and Simulation
TEXT   UPDATED Table MS1
       UPDATED Table MS2a
       UPDATED Table MS2b
       UPDATED Table MS3



               TO ACCESS THESE TABLES LISTED BELOW, USE THE LINKS AT THE TOP OF THIS PAGE
               System Drivers
TEXT           Table SYSD1
       UPDATED Table SYSD2
               Table SYSD3
               Table SYSD4

               Design
TEXT           Table DESN1
TEXT   ADDED   Table DESN X
       UPDATED Table DESN2
TEXT   UPDATED Table DESN3
               Table DESN4
TEXT           Table DESN5
               Table DESN6
TEXT           Table DESN7
               Table DESN8
               Table DESN9
TEXT           Table DESN10
TEXT           Table DESN11
TEXT           Table DESN12

               Test and Test Equipment
TEXT           Table TST1
       UPDATED Table TST2
               Table TST3
               Table TST4
               Table TST5
       UPDATED Table TST6
       UPDATED Table TST7
       UPDATED Table TST8
               Table TST9
TEXT           Table TST10
               Table TST11
               Table TST12
TEXT           Table TST13
               Table TST14
               Table TST15
                 RF and AMS for Wireless
       UPDATED Table RFAMS1
       UPDATED Table RFAMS2
       UPDATED Table RFAMS3
       UPDATED Table RFAMS4
       UPDATED Table RFAMS5
                 Table RFAMS6
                 Table RFAMS7
                 Table RFAMS8

                 Process Integration, Devices, and Structures (PIDS)
TEXT             Table PIDS1
       UPDATED Table PIDS2
       UPDATED Table PIDS3a and b
       UPDATED Table PIDS3c and d
               Table PIDS4
       UPDATED Table PIDS5
TEXT           Table PIDS6
               Table PIDS7

                 Emerging Research Devices
TEXT             Please refer to the ERD summary in the 2008 Update Overview

                 Emerging Research Materials
TEXT             Please refer to the ERM summary in the 2008 Update Overview

                 Front End Processes
TEXT             Table FEP1
       UPDATED   Table FEP2
       UPDATED   Table FEP3
       UPDATED   Table FEP4a
       UPDATED   Table FEP4b
       UPDATED   Table FEP5
       UPDATED   Table FEP6
       UPDATED   Table FEP7
       UPDATED   Table FEP8
                 Table FEP9

                 Lithography
TEXT           Table LITH1
TEXT           Table LITH2
       UPDATED Table LITH3
       UPDATED Table LITH4AB
               Table LITH4C
       UPDATED Table LITH5AB
       UPDATED Table LITH5CD
       UPDATED Table LITH5EF
               Table LITH6

                 Interconnect
TEXT             Table INTC1
       UPDATED Table INTC2
       UPDATED Table INTC3
               Table INTC4
TEXT           Table INTC5
       UPDATED Table INTC6
               Table INTC7

                 Factory Integration
TEXT           Table FAC1
TEXT           Table FAC2
               Table FAC3
       UPDATED Table FAC4
               Table FAC5
       UPDATED Table FAC6
               Table FAC7
TEXT           Table FAC8
TEXT           Table FAC9

                 Assembly and Packaging
TEXT             Table AP1
                 Table AP2
       UPDATED   Table AP3
       UPDATED   Table AP4
       ADD       Table AP4B
       UPDATED   Table AP5A
       UPDATED   Table AP5B
       UPDATED   Table AP5C
                 Table AP6
                 Table AP7
TEXT             Table AP8
       UPDATED   Table AP9
TEXT   UPDATED   Table AP10
       UPDATED   Table AP11
                 Table AP12a and b
TEXT             Table AP12c
TEXT             Table AP13
TEXT             Table AP14
TEXT   UPDATED   Table AP15
TEXT   UPDATED   Table AP16
TEXT             Table AP17
TEXT             Table AP18
TEXT   UPDATED   Table AP19
                 Table AP20
       UPDATED   Table AP21
 CUT ITWG TABLES:
 Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulation

System Drivers, Design, Test & Test Equipment, RF and AMS for Wireless, and Process Integration, Devices, & Structures


Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Processes (FEP), Lithography,
Factory Integration, and Assembly & Packaging
08 Update Overview
07 ITRS chapters

 Safety, and Health
             ESH Difficult Challenges
             ESH Intrinsic Requirements—Near-term Years
             ESH Intrinsic Requirements—Long-term Years
             Chemicals and Materials Management Technology Requirements
             Process and Equipment Management Technology Requirements—Near-term Years
             Process and Equipment Management Technology Requirements—Long-term Years
             Facilities Energy and Water Optimization Technology Requirements
             Sustainability and Product Stewardship Technology Requirements


               Definitions for the Different Interface Points
               Yield Enhancement Difficult Challenges
               Defect Budget Technology Requirement Assumptions
               Yield Model and Defect Budget MPU Technology Requirements
               Yield Model and Defect Budget DRAM/Flash Technology Requirements
               Defect Inspection on Patterned Wafer Technology Requirements

               Defect Inspection on Unpatterned Wafers: Macro, and Bevel Inspection Technology Requirements
               Defect Review and Automated Defect Classification Technology Requirements
               Technology Requirements for Wafer Environmental Contamination Control


               Metrology Difficult Challenges
               Metrology Technology Requirements
               Lithography Metrology (Wafer) Technology Requirements
               Lithography Metrology (Mask) Technology Requirements: Optical
               Lithography Metrology (Mask) Technology Requirements: EUV
               Front End Processes Metrology Technology Requirements—Near-term Years
               Front End Processes Metrology Technology Requirements—Long-term Years
               Interconnect Metrology Technology Requirements—Near and Long-term Years

d Simulation
         Modeling and Simulation Difficult Challenges
         Modeling and Simulation Technology Requirements: Capabilities—Near-term Years
         Modeling and Simulation Technology Requirements: Capabilities—Long-term Years
         Modeling and Simulation Technology Requirements: Accuracy—Near-term Years


THESE TABLES LISTED BELOW, USE THE LINKS AT THE TOP OF THIS PAGE

         Major Product Market Segments and Impact on System Drivers
         SOC Consumer Driver Design Productivity Trends
         Projected Mixed-Signal Figures of Merit for Four Circuit Types
         Embedded Memory Requirements


         Overall Design Technology Challenges
         Description of Improvement
         System-Level Design Requirements
         Correspondence Between System-Level Design Requirements and Solutions
         Logical/Circuit/Physical Design Technology Requirements
         Correspondence Between Logical/Circuit/Physical Requirements and Solutions
         Design Verification Requirements
         Correspondence Between Design Verification Requirements and Solutions
         Design for Test Technology Requirements
         Design for Manufacturability Technology Requirements
         Correspondence Between Design for Manufacturability Requirements and Solutions
         Near-term Breakthroughs in Design Technology for AMS
         Design Technology Improvements and Impact on Designer Productivity


         Summary of Key Test Drivers, Challenges, and Opportunities
         Multi-site Test for Product Segments
         System on Chip Test Requirements
         Logic Test Requirements
         Vector Multipliers
         Memory Test Requirements
         Mixed-signal Test Requirements
         RF Test Requirements
         Burn-in Requirements
         Test Handler and Prober Difficult Challenges
         Prober Requirements
         Handler Requirements
         Probing Difficult Challenges
         Wafer Probe Technology Requirements
         Test Socket Technology Requirements
for Wireless
               RF and Analog Mixed-Signal CMOS Technology Requirements
               RF and Analog Mixed-Signal Bipolar Technology Requirements
               On-Chip Passives Technology Requirements
               Embedded Passives Technology Requirements
               Power Amplifier Technology Requirements
               Base Station Devices Technology Requirements
               Millimeter Wave 10 GHz–100 GHz Technology Requirements
               RF and Analog Mixed-Signal RFMEMS

ration, Devices, and Structures (PIDS)
             Process Integration Difficult Challenges
             High-performance Logic Technology Requirements
             Low Standby Power Technology Requirements
             Low Operating Power Technology Requirements
             DRAM Technology Requirements
             Non-volatile Memory Technology Requirements
             Reliability Difficult Challenges
             Reliability Technology Requirements

search Devices
o the ERD summary in the 2008 Update Overview

search Materials
o the ERM summary in the 2008 Update Overview


               Front End Processes Difficult Challenges
               Starting Materials Technology Requirements—Near and Long-term Years
               Front End Surface Preparation Technology Requirements—Near and Long-term Years
               Thermal, Thin Film, Doping and Etching Technology Requirements—Near-term Years
               Thermal, Thin Film, Doping and Etching Technology Requirements—Long-term Years
               DRAM Stacked Capacitor Technology Requirements—Near and Long-term Years
               DRAM Trench Capacitor Technology Requirements—Near and Long-term Years
               FLASH Non-volatile Memory Technology Requirements
               Phase Change Memory (PCM) Technology Requirements—Near and Long-term Years
               FeRAM Technology Requirements—Near and Long-term Years


               Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection Lithography
               Lithography Difficult Challenges
               Lithography Technology Requirements—Near and Long-term Years
               Resist Requirements—Near and Long-term Years
Resist Sensitivities
Optical Mask Requirements—Near and Long-term Years
EUVL Mask Requirements—Near and Long-term Years
Imprint Template Requirements—Near and Long-term Years
Maskless Technology Requirements—Near and Long-term Years


Interconnect Difficult Challenges
 MPU Interconnect Technology Requirements—Near and Long-term Years
DRAM Interconnect Technology Requirements—Near and Long-term Years
Interconnect Surface Preparation Technology Requirements—Near and Long-term Years
Options for Interconnects Beyond the Metal/Dielectric System
High Density Through Silicon via Draft Specification
M inimum Density of Metallic SWCNTs Needed to Exceed Minimum Cu Wire Conductivity


 Factory Integration Difficult Challenges—Near and Long-term Years
 Key Focus Areas and Issues for FI Functional Areas Beyond 2007
 Factory Operations Technology Requirements—Near and Long-term Years
 Production Equipment Technology Requirements—Near and Long-term Years
 Material Handling Systems Technology Requirements—Near and Long-term Years
 Factory Information and Control Systems Technology Requirements—Near and Long-term Years
 Facilities Technology Requirements—Near and Long-term Years
 Crosscut Issues Relating to Factory Integration
 List of Next Wafer Size Challenges


Assembly and Packaging Difficult Challenges
  Single-chip Packages Technology Requirements—Near and Long-term Years
Chip-to-package Substrate Technology Requirements—Near and Long-term Years
Substrate to Board Pitch—Near and Long-term Years
Warpage at Peak Temperature
Package Substrates—Near and Long-term Years
Polymer Package Substrate Design Parameters—Near and Long-term Years
Cost Performance Glass-ceramic Substrates (high end FCBGA)
Wafer Level Packaging—Near and Long-term Years
Key Technical Parameters for Stacked Architectures Using TSV
Comparison of SoC and SiP Architecture
Package Level System Integration
Processes for SiP
System in Package Requirements—Near and Long-term Years
Thinned Silicon Wafer Thickness 200 mm/300 mm—Near and Long-term Years
Challenges and Potential Solutions in Thinning Si Wafers
SiP Failure Modes
Some Common Optoelectronic Packages and Their Applications
Optical Communications and Interconnect
Optoelectronic Packaging Challenges and Potential Solutions
MEMS Packaging Methods
MEMS Packaging Examples
Materials Challenges
Package Substrate Physical Properties
 Automotive Operating Environment Specifications
http://www.itrs.net/Links/2008ITRS/Update/2008Tables_FOCUS_A.xls


http://www.itrs.net/Links/2008ITRS/Update/2008Tables_FOCUS_B.xls

http://www.itrs.net/Links/2008ITRS/Update/2008_Update.pdf
http://www.itrs.net/Links/2007ITRS/Home2007.htm
   2008
  INDEX


 2007 ITRS   Overall Roadmap Technology Characteristics [ORTC]
 Chapters

UPDATED      Trends Graphic
UPDATED      Table 1a&b
UPDATED      Table 1c&d
UPDATED      Table 1e&f
UPDATED      Table 1g&h
UPDATED      Table 1i&j
UPDATED      Table 2a&b
UPDATED      Table 3a&b
UPDATED      Table 4a&b
UPDATED      Table 4c&d
UPDATED      Table 5a&b
UPDATED      Table 6a&b
UPDATED      Table 7a&b
Roadmap Technology Characteristics [ORTC]


           Product Generations and Chip Size Model Technology Trend Targets
           DRAM and Flash Production Product Generations and Chip Size Model
           DRAM Introduction Product Generations and Chip Size Model
           MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model
           High-Performance MPU and ASIC Product Generations and Chip Size Model
           Lithographic-Field and Wafer Size Trends
           Performance of Packaged Chips: Number of Pads and Pins
           Performance and Package Chips: Pads, Cost
           Performance and Package Chips: Frequency On-chip Wiring Levels
           Electrical Defects [**]
           Power Supply and Power Dissipation
           Cost
2008 Update Trend Graphic, including ITRS 7/15 meetings Final Litho Pr
15 meetings Final Litho Printed Gate Length Proposal
      Table 1a&bProduct Generations and Chip Size Model Technology Trend Targets

      Year of Production                                                           2007            2008           2009            2010           2011            2012           2013


      Flash ½ Pitch (nm) (un-contacted Poly)(f)                                     54              45              40             36              32             28              25
WAS   DRAM ½ Pitch (nm) (contacted)                                                 65              57             50              45             40              36             32
 IS   DRAM ½ Pitch (nm) (contacted)                                                 68              59             52              45              40             36              32
 IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                            68              59              52             45              40             36              32
WAS   MPU Printed Gate Length (nm)                                                  42              38              34             30              27             24              21
 IS   MPU Printed Gate Length (GLpr) (nm) ††                                        54              47              41             35              31             28              25
WAS   MPU Physical Gate Length (GLph) (nm)                                          25              23              20             18              16             14              13
 IS   MPU Physical Gate Length (GLph) (nm)                                          32              29              27             24              22             20              18
WAS   ASIC/Low Operating Power Printed Gate Length (nm) ††                          54              48              42             38              34             30              27
 IS   ASIC/Low Operating Power Printed Gate Length (nm) ††                          64              54              47             41              35             31              25
WAS   ASIC/Low Operating Power Physical Gate Length (nm)                            32              28              25             23              20             18              16
 IS   ASIC/Low Operating Power Physical Gate Length (nm)                            38              32              29             27              24             22              18
ADD   ASIC/Low Standby Power Physical Gate Length (nm)                              45              38              32             29              27             22              18
ADD   MPU Etch Ratio GLpr/GLph (nm)                                              1.6818           1.6039         1.5296          1.4588         1.4237          1.3895         1.3561


      Notes for Tables 1a and 1b (revised from 2007 ITRS document):
      †† MPU and ASIC gate-length (in resist) node targets refer to the most aggressive requirements, as printed in photoresist (which was by definition also “as etched in polysilicon,” in the 1999 ITRS).


      However, during the 2000/2001 ITRS development, trends were identified, in which the MPU and ASIC “physical” gate lengths may be reduced from the “as-printed” dimension. These physical gate-length
      targets are driven by the need for maximum speed performance in logic microprocessor (MPU) products, and are included in the Front End Processes (FEP), Process Integration, Devices, and Structures
      (PIDS), and Design chapter tables as needs that drive device design and process technology requirements.

      Refer to the Glossary for definitions of Introduction, Production, InTERgeneration, and InTRAgeneration terms.


      MPU Physical Gate Length targets are significantly revised in the 2008 Update from previous ITRS roadmap document to align with survey and data updates from the PIDS and FEP TWGs. The MPU physical
      gate length targets are now set based on a modeled trend for a 3.8-year cycle (0.5x per7.6 years), which is a best-fit to the survey update data. The MPU printed gate length has been adjusted to reflect the
      agreement between the FEP and Lithography TWGs to use a variable ratio factor, to model the relationship between the final physical gate length and the printed gate length, after additional processing is
      applied to printed gate length isolated feature. The new variable ratio targets can be seen above in the new added line item. The ASIC/Low Operating Power gate length targets were likewise adapted to the
      new PIDS survey data; and a new Standby Physical Gate Length was added. MPU/ASIC M1 stagger-contact targets were previously accelerated to 90 nm/2005 to reflect actual industry performance per the
      Interconnect ITWG recommendation, and a new consensus model technology cycle timing of 2.5 years (0.5× per 5 years reduction rate) has been applied through 2010, when the trend targets become equal to
      the
      DRAM stagger-contact M1 through 2020. The DRAM M1 stagger-contact half-pitch data has been revised to match the PIDS survey data (equal to MPU M1 2.5-year cycle through
      2010, then DRAM and MPU M1 are equal on a 3-year cycle.

      Numbers in the header are rounded from the actual trend numbers used for calculation of models in ITRS ORTC and ITWG tables (see discussion in the online 2007 ITRS Executive Summary on rounding
      practices).
      For the 2008 Update, beyond 2016, the numbers are now rounded to one decimal point.
                             2014           2015


                              23             20
                              28             25
                              28             25
                              28             25
                              19             17
                              22             20
                              11             10
                              17             15
                              24             21
                              22             20
                              14             13
                              17             15
                              17             15
                            1.3235         1.2917



ched in polysilicon,” in the 1999 ITRS).


 “as-printed” dimension. These physical gate-length
(FEP), Process Integration, Devices, and Structures




 es from the PIDS and FEP TWGs. The MPU physical
  printed gate length has been adjusted to reflect the
he printed gate length, after additional processing is
ower gate length targets were likewise adapted to the
 /2005 to reflect actual industry performance per the
hrough 2010, when the trend targets become equal to

 2.5-year cycle through



 online 2007 ITRS Executive Summary on rounding
2016     2017     2018     2019     2020     2021     2022


 17.9     15.9     14.2     12.6     11.3     10.0     8.9
 23       20       18       16       14       13       11
 22.5     20.0     17.9     15.9     14.2     12.6     11.3
 22.5     20.0     17.9     15.9     14.2     12.6     11.3
 15       13       12       11       9.5      8.4      7.5
 17.7     15.7     14.0     12.5     11.1     9.9      8.8
 8.9      8.0      7.1      6.3      5.6      5.0      4.5
 14.0     12.8     11.7     10.7     9.7      8.9      8.1
 19       17       15       13       12       11       9.5
 17.7     15.7     14.0     12.5     11.1     9.9      8.8
 11       10       8.9      8.0      7.1      6.3      5.6
 14.0     12.8     11.7     10.7     9.7      8.9      8.1
 14.0     12.8     11.7     10.7     9.7      8.9      8.1
1.2607   1.2304   1.2008   1.1720   1.1438   1.1163   1.0895
     Table 1c&d DRAM and Flash Production Product Generations and Chip Size Model

     Year of Production                                                   2007            2008            2009              2010        2011            2012            2013            2014


IS   DRAM ½ Pitch (nm) (contacted)                                         68              59               52               45          40              36              32              28
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                    68              59               52               45          40              36              32              28
IS   MPU Physical Gate Length (nm)                                         32               29              27               24          22              20              18              17
     DRAM Product Table
     Cell area factor [a]                                                   6               6                6                6           6               6               6               6
                                  2
IS   Cell area [Ca = af2] (um )                                           0.028           0.021           0.016             0.012      0.0096          0.0077          0.0061          0.0048
     Cell array area at production (% of chip size) §                    56.08%          56.08%          56.08%             56.08%     56.08%          56.08%          56.08%         56.08%
     Generation at production §                                            2G               2G              2G                4G         4G              4G              8G              8G
     Functions per chip (Gbits)                                           2.15             2.15            2.15              4.29       4.29            4.29            8.59            8.59
                                      2
IS   Chip size at production (mm )§                                        107              81              61               93          74              59              93              74
IS   Gbits/cm2 at production §                                            2.01             2.65            3.50              4.62       5.82            7.33            9.23           11.63
     Flash Product Table
     Flash ½ Pitch (nm) (un-contacted Poly)(f)                            53.5             45.0            40.1              35.7        31.8            28.3           25.3            22.5
     Cell area factor [a]                                                   4                4               4                4           4               4               4               4
                           2      2
     Cell area [Ca = af ] (um )                                          0.0115          0.0081           0.0064            0.0051     0.0041          0.0032          0.0026          0.0020
     Cell array area at production (% of chip size) §                    68.35%          68.35%          68.35%             68.35%     68.35%          68.35%          68.35%          68.35%
     Generation at production § SLC                                        8G              8G               8G               16G         16G             16G            32G             32G
     Generation at production § MLC [2 bits/cell]                          16G             16G             16G               32G         32G             32G            64G             64G
     Generation at production § MLC [4 bits/cell]                          32G             32G             32G               64G         64G             64G            128G            128G
     Functions per chip (Gbits) SLC                                       8.59             8.59            8.59             17.18       17.18           17.18           34.36           34.36
     Functions per chip (Gbits) MLC [2 bits/cell]                         17.18           17.18           17.18             34.36       34.36           34.36           68.72           68.72
     Functions per chip (Gbits) MLC [4 bits/cell]                         34.36           34.36           34.36             68.72       68.72           68.72          137.44          137.44
                                      2
     Chip size at production (mm )§ SLC                                  143.96          101.80           80.80             128.26     101.80           80.80          128.26          101.80
     Chip size at production (mm2)§ MLC
     [2 bits/cell & 4 bits/cell]                                         143.96          101.80           80.80             128.26     101.80           80.80          128.26          101.80
                2
     Bits /cm       at production § SLC                                5.97E+09         8.44E+09        1.06E+10        1.34E+10      1.69E+10        2.13E+10       2.68E+10        3.38E+10
     Bits/cm2 at production § MLC [2 bits/cell]                        1.19E+10         1.69E+10        2.13E+10        2.68E+10      3.38E+10        4.25E+10       5.36E+10        6.75E+10
     Functions per chip (Gbits) MLC [4 bits/cell]                      2.39E+10         3.38E+10        4.25E+10        5.36E+10      6.75E+10        8.51E+10       1.07E+11        1.35E+11

     Notes for Tables 1c and 1d (revised from 2007 ITRS document):
     § Except for 2007-2009 column impact of the cell area, function density, and chip size (due to new survey 2.5-year cycle alignment), the DRAM Model is unchanged from the 2007 ITRS, and the cell
     area factor (design/process improvement) targets are as follows:

     1999–2006/8×: 2006 – - 2022/6×. Due to the elimination of the “7.5,” “7,”and the “5” DRAM Cell design improvement Factors [a] in the latest 2005 ITRS DRAM consensus model, the addition of
     “Moore’s Law” bits/chip slows from 2× every 2.5–3 years to 2× every three years.

     DRAM product generations were increased by 4  bits/chip every four years with interim 2  bits/chip generation. However, in the last model 2005 ITRS timeframe refer to Figures 8 and 9 for bit size
     and bits/chip trends:

     1. at the Introduction phase, after the 16 Gbit generation, the introduction rate is 4  /six years (2  /three years); and


     2. at the Production phase, after the 4 Gbit generation, the introduction rate is 4  /six years (2  /three years).


     As a result of the latest DRAM consensus model changes for the 2007 ITRS, the InTER-generation chip size growth rate model target for Production-phase DRAM product are delayed an additional
                                                        2
     year and now remains “flat” at less than 93 mm , about one third smaller than the MPU model. However, with the pull-in of the 6f 2 “cell area factor” , the flat-chip-size model target still requires
     the bits/chip “Moore’s Law” model for DRAM products to increase the time for doubling bits per chip to an average of 2  per 3 years (see ORTC Table 1c, 1d).



     In addition to the revisions noted above, the cell array efficiency (CAE – the Array % of total chip area) was change to 56.1% after 2006. Only the storage cell array area benefits from the 6× “cell
     area factor” improvement, not the periphery, however, the CAE pull-in enables the production-phase product chip size to meet the target flat-chip-size model. It can be observed in the Table 1c and d
     model data that the InTRA-generation chip size shrink model is still 0.5  every technology cycle (to 0.71× reduction) in-between cell area factor reductions.



     Refer to the Glossary for definitions of Introduction, Production, InTERgeneration, and InTRAgeneration terms.


     The Flash product model was revised in the 2007 roadmap to extend the 2-year-cycle half-pitch to 2008, also targets an affordable (<145 mm 2 ) chip size and includes a doubling of functions (bits)
     per chip every technology cycle (three years after 2008) on an Inter-generation. Flash cells have reached a limit of the 4-design factor, so the reduction of the Flash single-level cell (SLC) size is
     paced by the uncontacted polysilicon (three-year cycle). However, the Flash technology has the ability to store and electrically access two bits in the same cell area, creating a multi-level-cell (MLC)
     “virtual” per-bit size that is one-half the size of an SLC product cell size; and the latest revision of the Flash model also includes the introduction of 4 bits/cell beginning 2010 (refer to Figures 9 and
     10).
                             2015


                              25
                              25
                              15


                               6
                            0.0038
                           56.08%
                              8G
                             8.59
                              59
                            14.65


                             20.0
                               4
                            0.0016
                           68.35%
                             32G
                             64G
                            128G
                            34.36
                            68.72
                            137.44
                            80.80

                            80.80
                          4.25E+10
                          8.51E+10
                          1.70E+11



ged from the 2007 ITRS, and the cell


AM consensus model, the addition of


e refer to Figures 8 and 9 for bit size




M product are delayed an additional
t-chip-size model target still requires




array area benefits from the 6× “cell
an be observed in the Table 1c and d




ncludes a doubling of functions (bits)
  Flash single-level cell (SLC) size is
 ea, creating a multi-level-cell (MLC)
 ginning 2010 (refer to Figures 9 and
 2016       2017       2018       2019       2020       2021       2022


  22.5       20.0       17.9       15.9       14.2       12.6       11.3
  22.5       20.0       17.9       15.9       14.2       12.6       11.3
  14.0       12.8       11.7       10.7       9.7        8.9        8.1


   6          6          6          6          6          6          6
 0.0030     0.0024     0.0019     0.0015     0.0012    0.00096    0.00076
56.08%     56.08%     56.08%     56.08%     56.08%     56.08%     56.08%
  16G        16G        16G        32G        32G        32G        64G
 17.18      17.18      17.18      34.36      34.36      34.36      68.72
  93         74         59         93         74         59         93
 18.46      23.26      29.31      36.93      46.52      58.61      73.85


  17.9       15.9       14.2       12.6       11.3       10.0       8.9
   4          4          4          4          4          4          4
 0.0013     0.0010    0.00080    0.00064    0.00051    0.00040    0.00032
68.35%     68.35%     68.35%     68.35%     68.35%     68.35%     68.35%
  64G        64G        64G       128G       128G       128G       256G
 128G       128G       128G       256G       256G       256G       512G
 256G       256G       256G       512G       512G       512G       1024G
 68.72      68.72      68.72      137.44     137.44     137.44     274.88
 137.44     137.44     137.44     274.88     274.88     274.88     549.76
 274.88     274.88     274.88     549.76     549.76     549.76    1099.51
 128.26     101.80     80.80      128.26     101.80     80.80      128.26

 128.26     101.80     80.80      128.26     101.80     80.80      128.26
5.36E+10   6.75E+10   8.51E+10   1.07E+11   1.35E+11   1.70E+11   2.14E+11
1.07E+11   1.35E+11   1.70E+11   2.14E+11   2.70E+11   3.40E+11   4.29E+11
2.14E+11   2.70E+11   3.40E+11   4.29E+11   5.40E+11   6.80E+11   8.57E+11
     Table 1e&f DRAM Introduction Product Generations and Chip Size Model

     Year of Production                                                           2007            2008            2009              2010     2011        2012            2013           2014


IS   DRAM ½ Pitch (nm) (contacted)                                                 68              59              52                45       40           36             32             28
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                            68              59              52                45       40           36             32             28
IS   MPU Physical Gate Length (nm)                                                 32              29               27               24       22           20             18             17
     Cell area factor [a]                                                           6               6               6                6        6             6              6              6
                           2       2
IS   Cell area [Ca = af ] (um )                                                  0.028           0.021            0.016            0.012    0.0096      0.0077          0.0061         0.0048
     Cell array area at introduction (% of chip size) §                         73.52%          73.76%           73.97%            74.16%   74.30%      74.47%         74.61%          74.70%
     Generation at introduction §                                                 16G             16G              16G              32G      32G          32G            64G             64G
     Functions per chip (Gbits)                                                  17.18           17.18            34.36            34.36    34.36        68.72          68.72           68.72
                                        2
IS   Chip size at introduction (mm ) §                                            652              493             745              563      446          706            560             444
                2
IS   Gbits/cm       at introduction §                                             2.63            3.49             4.61             6.10     7.70         9.73           12.28          15.49


     Notes for Tables 1e and 1f (revised from 2007 ITRS document):
     § Except for 2007-2009 column impact of the cell area, function density, and chip size (due to new survey 2.5-year cycle alignment), the DRAM Model is unchanged from the 2007 ITRS, and
     the cell area factor (design/process improvement) targets are as follows:

     1999–2006/8×: 2006 – - 2022/6×. Due to the elimination of the “7.5,” “7,”and the “5” DRAM Cell design improvement Factors [a] in the latest 2005 ITRS DRAM consensus model, the
     addition of “Moore’s Law” bits/chip slows from 2× every 2.5–3 years to 2× every three years.

     DRAM product generations were increased by 4  bits/chip every four years with interim 2  bits/chip generation. However, in the last model 2005 ITRS timeframe refer to Figures 8 and 9
     for bit size and bits/chip trends:

     1. at the Introduction phase, after the 16 Gbit generation, the introduction rate is 4  /six years (2  /three years); and


     2. at the Production phase, after the 4 Gbit generation, the introduction rate is 4  /six years (2  /three years).


     As a result of the latest DRAM consensus model changes for the 2007 ITRS, the InTER-generation chip size growth rate model target for Production-phase DRAM product are delayed an
                                                                    2
     additional year and now remains “flat” at less than 93 mm , about one third smaller than the MPU model. However, with the pull-in of the 6f 2 “cell area factor” , the flat-chip-size model
     target still requires the bits/chip “Moore’s Law” model for DRAM products to increase the time for doubling bits per chip to an average of 2  per 3 years (see ORTC Table 1c, 1d).



     In addition to the revisions noted above, the cell array efficiency (CAE – the Array % of total chip area) was change to 56.1% after 2006. Only the storage cell array area benefits from the
     6× “cell area factor” improvement, not the periphery, however, the CAE pull-in enables the production-phase product chip size to meet the target flat-chip-size model. It can be observed in
     the Table 1c and d model data that the InTRA-generation chip size shrink model is still 0.5  every technology cycle (to 0.71× reduction) in-between cell area factor reductions.




     Refer to the Glossary for definitions of Introduction, Production, InTERgeneration, and InTRAgeneration terms.
 2015


  25
  25
  15
  6
0.0038
74.83%
 64G
68.72
 351

19.55
 2016     2017     2018     2019     2020     2021      2022


 22.5     20.0     17.9     15.9     14.2     12.6      11.3
 22.5     20.0     17.9     15.9     14.2     12.6      11.3
 14.0     12.8     11.7     10.7     9.7       8.9       8.1
  6        6        6        6        6        6         6
0.0030   0.0024   0.0019   0.0015   0.0012   0.00096   0.00076
74.93%   75.00%   75.09%   75.18%   75.27%   75.36%    75.45%
 128G     128G     128G     256G     256G     256G      512G
137.44   137.44   137.44   274.88   274.88   274.88    549.76
 557      442      350      555      440      349       553

24.67    31.11    39.24    49.50    62.44     78.77     99.36
     Table 1g&h MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model

     Year of Production                                                    2007        2008           2009           2010            2011           2012           2013            2014


IS   DRAM ½ Pitch (nm) (contacted)                                         68           59             52             45              40             36              32             28
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                     68          59             52             45              40             36              32             28
IS   MPU Physical Gate Length (nm)                                          32          29             27              24             22             20              18             17
     SRAM Cell (6-transistor) Area factor ++                               97.5        100.7         104.1           107.8          106.7           105.7          104.8           104.1
     Logic Gate (4-transistor) Area factor ++                              279         292            306             320            320             320            320             320
     SRAM Cell (6-transistor) Area efficiency ++                           0.63        0.63           0.63           0.63            0.63           0.63            0.63           0.63
     Logic Gate (4-transistor) Area efficiency ++                          0.5          0.5            0.5            0.5             0.5            0.5             0.5            0.5
     SRAM Cell (6-transistor) Area (um2)++                                 0.45        0.35           0.28           0.22            0.17           0.13            0.11           0.084
     SRAM Cell (6-transistor) Area w/overhead (um2)++                      0.73        0.57           0.45           0.35            0.27           0.22            0.17           0.13
     Logic Gate (4-transistor) Area (um2) ++                               1.3          1.0           0.82           0.65            0.51           0.41            0.32           0.26

     Logic Gate (4-transistor) Area w/overhead (um2) ++                    2.6          2.1            1.6            1.3             1.0           0.82            0.65           0.51
                                                    2
     Transistor density SRAM (Mtransistors/cm )                            827         1,057         1,348           1,718          2,187           2,781          3,532           4,484
                                                2
     Transistor density logic (Mtransistors/cm )                           154         194            245             309            389             490            617             778
     Generation at introduction *                                          p10c        p10c           p13c           p13c            p13c           p16c           p16c            p16c
     Functions per chip at introduction (million transistors
     [Mtransistors])                                                       773         773            1546           1546            1546           3092            3092           3092
                                      2
     Chip size at introduction (mm ) ‡                                     280         222            353             280            222             353            280             222
                                                2
     Cost performance MPU (Mtransistors/cm              at introduction)
     (including on-chip SRAM) ‡                                            276         348            438             552            696             876            1104           1391
     Generation at production *                                            p07c        p07c           p07c           p10c            p10c           p10c           p13c            p13c
     Functions per chip at production (million transistors
     [Mtransistors])                                                       386         386            386             773            773             773            1546           1546
                                  2
     Chip size at production (mm ) §§                                      140         111             88             140            111             88             140             111
                                                2
     Cost performance MPU (Mtransistors/cm              at production,
     including on-chip SRAM) ‡                                             276         348            438             552            696             876            1104           1391

     Notes for Tables 1g and 1h (unchanged from 2007 ITRS document):
     ++ The MPU area factors are analogous to the “cell area factor” for DRAMs. The reduction of area factors has been achieved historically through a combination of many factors, for
     example—use of additional interconnect levels, self-alignment techniques, and more efficient circuit layout. However, recent data has indicated that the improvement (reduction) of the
     area factors is slowing, and is virtually flat for the logic gate area factor.

     * p is processor, numerals reflect year of production; c indicates cost-performance product. Examples—the cost-performance processor, p04c, was introduced in 2002, but not ramped
     into volume production until 2004; similarly, the p07c, is introduced in 2004, but is targeted for volume production in 2007.


     ‡ MPU Cost-performance Model—Cost-performance MPU includes Level 2 (L2) on-chip SRAM (512Kbyte/2000) plus Logic (20M transistors in 1 core in year 2000); and the
     combination of both SRAM and logic transistor functionality doubles every technology node cycle. The 2007 MPU model was revised by the Design TWG to introduce the doubling of
     logic cores every other technology cycle, but function size and density was kept unchanged by doubling the transistor/core targets. The Design TWG believed this approach to the MPU
     Model was more representative of current design trends.


     §§ MPU Chip Size Model—Both the cost-performance and high-performance MPUs InTER-generation production-level chip sizes are modeled to be below affordable targets, which
                                          2                                        2                                           2
     are flat through 2022 (280 mm /cost-performance at introduction; 140 mm /cost-performance at production; 310 mm /high-performance at production). The MPU flat chip-size
     affordability model is accomplished by doubling the on-chip functionality every technology cycle. Actual market chip sizes may exceed the affordability targets in order to continue the
     doubling of on-chip functionality on a shorter cycle, but their unit costs and market values must be increased. In the 2005 ITRS, the MPU model now includes introduction-level high-
     performance MPU targets that shrink to the “affordable” targets (the same way the DRAM model operates). The InTRA-generation chip size shrink model is 0.5  every two-year
     density-driven technology cycle through 2004, and then 0.5  every three-year density-driven technology cycle after 2004, in order to stay under the affordable flat-chip-size target.




     Refer to the Glossary for definitions.
2015


 25
 25
 15
103.4
320
0.63
 0.5
0.066
0.11
0.20

0.41
5,687
980
p19c

6184
353


1753
p13c

1546
 88


1753
                                                             Comment

2016    2017    2018     2019     2020     2021     2022


22.5    20.0     17.9     15.9     14.2     12.6     11.3
22.5    20.0     17.9     15.9     14.2     12.6     11.3
14.0    12.8     11.7     10.7     9.7      8.9      8.1
102.8   102.2   101.7    101.3    100.9    100.5    100.1
320     320      320      320      320      320      320
0.63    0.63     0.63     0.63     0.63     0.63     0.63
 0.5     0.5     0.5      0.5      0.5      0.5      0.5
0.052   0.041   0.032    0.026    0.020    0.016     0.01
0.083   0.066   0.052    0.041    0.032    0.026    0.020
0.16    0.13     0.10    0.081    0.064    0.051    0.040

0.32    0.26     0.20     0.16     0.13     0.10     0.08
7,208   9,130   11,558   14,625   18,497   23,394   29,588
1,235   1,555   1,960    2,469    3,111    3,920    4,938    Correction of 7/12 draft - data was incorrect - should have been left unchanged f
p19c    p19c    p22c     p22c     p22c     p25c     p25c

6184    6184    12368    12368    12368    24736    24736
280     222      353      280      222      353      280


2209    2783    3506     4417     5565     7012     8834
p16c    p16c    p16c     p19c     p19c     p19c     p22c

3092    3092    3092     6184     6184     6184     12368
140     111      88       140      111      88       140


2209    2783    3506     4417     5565     7012     8834
uld have been left unchanged from 2005 ITRS
     Table 1i&j High-Performance MPU and ASIC Product Generations and Chip Size Model

     Year of Production                                                           2007      2008           2009           2010           2011           2012           2013           2014

IS   DRAM ½ Pitch (nm) (contacted)                                                 68        59             52             45             40             36             32             28
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                            68        59             52             45             40             36             32             28
IS   MPU Physical Gate Length (nm)                                                 32        29             27             24             22             20             18              17
     Logic (Low-volume Microprocessor) High-performance ‡
     Generation at Introduction                                                   p10h      p10h           p13h           p13h           p13h           p16h           p16h           p16h
     Functions per chip at introduction (million transistors)                     2212      2212           4424           4424           4424           8848           8848           8848
                                      2
     Chip size at introduction (mm )                                               620       492            391            620            492            391            620            492
     Generation at production **                                                  p07h      p07h           p07h           p10h           p10h           p10h           p13h           p13h
     Functions per chip at production (million transistors)                       1106      1106           1106           2212           2212           2212           4424           4424
                                  2
     Chip size at production (mm ) §§                                             310        246            195            310            246            195            310            246
                                                    2
     High-performance MPU Mtransistors/cm               at introduction and
     production (including on-chip SRAM) ‡                                        357        449            566            714            899           1133           1427           1798
     ASIC
                                   2
     ASIC usable Mtransistors/cm          (auto layout)                           357        449            566            714            899           1133           1427           1798
                                                2
     ASIC max chip size at production (mm ) (maximum lithographic
     field size)                                                                  858       858            858             858            858            858            858            858
     ASIC maximum functions per chip at production (Mtransistors/chip)
     (fit in maximum lithographic field size)                                     3,061     3,857          4,859          6,122          7,713          9,718         12,244         15,427

     Notes for Tables 1i and 1j (unchanged from 2007 ITRS document):
     * p is processor, numerals reflect year of production; c indicates cost-performance product. Examples—the cost-performance processor, p04c, was introduced in 2002, but not ramped into
     volume production until 2004; similarly, the p07c, is introduced in 2004, but is targeted for volume production in 2007.

     ‡ MPU High-performance Model—High-performance MPU includes Level 2 (L2) on-chip SRAM (2048Kbyte in year 2000) plus Logic (25M transistors in 1 core in year 2000), and the
     combination of both SRAM and logic transistor functionality doubles every technology cycle. The 2007 MPU model was revised by the Design TWG to introduce the doubling of logic cores
     every other technology cycle, but function size and density was kept unchanged by doubling the transistor/core targets. The Design TWG believed this approach to the MPU Model was more
     representative of current design trends.

     §§ MPU Chip Size Model—Both the cost-performance and high-performance MPUs InTER-generation production-level chip sizes are modeled to be below affordable targets, which are flat
                            2                                                 2                                    2
     through 2022 (280 mm /cost-performance at introduction; 140 mm /cost-performance at production; 310 mm /high-performance at production). The MPU flat chip-size affordability model
     is accomplished by doubling the on-chip functionality every technology cycle. Actual market chip sizes may exceed the affordability targets in order to continue the doubling of on-chip
     functionality on a shorter cycle, but their unit costs and market values must be increased. In the 2005 ITRS, the MPU model now includes introduction-level high-performance MPU targets
     that shrink to the “affordable” targets (the same way the DRAM model operates). The InTRA-generation chip size shrink model is 0.5  every two-year density-driven technology cycle through
     2004, and then 0.5  every three-year density-driven technology cycle after 2004, in order to stay under the affordable flat-chip-size target.



     Refer to the Glossary for definitions.
2015

 25
 25
 15


p19h
17696
 391
p13h
4424
 195


2265


2265


 858

19,436
2016     2017     2018     2019     2020     2021      2022

 22.5     20.0     17.9     15.9     14.2     12.6     11.3
 22.5     20.0     17.9     15.9     14.2     12.6     11.3
 14.0     12.8     11.7     10.7     9.7      8.9       8.1


p19h     p19h     p22h     p22h     p22h     p25h      p25h
17696    17696    35391    35391    35391    70782    70782
 620      492      391      620      492      391       620
p16h     p16h     p16h     p19h     p19h     p19h      p22h
8848     8848     8848     17696    17696    17696    35391
 310      246      195      310      246      195      310


2854     3596     4531     5708     7192     9061     11416


2854     3596     4531     5708     7192     9061     11416


 858      858      858      858      858      858      1716

24,488   30,853   38,873   48,977   61,707   77,746   195,906
     Table 2a&b Lithographic-Field and Wafer Size Trends

     Year of Production                                       2007   2008   2009   2010   2011   2012   2013   2014

IS   DRAM ½ Pitch (nm) (contacted)                            68     59     52      45     40     36     32     28
     Flash ½ Pitch (nm) (un-contacted Poly)(f)                 54     45     40     36     32     28     25     22
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                        68     59     52     45     40     36     32     28
IS   MPU Physical Gate Length (nm)                             32     29     27     24     22     20     18     17
     Lithography Field Size
                                                 2
     Maximum Lithography Field Size—area (mm )                858    858    858    858    858    858    858    858
     Maximum Lithography Field Size—length (mm)                33     33     33     33     33     33     33     33
     Maximum Lithography Field Size—width (mm)                 26     26     26     26     26     26     26     26
     Maximum Substrate Diameter (mm)—High-volume Production
     (>20K parts wafer starts per month)
     Bulk or epitaxial or SOI wafer                           300    300    300    300    300    450    450    450
2015

 25
 20
 25
 15


858
 33
 26



450
2016   2017   2018   2019   2020   2021   2022

22.5   20.0   17.9   15.9   14.2   12.6   11.3
 18     16     14     13     11     10     9
22.5   20.0   17.9   15.9   14.2   12.6   11.3
14.0   12.8   11.7   10.7   9.7    8.9    8.1


858    858    858    858    858    858    858
 33     33     33     33     33     33     33
 26     26     26     26     26     26     26



450    450    450    450    450    450    450
     Table 3a&bPerformance of Packaged Chips: Number of Pads and Pins

     Year of Production                                       2007           2008          2009           2010           2011           2012           2013           2014

IS   DRAM ½ Pitch (nm) (contacted)                             68             59             52             45             40             36             32            28
     Flash ½ Pitch (nm) (un-contacted Poly)(f)                 54             45             40             36             32             28             25            22
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                        68             59             52             45             40             36             32            28
IS   MPU Physical Gate Length (nm)                             32             29             27             24             22             20             18             17
     Number of Chip I/Os (Number of Total Chip
     Pads)—Maximum
     Total pads—MPU unchanged                                3,072          3,072          3,072          3,072          3,072          3,072          3,072          3,072
     Signal I/O—MPU (% of total pads)                        33.3%          33.3%          33.3%          33.3%          33.3%          33.3%          33.3%          33.3%

     Power and ground pads—MPU (% of total pads)             66.7%          66.7%          66.7%          66.7%          66.7%          66.7%          66.7%          66.7%

     Total pads—ASIC High Performance unchanged              4,400          4,400          4,600          4,800          4,800          5,000          5,400          5,400
     Signal I/O pads—ASIC high-performance (% of total
     pads)                                                   50.0%          50.0%          50.0%          50.0%          50.0%          50.0%          50.0%          50.0%
     Power and ground pads—ASIC high-performance
     (% of total pads)                                       50.0%          50.0%          50.0%          50.0%          50.0%          50.0%          50.0%          50.0%

     Number of Total Package Pins—Maximum [1]

     Microprocessor/controller, cost-performance           600–2140       600–2400       660–2801       660–2783       720- 3061      720–3367       800–3704       800-4075
     Microprocessor/controller, high-performance              4000           4400          4620           4851           5094           5348           5616           5896
     ASIC (high-performance)                                  4000           4400          4620           4851           5094           5348           5616           5896

     Notes for Tables 3a and 3b:
     [1] Pin counts will be limited for some applications where fine pitch array interconnect is used by printed wiring board (PWB) technology and system cost. The highest pin
     count applications will as a result use larger pitches and larger package sizes. The reference to signal pin ratio will also vary greatly dependent on applications with an
  2015

   25
   20
   25
   15



 3,072
 33.3%

 66.7%

 5,600

 50.0%

 50.0%




880–4482
  6191
  6191
  2016      2017       2018        2019         2020         2021        2022

  22.5       20.0       17.9       15.9         14.2         12.6        11.3
   18        16         14          13           11           10          9
  22.5       20.0       17.9       15.9         14.2         12.6        11.3
  14.0       12.8       11.7       10.7          9.7          8.9         8.1



 3,072      3,072      3,072       3,072       3,072         3,072       3,072
 33.3%      33.3%      33.3%      33.3%        33.3%        33.3%       33.3%

 66.7%      66.7%      66.7%      66.7%        66.7%        66.7%       66.7%

 6,000      6,000      6,200       6,200       6,200         6,840       6,840

 50.0%      50.0%      50.0%      50.0%        50.0%        50.0%       50.0%

 50.0%      50.0%      50.0%      50.0%        50.0%        50.0%       50.0%




880–4930   960-5423   960–5966   1050-6562   1050 - 7218   1155-7940   1155-8337
  6501      6826       7167        7525         7902         8297        8712
  6501      6826       7167        7525         7902         8297        8712
         Table 4a&b Performance and Package Chips: Pads, Cost

         Year of Production                                          2007       2008       2009       2010      2011      2012      2013
  IS     DRAM ½ Pitch (nm) (contacted)                                68         59         52         45         40        36        32
         Flash ½ Pitch (nm) (un-contacted Poly)(f)                    54         45         40         36         32        28        25
  IS     MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                           68         59         52         45         40        36        32
  IS     MPU Physical Gate Length (nm)                                32         29         27         24         22        20        18
         Chip Pad Pitch (micron)
DELETE   Pad pitch—ball bond                                          30         30         25         25         25        20        20
  IS     Pad pitch— Wedge bond                                        25         25         20         20         20        20        20
         Pad Pitch— Area array flip-chip (cost-performance, high-
  IS     performance)                                                 130        130        130        130       120       110       110
  IS     Pad Pitch— 2-row staggered-pitch (micron)                    55         50         45         45         45        40        40
  IS     Pad Pitch— Three-tier-pitch pitch (micron)                   60         60         60         55         55        50        45
         Cost-Per-Pin
         Package cost (cents/pin) (Cost per Pin Minimum for
         Contract Assembly – Cost-performance) —
         minimum–maximum                                            .69-1.19   .66-1.13   .63-1.70   .60-1.20   .57-.97   .54-.92   .51-.87
         Package cost (cents/pin) (Low-cost, hand-held and
         memory) — minimum–maximum                                  .27-.50    .25-.48    .24-.46    .23-.44    .22-.42   .21-.40   .20-.38
 2014        2015
   28          25
   22          20
   28          25
   17          15


   20          20
   20          20

  100         100
   40          40
   45          45




.48 - .83   .46 - .79

.20-.36     .20 -.34
 2016        2017        2018        2019        2020       2021        2022
  22.5        20.0        17.9        15.9        14.2       12.6       11.3
   18          16          14          13          11         10         9
  22.5        20.0        17.9        15.9        14.2       12.6       11.3
  14.0        12.8        11.7        10.7        9.7        8.9         8.1


   20          20          20          20          20         20         20
   20          20          20          20          20         20         20

   95          95          90          90          85         85         80
   35          35          35          35          35         35         35
   45          45          45          45          45         45         45




.44 - .75   .42 - .71   .39 - .68   .37 - .64   .35 - .61   .33-.58   0.32-0.55

.20-.32     .20-.30     .20-.29     .20-.27     .20-.26     .19-.25    .19-.25
     Table 4c&d Performance and Package Chips: Frequency On-chip Wiring Levels

     Year of Production                                                    2007            2008            2009            2010           2011            2012            2013
IS   DRAM ½ Pitch (nm) (contacted)                                           68             59              52              45              40             36              32
     Flash ½ Pitch (nm) (un-contacted Poly)(f)                               54             45              40              36              32             28              25
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                      68             59              52              45              40             36              32
IS   MPU Physical Gate Length (nm)                                           32              29             27              24              22              20             18
     Chip Frequency (MHz)
     On-chip local clock [1]                                               4.700           5.063           5.454          5.875           6.329           6.817           7.344
     Maximum number wiring levels [3] [**]                                   11              12             12              12              12              12             13


     [**] [Note ** : The Interconnect TWG has deleted their "optional levels" from table 80a&b, therefore the ORTC "Maximum number wiring levels - maximum" line is deleted; also the "

     Notes for Tables 4c and 4d (ORTC 4c,d) unchanged from 2007 ITRS document, but see notes regarding PIDS TWG modeling update):
     [1] The on-chip frequency is based on the fundamental transistor delay (defined by the PIDS TWG), and an assumed maximum number of 12 inverter delays.

     Prior to the 2008 Update, the PIDS model was based on a fundamental reduction rate of ~ -14.7% for the transistor delay, which results in an individual transistor frequency growth rate of
     ~17.2% per year growth. In the 2007 roadmap, the PIDS TWG model continued to use a target of the on-chip frequency growth rate of ~17.2%.

     However, In the 2007 Roadmap, the ORTC Table 4c,d was adjusted to the revised Design TWG ~8% on-chip frequency growth target.. That ~8% growth rate target is continued in the
     ORTC Table 4c,d 2008 Update.

     In the 2008 Update, the 17% transistor performance trend target has been re-evaluated by the PIDS TWG; and now in their 2008 Update model work, the PIDS TWG is using, as a driver,
     the Design TWG revised long-range on-chip frequency trend: ~ 8% growth rate per year.

     The ongoing model revision work in 2008 and 2009 will reflect both the recent/y observed on-chip frequency slowing trends and also the anticipated speed-power design tradeoffs to manage
     a maximum 200 watts/chip affordable power management tradeoffs.

     [2] The off-chip frequency is defined by the Assembly and Packaging (A&P) model, and is available in the A&P chapter.



     [3] The maximum number of interconnect wiring levels includes the optional levels required for power, ground, signal conditioning, and integrated passives (i.e., capacitors).
                            2014         2015
                             28           25
                             22           20
                             28           25
                             17           15


                            7.911        8.522
                             13           13


er wiring levels - maximum" line is deleted; also the "Maximum number wiring levels - minimum" is now just "Maximum number of wiring levels."


ays.

al transistor frequency growth rate of



growth rate target is continued in the



 the PIDS TWG is using, as a driver,



eed-power design tradeoffs to manage




ves (i.e., capacitors).
                                                                                                             Comments

                       2016        2017         2018         2019         2020         2021         2022
                       22.5         20.0         17.9        15.9         14.2         12.6         11.3
                        18           16          14           13           11           10           9
                       22.5         20.0         17.9        15.9         14.2         12.6         11.3
                       14.0         12.8         11.7        10.7          9.7          8.9          8.1


                      9.180        9.889       10.652       11.475       12.361       13.315       14.343
                        13           14          14           14           14           15           15


" line is deleted; also the "Maximum number wiring levels - minimum" is now just "Maximum number of wiring levels."
      Table 5a&b Electrical Defects [**]

      Year of Production                                                  2007            2008             2009              2010   2011            2012           2013            2014
IS    DRAM ½ Pitch (nm) (contacted)                                        68              59               52                45     40              36              32             28
      Flash ½ Pitch (nm) (un-contacted Poly)(f)                            54               45              40                36     32              28              25             22
IS    MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                   68               59              52                45     40              36              32             28
IS    MPU Physical Gate Length (nm)                                        32               29              27                24      22             20              18             17
      Flash Random Defect D 0 at production chip size and
                            2
ADD   89.5% yield (faults/m ) §                                           2503            2503             2503              2503   2503            2503           2503            2503
      Flash Random Defect D 0 at production chip size and
                            2
ADD   89.5% yield (faults/m ) §                                           2503            2503             2503              2503   2503            2503           2503            2503
      DRAM Random Defect D 0 at production chip size and
                            2
                                                                          3517            2957             2957              2957   2957            2957           2957            2957
WAS   89.5% yield (faults/m ) §
      DRAM Random Defect D 0 at production chip size and
                            2                                             2430            2430             2430              2430   2430            2430           2430            2430
IS    89.5% yield (faults/m ) §
      MPU Random Defect D 0 at production chip size and 83%
                      2
      yield (faults/ m ) §§                                               1395            1395             1395              1395   1395            1395           1395            1395
      # Mask Levels—MPU                                                    33               35              35                35      35             35              37             37
      # Mask Levels—DRAM                                                   24               24              24                26      26             26              26             26
ADD   # Mask Levels—Flash [to be added in 2009]                            ??               ??              ??                ??     ??              ??              ??             ??


      Notes for Tables 5a and 5b (ORTC Electrical Defects are revised from 2007 ITRS document):
      D 0 — defect density
      § Notes regarding the DRAM and Flash chip size models, which affect defect density: Except for 2007-2009 column impact of the cell area, function density, and chip size (due to new survey 2.5-yea
      alignment), the DRAM Model is unchanged from the 2007 ITRS, and the cell area factor (design/process improvement) targets are as follows:

      1999–2006/8×: 2006 – - 2022/6×. Due to the elimination of the “7.5,” “7,”and the “5” DRAM Cell design improvement Factors [a] in the latest 2005 ITRS DRAM consensus model, the addition of “Moore
      bits/chip slows from 2× every 2.5–3 years to 2× every three years.


      DRAM product generations were increased by 4  bits/chip every four years with interim 2  bits/chip generation. However, in the last model 2005 ITRS timeframe refer to Figures 8 and 9 for bit size and b
      trends:
      1. at the Introduction phase, after the 16 Gbit generation, the introduction rate is 4  /six years (2  /three years); and


      2. at the Production phase, after the 4 Gbit generation, the introduction rate is 4  /six years (2  /three years).

      As a result of the latest DRAM consensus model changes for the 2007 ITRS, the InTER-generation chip size growth rate model target for Production-phase DRAM product are delayed an additional year a
                                          2
      remains “flat” at less than 93 mm , about one third smaller than the MPU model. However, with the pull-in of the 6f 2 “cell area factor” , the flat-chip-size model target still requires the bits/chip “Moore
      model for DRAM products to increase the time for doubling bits per chip to an average of 2  per 3 years (see ORTC Table 1c, 1d).


      In addition to the revisions noted above, the cell array efficiency (CAE – the Array % of total chip area) was change to 56.1% after 2006. Only the storage cell array area benefits from the 6× “cell area
      improvement, not the periphery, however, the CAE pull-in enables the production-phase product chip size to meet the target flat-chip-size model. It can be observed in the Table 1c and d model data that the
      generation chip size shrink model is still 0.5  every technology cycle (to 0.71× reduction) in-between cell area factor reductions.

      Refer to the Glossary for definitions of Introduction, Production, InTERgeneration, and InTRAgeneration terms.


      The Flash product model was revised in the 2007 roadmap to extend the 2-year-cycle half-pitch to 2008, also targets an affordable (<145 mm 2 ) chip size and includes a doubling of functions (bits) per ch
      technology cycle (three years after 2008) on an Inter-generation. Flash cells have reached a limit of the 4-design factor, so the reduction of the Flash single-level cell (SLC) size is paced by the unco
      polysilicon (three-year cycle).M1 ORTC DRAM Model changes are now reflected in the DRAM Random Defect targets. the same cell area, creating a multi-level-cell (MLC) “virtual” per-bit size that is one-ha
      The impact of the 2007-2009 However, the Flash technology has the ability to store and electrically access two bits in


      Also, new Flash Memory Product Defect Density line items have been added to provide Single-Level-Cell (SLC) and Multi-Level-Cell (MLC) defect density targets.


      The Flash number of mask steps is a new place-holder line item for the ORTC Table 5a,b. The line item will be filled out in the 2009 ITRS roadmap work.


      Refer to the Glossary for definitions of Introduction, Production, InTERgeneration, and InTRAgeneration terms.
                            2015
                             25
                             20
                             25
                             15


                            2503


                            2503

                            2957


                            2430



                            1395
                             37
                             26
                             ??




ty, and chip size (due to new survey 2.5-year cycle


AM consensus model, the addition of “Moore’s Law”



me refer to Figures 8 and 9 for bit size and bits/chip




AM product are delayed an additional year and now
del target still requires the bits/chip “Moore’s Law”



 array area benefits from the 6× “cell area factor”
ed in the Table 1c and d model data that the InTRA-




ncludes a doubling of functions (bits) per chip every
e-level cell (SLC) size is paced by the uncontacted
ll (MLC) “virtual” per-bit size that is one-half the
                             2016         2017   2018   2019   2020   2021   2022
                             22.5         20.0   17.9   15.9   14.2   12.6   11.3
                              18           16     14     13     11     10     9
                             22.5         20.0   17.9   15.9   14.2   12.6   11.3
                             14.0         12.8   11.7   10.7   9.7    8.9    8.1


                             2503         2503   2503   2503   2503   2503   2503


                             2503         2503   2503   2503   2503   2503   2503

                             2957         2957   2957   2957   2957   2957   2957


                             2430         2430   2430   2430   2430   2430   2430



                             1395         1395   1395   1395   1395   1395   1395
                              37           39     39     39     39     39     39
                              26           26     26     26     26     26     26
                              ??           ??     ??     ??     ??     ??     ??




e (due to new survey 2.5-year cycle


odel, the addition of “Moore’s Law”



ures 8 and 9 for bit size and bits/chip




 delayed an additional year and now
equires the bits/chip “Moore’s Law”



nefits from the 6× “cell area factor”
 1c and d model data that the InTRA-




ing of functions (bits) per chip every
C) size is paced by the uncontacted
al” per-bit size that is one-half the
      Table 6a&b Power Supply and Power Dissipation

      Year of Production                                               2007            2008        2009   2010   2011   2012   2013
IS    DRAM ½ Pitch (nm) (contacted)                                     68              59         52      45     40     36     32
      Flash ½ Pitch (nm) (un-contacted Poly)(f)                         54              45          40     36     32     28     25
IS    MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                68              59          52     45     40     36     32
IS    MPU Physical Gate Length (nm)                                      32             29          27     24     22     20     18
      Power Supply Voltage (V)
WAS   Vdd (high-performance)                                            1.1             1.0        1.0    1.0    0.95   0.90   0.90
 IS   Vdd (high-performance)                                            1.1             1.1        1.1    1.1    1.0    1.0    1.0


WAS   V dd (Low Operating Power, high V dd transistors)[WAS]            0.80           0.80        0.80   0.70   0.70   0.70   0.60

 IS   V dd (Low Operating Power, high V dd transistors)                 0.90           0.80        0.80   0.80   0.77   0.70   0.70
      Allowable Maximum Power [1]
IS    High-performance with heatsink (W)                                102            146         143    146    161    158    149
      Maximum Affordable Chip Size Target for High-
      performance MPU Maximum Power Calculation                         310            310         310    310    310    310    310
      Maximum High-performance MPU Maximum Power
IS    Density for Maximum Power Calculation                             0.33           0.47        0.46   0.47   0.52   0.51   0.48
IS    Cost-performance (W)                                              102            146         143    146    161    158    149
      Maximum Affordable Chip Size Target for Cost-
      performance MPU Maximum Power Calculation                         140            140         140    140    140    140    140
      Maximum Cost-performance MPU Maximum Power
IS    Density for Maximum Power Calculation                             0,57           0.86        0.9    0.96   1.13   1.11   1.1
      Battery (W)—(low-cost/hand-held)                                   3               3          3      3      3      3      3


      [1] Power will be limited more by system level cooling and test constraints than packaging
2014   2015
 28     25
 22     20
 28     25
 17     15


0.90   0.80
1.0    1.0


0.60   0.60
0.65   0.60


152    143

310    310

0.49   0.46
152    143

140    140

1.17   1.19
 3      3
                                                 Comments?

2016   2017   2018   2019   2020   2021   2022
22.5   20.0   17.9   15.9   14.2   12.6   11.3
 18     16     14     13     11     10     9
22.5   20.0   17.9   15.9   14.2   12.6   11.3
14.0   12.8   11.7   10.7   9.7    8.9    8.1


0.80   0.70   0.70   0.70   0.65   0.65   0.65
0.90   0.90   0.90   0.90   0.80   0.80   0.80


0.50   0.50   0.50   0.50   0.50   0.45   0.45
0.60   0.60   0.60   0.57   0.50   0.50   0.50


130    130    136    133    130    130    130

310    310    310    310    310    310    310

0.42   0.42   0.44   0.43   0.42   0.42   0.42
130    130    136    133    130    130    130

140    140    140    140    140    140    140

1.07   1.12   1.19   1.27   1.24   1.63   1.73
 3      3      3      3      3      3      3
     Table 7a&b Cost

     Year of Production                                                           2007             2008             2009           2010      2011            2012            2013


IS   DRAM ½ Pitch (nm) (contacted)                                                  68              59               52             45        40              36              32
     Flash ½ Pitch (nm) (un-contacted Poly)(f)                                      54              45               40             36        32              28              25
IS   MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                             68              59               52             45        40              36              32
IS   MPU Physical Gate Length (nm)                                                  32              29               27             24         22             20              18
     Affordable Cost per Function ++

     DRAM cost/bit at (packaged microcents) at samples/introduction                 2.6             1.9              1.3           0.9        0.7             0.5             0.3
     DRAM cost/bit at (packaged microcents) at production §                        0.96            0.68             0.48           0.34      0.24            0.17            0.12
     Cost-performance MPU (microcents/transistor)
     (including on-chip SRAM) at introduction §§                                   22.0            15.6             11.0           7.8        5.5             3.9             2.8
     Cost-performance MPU (microcents/transistor)
     (including on-chip SRAM) at production §§                                     13.3             9.4              6.7           4.7        3.3             2.4             1.7
     High-performance MPU (microcents/transistor)
     (including on-chip SRAM) at production §§                                     12.2             8.6              6.1           4.3        3.0             2.2             1.5



     Notes for Tables 7a and b (table unchanged from the 2007 ITRS document, but notes were updated to latest DRAM model):

     ++ Affordable packaged unit cost per function based upon average selling prices (ASPs) available from various analyst reports less gross profit margins (GPMs); 35% GPM used for commodity DRAMs and 60% GP
     for MPUs; 0.5  /two years inTER-generation reduction rate model used; .55  /year inTRA-generation reduction rate model used; DRAM unit volume life-cycle peak occurs when inTRA-generation cost per function is
     by next generation, typically seven–eight years after introduction; MPU unit volume life-cycle peak occurs typically after four–six years, when the next generation processor enters its ramp phase (typically two to fo
     after introduction).

     § DRAMChip size model: Except for 2007-2009 column impact of the cell area, function density, and chip size (due to new survey 2.5-year cycle alignment), the DRAM Model is unchanged from the 2007 ITRS, and
     area factor (design/process improvement) targets are as follows:

     1999–2006/8×: 2006 – - 2022/6×. Due to the elimination of the “7.5,” “7,”and the “5” DRAM Cell design improvement Factors [a] in the latest 2005 ITRS DRAM consensus model, the addition of “Moore’s Law” b
     slows from 2× every 2.5–3 years to 2× every three years.

     DRAM product generations were increased by 4  bits/chip every four years with interim 2  bits/chip generation. However, in the last model 2005 ITRS timeframe refer to Figures 8 and 9 for bit size and bits/chip tren


     1. at the Introduction phase, after the 16 Gbit generation, the introduction rate is 4  /six years (2  /three years); and


     2. at the Production phase, after the 4 Gbit generation, the introduction rate is 4  /six years (2  /three years).


     As a result of the latest DRAM consensus model changes for the 2007 ITRS, the InTER-generation chip size growth rate model target for Production-phase DRAM product are delayed an additional year and now
                                2
     “flat” at less than 93 mm , about one third smaller than the MPU model. However, with the pull-in of the 6f 2 “cell area factor” , the flat-chip-size model target still requires the bits/chip “Moore’s Law” model fo
     products to increase the time for doubling bits per chip to an average of 2  per 3 years (see ORTC Table 1c, 1d).

     In addition to the revisions noted above, the cell array efficiency (CAE – the Array % of total chip area) was change to 56.1% after 2006. Only the storage cell array area benefits from the 6× “cell area factor” impro
     not the periphery, however, the CAE pull-in enables the production-phase product chip size to meet the target flat-chip-size model. It can be observed in the Table 1c and d model data that the InTRA-generation c
     shrink model is still 0.5  every technology cycle (to 0.71× reduction) in-between cell area factor reductions.


     §§ MPU Chip Size Model—Both the cost-performance and high-performance MPUs InTER-generation production-level chip sizes are modeled to be below affordable targets, which are flat through 2022 (280 mm
                                              2                                            2
     performance at introduction; 140 mm /cost-performance at production; 310 mm /high-performance at production). The MPU flat chip-size affordability model is accomplished by doubling the on-chip functionali
     technology node cycle. Actual market chip sizes may exceed the affordability targets in order to continue the doubling of on-chip functionality on a shorter cycle, but their unit costs and market values must be incre
     the 2007 ITRS, the MPU model still includes introduction-level high-performance MPU targets that shrink to the “affordable” targets (the same way the DRAM model operates). The InTRA-generation chip size shrin
     is 0.5  every two-year density-driven technology cycle through 2004, and then 0.5  every three-year density-driven technology cycle after 2004, in order to stay under the affordable flat-chip-size target. . The 20
     model was revised by the Design TWG to introduce the doubling of logic cores every other technology cycle, but function size and density was kept unchanged by doubling the transistor/core targets. The Design TWG
     this approach to the MPU Model was more representative of current design trends.
     Refer to the Glossary for definitions.
                              2014            2015


                               28              25
                               22              20
                               28              25
                               17              15



                               0.2             0.2
                              0.08            0.06

                               1.9             1.4

                               1.2            0.83

                               1.1            0.76




(GPMs); 35% GPM used for commodity DRAMs and 60% GPM used
 ycle peak occurs when inTRA-generation cost per function is crossed
 neration processor enters its ramp phase (typically two to four years


 nt), the DRAM Model is unchanged from the 2007 ITRS, and the cell


RS DRAM consensus model, the addition of “Moore’s Law” bits/chip


meframe refer to Figures 8 and 9 for bit size and bits/chip trends:




ase DRAM product are delayed an additional year and now remains
el target still requires the bits/chip “Moore’s Law” model for DRAM


 cell array area benefits from the 6× “cell area factor” improvement,
  the Table 1c and d model data that the InTRA-generation chip size


                                                                2
low affordable targets, which are flat through 2022 (280 mm           /cost-
 y model is accomplished by doubling the on-chip functionality every
er cycle, but their unit costs and market values must be increased. In
DRAM model operates). The InTRA-generation chip size shrink model
 er to stay under the affordable flat-chip-size target. . The 2007 MPU
ged by doubling the transistor/core targets. The Design TWG believed
                              2016              2017   2018   2019   2020   2021   2022


                               22.5             20.0   17.9   15.9   14.2   12.6   11.3
                                18               16     14     13     11     10     9
                               22.5             20.0   17.9   15.9   14.2   12.6   11.3
                               14.0             12.8   11.7   10.7   9.7    8.9    8.1



                                0.1             0.1    0.1    0.0    0.0    0.0    0.0
                               0.04             0.03   0.02   0.01   0.01   0.01   0.01

                               0.97             0.69   0.49   0.34   0.24   0.17   0.12

                               0.59             0.42   0.29   0.21   0.15   0.10   0.07

                               0.54             0.38   0.27   0.19   0.13   0.10   0.07




 mmodity DRAMs and 60% GPM used
generation cost per function is crossed
amp phase (typically two to four years


nged from the 2007 ITRS, and the cell


 addition of “Moore’s Law” bits/chip


9 for bit size and bits/chip trends:




 an additional year and now remains
hip “Moore’s Law” model for DRAM


he 6× “cell area factor” improvement,
a that the InTRA-generation chip size


                                 2
 re flat through 2022 (280 mm          /cost-
ubling the on-chip functionality every
d market values must be increased. In
 RA-generation chip size shrink model
 flat-chip-size target. . The 2007 MPU
ore targets. The Design TWG believed
                                             Table ESH1             ESH Difficult Challenges
Difficult Challenges ≥ 22 nm             Summary of Issues
                                         Chemical Assessment
                                         Evaluation and refinement of quality, rapid assessment methodologies
                                             nanomaterials can be utilized in manufacturing, while protecting h
                                             environment without delaying process implementation
                                         Regional differences in regulations for chemicals; given regional move
                                             and full commercialization
                                         Trend towards lowering exposure limits and more monitoring
Chemicals and materials management       Chemical Data Availability
                                         Inability to forecast/anticipate future restrictions or bans on materials,
                                         Lack of comprehensive ESH data for new, proprietary chemicals and m
                                             external and regional requirements on the use of chemicals
                                         Chemical Exposure Management
                                         Lack of information on how the chemicals and materials are used and
                                         Method to obtain information on how the chemicals and materials are
                                             are formed
                                         Process Chemical Optimization
                                         Need to develop equipment and processes that meet technology deman
                                             health, safety and the environment, both through the use of more b
                                             chemical quantity requirements through more efficient and cost-ef
                                         Environment Management
                                         Capability for component isolation in waste streams
                                         Need to understand ESH characteristics of process emissions and by-p
                                            mitigation
                                         Need to develop effective management systems to address issues relate
                                             residues from the manufacturing processes
                                         Global Warming Emissions Reduction
                                         Need to reduce emissions from processes using high GWP chemicals
                                         Water and Energy Conservation
                                         Need for innovative energy- and water-efficient processes and equipm
Process and equipment management         Consumables Optimization
                                         Need for more efficient utilization of chemicals and materials, and inc
                                         Byproducts Management
                                         Development of improved metrology for byproduct speciation.
                                         Chemical Exposure Management
                                         Need to design-out potential for chemical exposures and the necessity
                                             (PPE)
                                         Design for Maintenance
                                         Need to design equipment so that commonly serviced components and
                                            safely accessed
                                         Need to design equipment so that maintenance and service may be safe
                                         Need to minimize health and safety risks during maintenance activities
                                         Equipment End-of-Life
                                         Need to develop effective management systems to address issues relate
                                         Conservation
                                         Need to reduce use of energy, water and other utilities
                                         Need for more efficient thermal management of cleanrooms and facilit
Facilities technology requirements
                                         Global Warming Emissions Reduction
                                         Need to design energy efficient manufacturing facilities
                                         Need to reduce total CO2 equivalent emissions
                                         Sustainability Metrics
                                         Need to identify the elements for defining and measuring the sustainab
                                         Design for ESH
Sustainability and product stewardship
                                         Need to make ESH a design parameter at the design stage of new equi
                                         End-of-Life Disposal/Reclaim
                                          Need to develop effective management systems to address issues relate
                                          Conservation
                                          Need to reduce use of energy, water and other utilities
                                          Need for more efficient thermal management of cleanrooms and facilit
Facilities technology requirements
                                          Global Warming Emissions Reduction
                                          Need to design energy efficient manufacturing facilities
                                          Need to reduce total CO2 equivalent emissions
                                          Sustainability Metrics
                                          Need to identify the elements for defining and measuring the sustainab
                                          Design for ESH
Sustainability and product stewardship
                                          Need to make ESH a design parameter at the design stage of new equi
                                          End-of-Life Disposal/Reclaim
                                          Need to design facilities, equipment and products to facilitate re-use/di

Difficult Challenges < 22 nm             Summary of Issues
                                         Chemical Assessment
                                         Evaluation and refinement of quality, rapid assessment methodologies t
                                             nanomaterials can be utilized in manufacturing, while protecting hu
                                             environment without delaying process implementation
Chemicals and materials management       Chemical Data Availability
                                         Lack of comprehensive ESH data for new, proprietary chemicals and m
                                             external and regional requirements on the use of chemicals
                                         Chemical Exposure Management
                                         Lack of information on how the chemicals and materials are used and w
                                         Chemical Reduction
                                         Need to develop processes that meet technology demands while reducin
                                            the environment, both through the use of more benign materials, an
                                            requirements through more efficient and cost-effective process man
                                         Need to reduce emissions from processes using high GWP chemicals
                                         Environment Management
                                         Need to understand ESH characteristics of process emissions and by-pro
                                            mitigation
                                         Need to develop effective management systems to address issues related
                                            residues from the manufacturing processes
                                         Water and Energy Conservation
                                         Need to reduce water and energy consumption
Process and equipment management
                                         Need for innovative energy and water-efficient processes and equipmen
                                         Consumables Optimization
                                         Need for more efficient utilization of chemicals and materials, and incre
                                         Chemical Exposure Management
                                         Need to design-out potential for chemical exposures and need for person
                                         Design for Maintenance
                                         Need to design equipment so that maintenance and service may be safel
                                         Need to design equipment so that commonly serviced components and c
                                         Need to minimize health and safety risks during maintenance activities
                                         Equipment End-of-Life
                                         Need to develop effective management systems to address issues related
                                         Conservation
                                         Need to reduce use of energy, water and other utilities
                                         Need for more efficient thermal management of cleanrooms and facilitie
Facilities technology requirements
                                         Global Warming Emissions Reduction
                                         Need to design energy efficient facilities support equipment and manufa
                                         Need to reduce emissions from processes using high GWP chemicals
                                         Sustainability Metric
                                         Need to identify the elements for defining and measuring the sustainabil
                                         Need to identify the elements for defining and measuring sustainability
                                         Design for ESH
Sustainability and product
stewardship                              Need method to holistically evaluate and quantify the ESH impacts of p
                                            equipment for the total manufacturing process
                                         Need to make ESH a design parameter in development of new equipme
                                         End-of-Life Disposal/Reclaim
                             Global Warming Emissions Reduction
                             Need to design energy efficient facilities support equipment and manufa
                             Need to reduce emissions from processes using high GWP chemicals
                             Sustainability Metric
                             Need to identify the elements for defining and measuring the sustainabil
                             Need to identify the elements for defining and measuring sustainability
                             Design for ESH
Sustainability and product
stewardship                  Need method to holistically evaluate and quantify the ESH impacts of p
                                equipment for the total manufacturing process
                             Need to make ESH a design parameter in development of new equipme
                             End-of-Life Disposal/Reclaim
                             Need to design facilities, equipment, and products to facilitate re-use/dis
H Difficult Challenges


uality, rapid assessment methodologies to ensure that new materials such as
ed in manufacturing, while protecting human health, safety, and the
 ng process implementation
 ons for chemicals; given regional movement for R&D, pre-manufacturing,

 re limits and more monitoring

 uture restrictions or bans on materials, especially nanomaterials
ta for new, proprietary chemicals and materials to respond to the increasing
 ements on the use of chemicals
nt
 chemicals and materials are used and what process by-products are formed
 n how the chemicals and materials are used and what process by-products


  processes that meet technology demands while reducing impact on human
 onment, both through the use of more benign materials, and by reducing
 ents through more efficient and cost-effective process management

 ion in waste streams
 teristics of process emissions and by-products to identify the appropriate

 gement systems to address issues related to hazardous and non-hazardous
uring processes
 uction
processes using high GWP chemicals
n
d water-efficient processes and equipment

 on of chemicals and materials, and increased reuse and recycling

ology for byproduct speciation.
nt
 chemical exposures and the necessity for personal protective equipment



 at commonly serviced components and consumable items are easily and

 at maintenance and service may be safely performed by a single person
 fety risks during maintenance activities.

 gement systems to address issues related to re-use and disposal of equipment

water and other utilities
 management of cleanrooms and facilities systems
 uction
 manufacturing facilities
 lent emissions

 r defining and measuring the sustainability of a technology generation

 ameter at the design stage of new equipment, processes and products
 gement systems to address issues related to re-use and disposal of equipment

water and other utilities
 management of cleanrooms and facilities systems
 uction
 manufacturing facilities
 lent emissions

 r defining and measuring the sustainability of a technology generation

 ameter at the design stage of new equipment, processes and products

ment and products to facilitate re-use/disposal at end of life




 lity, rapid assessment methodologies to ensure that new materials such as
d in manufacturing, while protecting human health, safety, and the
 g process implementation


 for new, proprietary chemicals and materials to respond to the increasing
 ments on the use of chemicals


 hemicals and materials are used and what process by-products are formed


 eet technology demands while reducing impact on human health, safety, and
gh the use of more benign materials, and by reducing chemical quantity
 fficient and cost-effective process management
 rocesses using high GWP chemicals


eristics of process emissions and by-products to identify the appropriate

 ement systems to address issues related to hazardous and non-hazardous
 ring processes


 consumption
water-efficient processes and equipment


 n of chemicals and materials, and increased reuse and recycling


chemical exposures and need for personal protective equipment (PPE)


  maintenance and service may be safely performed by a single person
  commonly serviced components and consumable items are easily accessed
 ty risks during maintenance activities


 ement systems to address issues related to re-use and disposal of equipment


 ter and other utilities
management of cleanrooms and facilities systems
 ction
 acilities support equipment and manufacturing facilities.
 rocesses using high GWP chemicals


 defining and measuring the sustainability of a technology generation
 defining and measuring sustainability at a factory infrastructure level


uate and quantify the ESH impacts of processes, chemicals, and process
 facturing process
 meter in development of new equipment, processes and products
ction
acilities support equipment and manufacturing facilities.
rocesses using high GWP chemicals


 defining and measuring the sustainability of a technology generation
 defining and measuring sustainability at a factory infrastructure level


uate and quantify the ESH impacts of processes, chemicals, and process
 facturing process
meter in development of new equipment, processes and products


ent, and products to facilitate re-use/disposal at end of life
         Table ESH2A                                                           ESH Intrinsic Requirements—Near-term Years

         Year of Production                                                       2007            2008           2009          2010

         I. Chemicals and Materials Management Technology Requirements
         Chemical risk assessments (environmental, health and safety)
                                                                                           100%                         100%
         defined and completed
         ESH risk assessment techniques for nano-materials and nano-              Develop assessment
                                                                                                                                      Implement risk asses
         particles                                                                   methodology.
         II. Process and Equipment Technology Requirements
         Energy Consumption
  IS     Total fab tools (kWh/cm2) [2] [3]                                                        0.5                                      0.43
DELETE   Tool energy usage (% of 2005 baseline)                                                    90                                       80
DELETE   Tool total equivalent energy* (% of 2007 baseline)                                 100                   80                        70
         Water Consumption (driven by sustainable growth and cost)
         Surface preparation UPW use (% of 2005 baseline)                                    90                                             80
         Tool UPW usage (% of 2005 baseline)                                                 90                                             80
         Chemical Consumption and Waste Reduction (driven by environmental stewardship and cost)

         Improvement in process chemical utilization (% of 2005 baseline)                          90                                       80


                                                                               10% absolute reduction from 1995 baseline by 2010 as
         Reduce PFC emission
                                                                               agreed to by the World Semiconductor Council (WSC)

         Liquid and solid waste reduction (% of 2007 baseline)                              100                   90                        80
         Worker and Workplace Protection
         Safety screening methodologies for new technologies (e.g., 450mm,
                                                                                         Develop methodologies.                                     Implem
         EUV lithography, ERM)
         III. Facilities Technology Requirements
         Energy Consumption
                                          2
  IS     Total fab energy usage (kWh/cm ) [3]                                                      1                                       0.85
                                                          2
  IS     Total fab support systems energy usage (kWh/cm ) [2]                                     0.5                                      0.43

DELETE   Reduce total fab energy usage (% of 2007 baseline)                                 100                   90                        80
         Water Consumption
                                      2
DELETE   Net feed water use (liters/cm ) [2]                                        15                   15-12                            10-Dec
                                 2
DELETE   Fab UPW use (liters/cm ) [2]                                               8                    7-Aug                             6-Jul
         Chemical Consumption and Waste Reduction
         Reduce hazardous liquid waste by recycle/reuse** (% of 2007
                                                                                            100                   90                        80
         baseline)
         Reduce solid waste by recycle/reuse** (% of 2007 baseline)                         100                   90                        80
         IV. Sustainability and Product Stewardship Requirements

         Define environmental footprint metrics for process, equipment,
                                                                                     Define metrics and baseline.                     90% of baseline
         facilities, and products; reduce from baseline year.

         Integrate ESH priorities into the design process for new processes,
                                                                                     Define metrics and baseline.
         equipment, facilities, and products.
         Facilitate end-of-life disposal/reclaim                                     Define metrics and baseline.


         Notes for Table ESH2a and b:
         [1] CPIF = Chemical Properties Information Form
         [2] cm 2 per wafer out
 ADD     [3] Without including the influence of EUV
* as defined by SEMI guideline S23
**Recycle = Re-use after treatment

**Reuse = Use in secondary application (without treatment)
**Reclaim = Extracting a useful component from waste


          Manufacturable solutions exist, and are being optimized
                             Manufacturable solutions are known
                                      Interim solutions are known   
                        Manufacturable solutions are NOT known
ear-term Years

                 2011             2012         2013          2014         2015



                                               100%

            Implement risk assessment methodology.




                  0.43                                       0.35
                  80                              Functional Area Goals TBD
                  70                                          60


                  80                                          75
                  80                                          75


                  80                                          75


                         Maintain 10% absolute reduction from 1995 baseline


                  80                                          75


                             Implement methodologies.




                  0.85                                       0.7

                  0.43                                       0.35
                  80                                          70


                 10-Dec                                     8-Oct

                 6-Jul                                      4-Jun



                  80                                          75

                  80                                          75



           90% of baseline                             80% of baseline
         Table ESH2b                                                           ESH Intrinsic Requirements—Long-term Years

         Year of Production                                                         2016        2017        2018            2019

         I. Chemicals and Materials Management Technology Requirements
         Chemical risk assessments (environmental, health and safety)
                                                                                                                     100%
         defined and completed
         II. Process and Equipment Technology Requirements
         Energy Consumption
  IS     Total fab tools (kWh/cm2) [2] [3]                                                                         0.30-0.25
DELETE   Tool energy usage (kWh per wafer pass)                                                            Functional Area Goals TBD
DELETE   Tool total equivalent energy* (% of baseline)                                                                50
         Water Consumption (driven by sustainable growth and cost)
         Surface preparation UPW use (liters per wafer pass)                                                          50
         Tool UPW usage (% of 2005 baseline)                                                                          50
         Chemical Consumption and Waste Reduction (driven by environ-mental stewardship and cost)

         Improvement in process chemical utilization (% of 2005 baseline)                                             50

         Reduce PFC emission                                                                   Maintain 10% absolute reduction from 1995 baseline
         Reduce liquid and solid waste (% of 2007 baseline)                                                           50
         III.. Facilities Technology Requirements
         Energy Consumption
  IS     Total fab energy usage (kWh/cm2) [3]                                                                       0.6-0.5
                                                         2                                                         0.30-0.25
  IS     Total fab support systems energy usage (kWh/cm ) [2]
DELETE   Reduce total fab energy usage (% of 2007 baseline)                                                           50
         Water Consumption
DELETE   Net feed water use (liters/cm2) [2]                                                                          8-6
DELETE   Fab UPW use (liters/cm2) [2]                                                                                 4-3
         Chemical Consumption and Waste Reduction
         Reduce hazardous liquid waste by recycle/reuse** (% of 2007
                                                                                                                      50
         baseline)
         Reduce solid waste by recycle/reuse** (% of 2007 baseline)                                                   50
         IV. Sustainability and Product Stewardship Requirements

         Define environmental footprint metrics for process, equipment,
                                                                                                                50% of baseline
         facilities, and products; reduce from baseline year.


         Notes for Table ESH2a and b:
         [1] CPIF = Chemical Properties Information Form
         [2] cm 2 per wafer out
 ADD     [3] Without including the influence of EUV
         * as defined by SEMI guideline S23
         **Recycle = Re-use after treatment

         **Reuse = Use in secondary application (without treatment)
         **Reclaim = Extracting a useful component from waste


                    Manufacturable solutions exist, and are being optimized
                                         Manufacturable solutions are known
                                                 Interim solutions are known   
                                   Manufacturable solutions are NOT known
ng-term Years

                       2020          2021   2022



     100%




    0.30-0.25
ional Area Goals TBD
       50

       50
       50


       50

olute reduction from 1995 baseline
       50



     0.6-0.5
    0.30-0.25
       50


      8-6
      4-3


       50

       50



50% of baseline
Table ESH3                                                                Chemicals and Materials Management Technology Requir

The Environment, Safety, and Health new chemical screening tool ( Chemical Restrictions Table ) is linked online

Year of Production                                                                   2007                   2008          2009
Interconnect
                                                                          Establish chemical              Maintain or improve
Low-k materials—spin-on and CVD                                           utilization* and process        chemical utilization* by 10%
                                                                          byproducts baseline
                                                                          75% copper                      85% copper reclaimed/recycled
Copper deposition processes (conventional and alternative)
                                                                          reclaimed/recycled
                                                                          Establish chemical              Maintain or improve
Advanced metallization including barrier and nucleation deposition        utilization* and process        chemical utilization* by 10%;
                                                                          byproducts baseline             minimize process byproducts
                                                                          Characterize emissions and
Planarization methods                                                     consumables; establish                        > 15% Reduction in consumables
                                                                          baseline.
                                                                          Alternatives with improved Alternatives with improved
                                                                          ESH impacts. Maintain or        ESH impacts. Maintain or
Plasma etch                                                               improve chemical                improve chemical utilization*
                                                                          utilization*; characterize      by 10%; minimize process
                                                                          process byproducts.             byproducts.
                                                                          Alternatives with improved Alternatives with improved
                                                                          ESH impacts (e.g. lower         ESH impacts. Maintain or
                                                                          GWP, improve utilization);      improve chemical utilization*
CVD chamber clean (plasma)                                                characterize process            by 10%; minimize process
                                                                          byproducts.                     byproducts.
                                                                          Reduce Global Warming Impact (lower GWP emissions;
                                                                          improved utilization*) without increasing ESH risk

                                                                          Alternatives with improved   Alternatives with improved
                                                                          ESH impacts. Maintain or     ESH impacts. Maintain or
Surface preparation                                                       improve chemical             improve chemical utilization*
                                                                          utilization*; characterize   by 10%.
                                                                          emissions.
                                                                                                       Reduce Global Warming
                                                                                                       Impact (lower GWP
                                                                                                       emissions; alternative
                                                                          Characterize emissions;      etchants, improved
Through-silicon via etch using PFCs (e.g., 3D)
                                                                          establish baseline.          utilization*) without
                                                                                                       increasing ESH risk.
                                                                                                       Maintain or improve
                                                                                                       chemical utilization* by 10%.
Front End Processes
                                                                          Conduct ESH risk assessment of materials. Maintain or
High-k and metal gate materials                                           improve chemical utilization*; minimize process
                                                                          byproducts
Doping (implantation and diffusion)                                                     Low hazard dopant materials
                                                                          Characterize emissions;      Maintain or improve
Conventional surface preparation (stripping, cleaning, rinsing, drying)
                                                                          establish baseline.          chemical usage by 10%.

                                                                          Identify novel wafer cleaning materials. Conduct ESH risk
Alternative surface preparation methods
                                                                          assessment of materials

                                                                                                       Alternatives with improved
                                                                          Alternatives with improved   ESH impacts. Maintain or
Plasma etch                                                               ESH impacts; minimize        improve chemical utilization*
                                                                          process byproducts.          by 10%; minimize process
                                                                                                       byproducts.

                                                                          Conduct ESH risk assessment of materials. Maintain or improve chemical uti
Non-silicon, active substrates (channel)
                                                                                                                     byproducts.
                                                                          Conduct ESH risk assessment of materials. Maintain or
Novel memory materials                                                    improve chemical utilization*; minimize process
                                                                          byproducts.
Lithography

193 nm immersion resists                                                  Conduct ESH risk assessment of materials.


                                                                          Conduct ESH risk              Maintain or improve
193 nm immersion fluids
                                                                          assessment of materials.      chemical utilization by 10%.


EUV resists                                                               Conduct ESH risk assessment of materials.



Imprint                                                                   Conduct ESH risk assessment of materials.



PFOS/PFAS** chemicals                                                                                PFOS/PFAS alternatives researched / implemented

                                                                                                         Alternatives with improved
                                                                          Characterize emissions;        ESH impacts. Maintain or
Mask making and cleaning                                                                                improve chemical utilization
                                                                          establish baseline.
                                                                                                         by 10%; minimize process
                                                                                                                byproducts.
Assembly & Packaging
                                                                                                          Alternatives with improved
                                                                          Characterize emissions;          ESH impacts. Maintain or
Die thinning                                                                                             improve chemical utilization*
                                                                          establish baseline.
                                                                                                          by 10%; minimize process
                                                                                                                   byproducts.
                                                                                                          Alternatives with improved
                                                                          Characterize emissions;          ESH impacts. Maintain or
Assembly and packaging wastes                                                                            improve chemical utilization*
                                                                          establish baseline.
                                                                                                          by 10%; minimize process
                                                                                                                   byproducts.
                                                                                                        Reduce Global Warming
                                                                                                        Impact (lower GWP
                                                                                                        emissions; alternative
                                                                          Characterize emissions;       etchants, improved
Through-silicon via etch using PFCs (e.g., 3D)
                                                                          establish baseline.           utilization*) without
                                                                                                        increasing ESH risk.
                                                                                                        Maintain or improve
                                                                                                        chemical utilization* by 10%.
Emerging Research Materials
Nanomaterials                                                             Conduct ESH risk assessment of materials.
Biological materials and their waste                                      Conduct ESH risk assessment of materials.
Materials for novel logic and memory                                      Conduct ESH risk assessment of materials.
* Utilization = [(Feed - Output)/Feed] × 100%

** PFOS = perfluorooctane sulfonate; PFAS = perfluoroalkyl sulfonate




                Manufacturable solutions exist, and are being optimized
                                    Manufacturable solutions are known
                                            Interim solutions are known   
                              Manufacturable solutions are NOT known
gement Technology Requirements


                      2010           2011           2012           2013            2014           2015          2016           2017           2018


                 Maintain or improve chemical utilization* by Maintain or improve chemicals utilization*
                                                                                                                       Maintain or improve chemicals utilization* by 10% and minimize p
                 10%                                          by 10%

reclaimed/recycled                                    99% copper reclaimed/recycled                                                             100% copper reclaimed/recycled

                 Maintain or improve chemical utilization* by Maintain or improve chemicals utilization*
                                                                                                               Maintain or improve chemicals utilization* by 10% and minimize process
                 10%; minimize process byproducts             by 10%; minimize process byproducts

> 15% Reduction in consumables from baseline                   2% reduction in consumables per year                                          2% reduction in consumables per year

                 Alternatives with improved ESH impacts.       Alternatives with improved ESH impacts.
                 Low ESH impact chemistries. Maintain or       Low ESH impact chemistries. Maintain or        Alternatives with improved ESH impacts. Low ESH impact chemistries. Ma
                 improve chemical utilization* by 10%;         improve chemical utilization* by 10%;                                   utilization* by 10%; minimize process byproducts
                 minimize process byproducts.                  minimize process byproducts.
                 Alternatives with improved ESH impacts.       Alternatives with improved ESH impacts.
                 Low ESH impact chemistries. Maintain or       Low ESH impact chemistries. Maintain or        Alternatives with improved ESH impacts. Low ESH impact chemistries. Ma
                 improve chemical utilization* by 10%;         improve chemical utilization* by 10%;                                   utilization* by 10%; minimize process byproducts
                 minimize process byproducts.                  minimize process byproducts.
                 Reduce Global Warming Impact (lower           Reduce Global Warming Impact (lower
                                                                                                              Reduce Global Warming Impact (lower GWP emissions; improved utilizatio
                 GWP emissions; improved utilization*)         GWP emissions; improved utilization*)
                                                                                                                                                         risk
                 without increasing ESH risk                   without increasing ESH risk

                 Alternatives with improved ESH impacts.      Alternatives with improved ESH impacts.
                 Maintain or improve chemical utilization* by Maintain or improve chemical utilization* by        Alternatives with improved ESH impacts; 2% reduction in chemicals pe
                 10%.                                         10%.



                 Reduce Global Warming Impact (lower           Reduce Global Warming Impact (lower
                 GWP emissions; alternative etchants,          GWP emissions; alternative etchants,
                                                                                                               Reduce Global Warming Impact (lower GWP emissions; alternative etcha
                 improved utilization*) without increasing     improved utilization*) without increasing
                                                                                                                        without increasing ESH risk. Maintain or improve chemical util
                 ESH risk. Maintain or improve chemical        ESH risk. Maintain or improve chemical
                 utilization* by 10%.                          utilization* by 10%.




                 Maintain or improve chemical utilization* by Maintain or improve chemical utilization* by
                                                                                                               Maintain or improve chemical utilization* by 10% and minimize process e
                 10% and minimize process byproducts          10% and minimize process byproducts

                                                Low hazard dopant materials                                                                          Low hazard materials
                 Maintain or improve chemical usage by         Maintain or improve chemical usage by
                                                                                                                                          Maintain or improve chemical usage by 10%
                 10%.                                          10%.

                 Maintain or improve chemical usage by         Maintain or improve chemical usage by
                                                                                                                                         Maintain or improve chemical usage by 10%.
                 10% and minimize process byproducts           10% and minimize process byproducts

                 Alternatives with improved ESH impacts.
                                                                Alternatives with improved ESH impacts.
                 Low ESH impact chemistries Maintain or                                                       Alternatives with improved ESH impacts. Maintain or improve chemical ut
                                                               Maintain or improve chemical utilization* by
                 improve chemical utilization* by 10%;                                                                                        process emissions and byproducts
                                                                   10%; minimize process byproducts.
                 minimize process byproducts.

s. Maintain or improve chemical utilization*; minimize process Maintain or improve chemical utilization* by
                                                                                                               Maintain or improve chemical utilization* by 10% and minimize process e
    byproducts.                                                10% and minimize process byproducts
                Maintain or improve chemical utilization* by Maintain or improve chemical utilization* by
                                                                                                              Maintain or improve chemical utilization* by 10% and minimize process e
                10% and minimize process byproducts          10% and minimize process byproducts



                 Maintain or improve chemical utilization* by Maintain or improve chemical utilization* by   Maintain or improve chemical utilization* by 10% and minimize process by
                                   10%.                                         10%.                                                      hazardous solvents, PFAS-free resists.

                 Maintain or improve chemical utilization* by Maintain or improve chemical utilization* by
                                                                                                              Maintain or improve chemical utilization* by 10% and minimize process e
                                   10%.                                         10%.

                 Maintain or improve chemical utilization* by Maintain or improve chemical utilization* by   Maintain or improve chemical utilization* by 10% and minimize process by
                                   10%.                                         10%.                                                      hazardous solvents, PFAS-free resists.

                                                              Maintain or improve chemical utilization* by
                 Conduct ESH risk assessment of materials.                                                    Maintain or improve chemical utilization* by 10% and minimize process e
                                                                                10%.

                                                               Non-PFAS materials developed for critical
ernatives researched / implemented                                                                                             PFAS-free materials developed for critical uses in litho
                                                                        uses in lithography

                  Alternatives with improved ESH impacts.      Alternatives with improved ESH impacts
                  Low ESH impact chemistries Maintain or      (PFOS-free). Maintain or improve chemical Alternatives with improved ESH impacts (PFAS-free). Maintain or improve c
                   improve chemical utilization* by 10%;         utilization* by 10%; minimize process                              minimize process emissions and byproducts.
                        minimize process byproducts.                            byproducts.


                  Alternatives with improved ESH impacts.
                                                               Alternatives with improved ESH impacts.
                  Low ESH impact chemistries Maintain or                                                     Alternatives with improved ESH impacts. Maintain or improve chemical ut
                                                              Maintain or improve chemical utilization* by
                   improve chemical utilization* by 10%;                                                                                           process byproducts.
                                                                  10%; minimize process byproducts.
                        minimize process byproducts.

                  Alternatives with improved ESH impacts.
                                                               Alternatives with improved ESH impacts.
                  Low ESH impact chemistries Maintain or                                                     Alternatives with improved ESH impacts. Maintain or improve chemical ut
                                                              Maintain or improve chemical utilization* by
                   improve chemical utilization* by 10%;                                                                                           process byproducts.
                                                                  10%; minimize process byproducts.
                        minimize process byproducts.


                Reduce Global Warming Impact (lower          Reduce Global Warming Impact (lower
                GWP emissions; alternative etchants,         GWP emissions; alternative etchants,
                                                                                                             Reduce Global Warming Impact (lower GWP emissions; alternative etcha
                improved utilization*) without increasing    improved utilization*) without increasing
                                                                                                                      without increasing ESH risk. Maintain or improve chemical util
                ESH risk. Maintain or improve chemical       ESH risk. Maintain or improve chemical
                utilization* by 10%.                         utilization* by 10%.



                                       Conduct ESH risk assessment of materials.                                                        Conduct ESH risk assessment of materials.
                                       Conduct ESH risk assessment of materials.                                                        Conduct ESH risk assessment of materials.
                                       Conduct ESH risk assessment of materials.                                                        Conduct ESH risk assessment of materials.
                     2019            2020          2021            2022


ve chemicals utilization* by 10% and minimize process byproducts

        100% copper reclaimed/recycled

micals utilization* by 10% and minimize process emissions and byproducts


     2% reduction in consumables per year


 ESH impacts. Low ESH impact chemistries. Maintain or improve chemical
utilization* by 10%; minimize process byproducts.



 ESH impacts. Low ESH impact chemistries. Maintain or improve chemical
utilization* by 10%; minimize process byproducts.


mpact (lower GWP emissions; improved utilization*) without increasing ESH
                    risk



 ved ESH impacts; 2% reduction in chemicals per year; recycle/reclaim




Impact (lower GWP emissions; alternative etchants, improved utilization*)
sing ESH risk. Maintain or improve chemical utilization by 10%.




mical utilization* by 10% and minimize process emissions and byproducts

              Low hazard materials

  Maintain or improve chemical usage by 10%


  Maintain or improve chemical usage by 10%.



d ESH impacts. Maintain or improve chemical utilization* by 10%; minimize
       process emissions and byproducts



mical utilization* by 10% and minimize process emissions and byproducts
mical utilization* by 10% and minimize process emissions and byproducts




ical utilization* by 10% and minimize process byproducts; low-hazard/non-
     hazardous solvents, PFAS-free resists.


mical utilization* by 10% and minimize process emissions and byproducts


ical utilization* by 10% and minimize process byproducts; low-hazard/non-
     hazardous solvents, PFAS-free resists.


mical utilization* by 10% and minimize process emissions and byproducts



free materials developed for critical uses in lithography



ESH impacts (PFAS-free). Maintain or improve chemical utilization* by 10%;
 minimize process emissions and byproducts.




d ESH impacts. Maintain or improve chemical utilization* by 10%; minimize
             process byproducts.



d ESH impacts. Maintain or improve chemical utilization* by 10%; minimize
             process byproducts.




Impact (lower GWP emissions; alternative etchants, improved utilization*)
sing ESH risk. Maintain or improve chemical utilization by 10%.




   Conduct ESH risk assessment of materials.
   Conduct ESH risk assessment of materials.
   Conduct ESH risk assessment of materials.
Table ESH4a                                                      Process and Equipment Management Technology Requirements—

* The Environment, Safety, and Health new chemical screening tool ( Chemical Restrictions Table ) is linked online


Year of Production                                                       2007                   2008                  2009

Interconnect

                                                                 Establish chemical
                                                                 utilization and
Low-k processing spin-on and CVD                                                               Maintain or improve chemical utilization* by 10%; charac
                                                                 process byproducts
                                                                 baseline


                                                                   Baseline copper
                                                                 processes; optimize
                                                                    processes to
Copper deposition processes (conventional and alternative)                                                                                    Optimize
                                                                      minimize
                                                                  consumables and
                                                                       waste


                                                                  Establish chemical
Advanced metallization including barrier and nucleation              utilization and
                                                                                             Maintain or improve chemical utilization* by 10% and char
deposition                                                        process byproducts
                                                                         baseline


                                                                 Establish baseline for
                                                                                                                        >15% Reduction in consumabl
                                                                     consumables
Planarization methods
                                                                 Establish baseline for
                                                                                                                        >15% Reduction in water usag
                                                                     water usage

                                                                 Reduce Global Warming Impact (lower GWP emissions; improved
Plasma etch processes
                                                                 utilization*) without increasing ESH risk


                                                                 Reduce Global Warming Impact (lower GWP emissions; improved
CVD chamber clean (plasma)
                                                                 utilization*) without increasing ESH risk


                                                                 Establish baseline for
                                                                  chemical and water
Surface preparation                                                                                              > 15% Reduction in chemicals and wa
                                                                 usage.; characterize
                                                                      emissions


                                                                                          Reduce Global Warming impact (lower
                                                                    Characterize
                                                                                          GWP emissions; improved utilization*)
Through-silicon via etch using PFCs (e.g., 3D)                   emissions; establish
                                                                                          without increasing ESH risk. Maintain or
                                                                      baseline
                                                                                            improve chemical utilization by 10%




Front End Processes



                                                                     Characterize emissions; establish chemical utilization* and
                                                                                   process emissions baseline
High-k and metal gate processes                                    Establish energy
                                                                                                                          Energy efficient deposition p
                                                                   usage baseline
                                                                Low hazard dopant materials and processes
Doping (implantation and diffusion)
                                                       Establish energy
                                                                                                                            Energy
                                                       usage baseline

                                                     ESH-friendly wafer clean and rinse processes and tools evaluated


                                                     Characterize
                                                     emissions; establish    Maintain or improve chemical and water
Surface preparation (stripping, cleaning, rinsing)
                                                     water and chemical                utilization* by 10%
                                                     usage baselines.

                                                       Energy efficient clean processes (reduced exhaust flow rates,
                                                                             optimized heaters)
                                                     Identify novel wafer cleaning processes and equipment.
Alternative surface preparation methods              Characterize emissions; establish water and chemical usage
                                                     baselines. Conduct ESH risk assessment


                                                     Alternatives with
                                                                           Alternatives with improved ESH impacts.
                                                     improved ESH
Plasma etch processing                                                     Maintain or improve chemical utilization* by
                                                     impacts; characterize
                                                                           10%; characterize process byproducts.
                                                     process byproducts.


                                                     Conduct ESH risk assessment of processes and equipment. Maintain or improve chem
Non-silicon, active substrates (channel)
                                                                                                           and byproducts


                                                     Conduct ESH risk assessment of processes and equipment.
Novel memory materials                               Maintain or improve chemical utilization*; characterize process
                                                     emissions and byproducts


Lithography



193 nm immersion lithography                         Conduct ESH risk assessment of processes and equipment



EUV                                                  Conduct ESH risk assessment of processes and equipment

Imprint                                              Conduct ESH risk assessment of processes and equipment

                                                        Characterize      Maintain or improve chemical utilization* by
Mask cleaning                                        emissions; establish 10%; characterize process emissions and
                                                          baseline                        byproducts

Assembly and Packaging

                                                        Establish ESH
Molding process                                                                  Minimize molding process waste
                                                       impact baseline.

                                                                             Alternatives with improved ESH impacts.
                                                     Characterize
                                                                            Maintain or improve chemical utilization* by
Die thinning                                         emissions; establish
                                                                            10%; characterize process emissions and
                                                     baseline
                                                                                             byproducts
                                                                             Alternatives with improved ESH impacts.
                                                     Characterize
                                                                            Maintain or improve chemical utilization* by
Assembly and packaging wastes                        emissions; establish
                                                                            10%; characterize process emissions and
                                                     baseline
                                                                                             byproducts
                                                                                              Optimize processes and equipment for
                                                                     Characterize
                                                                                            improved ESH impacts. Maintain or improve
Through-silicon via etch using PFCs (e.g., 3D)                       emissions; establish
                                                                                             chemical utilization* by 10%; characterize
                                                                     baseline.
                                                                                                process emissions and byproducts

Emerging Research Materials
                                                                     Conduct ESH risk assessment of materials, processes and
Nanomaterials
                                                                     equipment


                                                                     Conduct ESH risk assessment of materials, processes and
Biological materials and their waste
                                                                     equipment



                                                                     Conduct ESH risk assessment of materials, processes and
Materials for novel logic and memory
                                                                     equipment


New Equipment Design
                                                                      Develop eco-design criteria, establishing metrics and targets for
Eco-design
                                                                              minimized environmental footprint and impact.


Design for Maintenance                                                              Develop safe maintenance criteria.



                                                                         Characterize energy requirements for process and ancillary
Energy Consumption (kWh per cm2) [1]
                                                                                                equipment.




                                                                     Characterize water and utilities requirements for process. Optimize
Water and other utilities (liters or m3 / cm2) [1]                      consumption. Determine feasibility for water recycle/reclaim;
                                                                      reduce water and utilities requirements 15% per technology node




Chemicals (gms/cm2) [1]                                                  Conduct ESH risk assessment of processes and equipment.


Consumables**                                                                         Establish consumables baseline.



Equipment thermal management                                                                 Establish baseline



Design for End-of-Life                                                                                                                Design process and an

* Utilization = [(Feed - Output)/Feed] x 100%
** Consumables = CMP pads, post-CMP brushes, filters, chamber liners, etc. (i.e., items that create solid waste)
       2
[1] cm per wafer out



           Manufacturable solutions exist, and are being optimized
                              Manufacturable solutions are known
                                       Interim solutions are known   
                        Manufacturable solutions are NOT known
Technology Requirements—Near-term Years



                        2010                  2011                  2012                 2013                   2014                   2015




                                                                                   Maintain or improve chemicals utilization* by 10%; characterize
chemical utilization* by 10%; characterize process emissions and byproducts
                                                                                                 process emissions and byproducts




                          Optimize copper processes to reduce consumables and waste by 25%




                                                                                       Maintain or improve chemicals utilization* by 10% and
emical utilization* by 10% and characterize process emissions and byproducts
                                                                                         characterize process emissions and byproducts




    >15% Reduction in consumables from baseline                                           Additional 2% reduction in consumables per year


                                                                                    Additional 2% reduction in water usage for planarization (e.g.,
     >15% Reduction in water usage from baseline
                                                                                                     reduction, re-use, recycle)

                Reduce Global Warming Impact (lower GWP emissions; improved Reduce Global Warming Impact (lower GWP emissions; improved
                utilization*) without increasing ESH risk                   utilization*) without increasing ESH risk


                Reduce Global Warming Impact (lower GWP emissions; improved Reduce Global Warming Impact (lower GWP emissions; improved
                utilization*) without increasing ESH risk                   utilization*) without increasing ESH risk




                                                                                   Additional 2% reduction in chemicals and water usage per year;
5% Reduction in chemicals and water usage from baseline
                                                                                                           recycle/reclaim




                 Reduce Global Warming impact (lower GWP emissions; improved Reduce Global Warming impact (lower GWP emissions; improved
                   utilization*) without increasing ESH risk. Maintain or improve utilization*) without increasing ESH risk. Maintain or improve
                                      chemical utilization by 10%                                    chemical utilization by 10%




                                                       Low-ESH impact deposition, etch, and cleans processes

      Energy efficient deposition processes (process and ancillary equipment); reduce energy requirements by 15%
                                                             Low hazard dopant materials and processes

                           Energy efficient doping processes (process and ancillary equipment)

                 ESH-friendly wafer clean and rinse processes and tools incorporated into manufacturing




                    Maintain or improve chemical and water utilization* by 10%         Maintain or improve chemical and water utilization* by 10%




                                          Energy efficient clean processes (optimized exhaust flow rates, optimized heaters)


                 Novel wafer cleaning technologies evaluated and optimized to
                                                                                   Novel wafer cleaning technologies implemented
                 minimize ESH impact



                 Alternatives with improved ESH impacts. Low ESH impact
                                                                                       Alternatives with improved ESH impacts. Maintain or improve
                 chemistries Maintain or improve chemical utilization* by 10%;
                                                                                      chemical utilization* by 10%; characterize process byproducts.
                 characterize process byproducts.



quipment. Maintain or improve chemical utilization*; characterize process emissions Maintain or improve chemical utilization* by 10% and characterize
        and byproducts                                                              emissions and process byproducts


                 Maintain or improve chemical utilization* by 10% and characterize Maintain or improve chemical utilization* by 10% and characterize
                 process emissions and byproducts                                  process emissions and byproducts




                 Minimal ESH impact from immersion fluids, processes, equipment Minimal ESH impact from immersion fluids, processes, equipment
                                       and consumables                                                and consumables

                 Minimal ESH impact from ionizing radiation and ergonomics; high    Minimal ESH impact from ionizing radiation and ergonomics; high
                                     efficiency EUV source                                              efficiency EUV source

                 Minimal ESH impact from processes, equipment and consumables Minimal ESH impact from processes, equipment and consumables

                      Identify minimal ESH impact cleaning technologies (e.g.,     Novel mask cleaning technologies evaluated and optimized to
                                         supercritical CO2)                        minimize ESH impact




                            Reduce molding compound waste by 50%.                         Zero waste (after recycling) from molding technologies


                    Alternatives with improved ESH impacts. Low ESH impact            Alternatives with improved ESH impacts. Maintain or improve
                   chemistries Maintain or improve chemical utilization* by 10%;    chemical utilization* by 10%; characterize process emissions and
                         characterize process emissions and byproducts                                          byproducts


                    Alternatives with improved ESH impacts. Low ESH impact            Alternatives with improved ESH impacts. Maintain or improve
                   chemistries Maintain or improve chemical utilization* by 10%;    chemical utilization* by 10%; characterize process emissions and
                         characterize process emissions and byproducts                                          byproducts
     Identify alternative processes and equipment with improved ESH Alternative processes and equipment with improved ESH impacts.
        impacts. Maintain or improve chemical utilization* by 10%;    Maintain or improve chemical utilization* by 10%; characterize
               characterize process emissions and byproducts                        process emissions and byproducts




                                   Conduct ESH risk assessment of materials, processes and equipment



                                   Conduct ESH risk assessment of materials, processes and equipment




                                   Conduct ESH risk assessment of materials, processes and equipment




                  Design process and ancillary equipment to minimize environmental footprint, and safety and health impact


              Design equipment so that commonly serviced components and consumable items are easily and safely accessed



       Optimize energy consumption. Add idle capability to ancillary equipment (pumps, etc.); reduce energy requirements by 15% per
                                                             technology node




      Optimize consumption. Determine feasibility for water recycle/reclaim; reduce water and utilities requirements 15% per technology
                                                                     node




    Conduct ESH risk assessment of processes and equipment. Maintain or improve chemical utilization*; characterize process emissions
                               and byproducts; reduce chemical consumption 15% per technology node


                  Optimize to minimize consumables and waste; reduce consumables and waste 15% per technology node


      Reduce heat rejection from process and ancillary equipment to     Reduce heat rejection from process and ancillary equipment to
                  cleanroom air by 15% from baseline                                  cleanroom air by additional 15%


Design process and ancillary equipment for disassembly and re-use/reclaim
Table ESH4b                                                              Process and Equipment Management Technology Requirem

* The Environment, Safety, and Health new chemical screening tool ( Chemical Restrictions Table ) is linked online


Year of Production                                                           2016            2017            2018           2019

Interconnect

Low-k processing spin-on and CVD                                         Maintain or improve chemical utilization* by   Maintain or improve chemic
                                                                         10%; characterize process emissions and         characterize process emiss
                                                                         byproducts
Copper deposition processes (conventional and alternative)               100% copper reclaimed/recycled; optimize copper processes to reduce consu

Advanced metallization including barrier and nucleation deposition        Maintain or improve chemicals utilization* by 10% and characterize process e


Planarization methods                                                                                 Additional 2% reduction in consumables per year

                                                                                     Additional 2% reduction in water for planarization (e.g., reduction,

Plasma etch processes                                                    Reduce Global Warming Impact (lower GWP emissions; improved utilization*)
                                                                         risk
CVD chamber clean (plasma)                                               Reduce Global Warming Impact (lower GWP emissions; improved utilization*)
                                                                         risk
Surface preparation                                                                     2% reduction in chemicals and water usage per year; recycl

3D (wafer thinning, drilling, bonding, metals)                               Alternatives with improved ESH impacts. Maintain or improve chemical u
                                                                                                             characterize process emissions
Through-silicon via etch using PFCs (e.g., 3D)                            Reduce Global Warming impact (lower GWP emissions; improved utilization
                                                                                                  risk. Maintain or improve chemical utilization by 10%
Front End Processes

High-k and metal gate processes                                           Low-ESH impact deposition, etch, and cleans processes; maintain or improv
                                                                                                10% and characterize process emissions and byprodu
                                                                          Energy efficient deposition processes (process and ancillary equipment); red
                                                                                                                    by additional 25%
Doping (implantation and diffusion)                                                                    Low hazard dopant materials and processes

                                                                          Energy efficient deposition processes (process and ancillary equipment); red
                                                                                                                    by additional 25%
Surface preparation (stripping, cleaning, rinsing)                              ESH-friendly wafer clean and rinse processes and tools incorporated
                                                                                                    Maintain or improve chemical and water usage by 10

                                                                          Energy efficient deposition processes (process and ancillary equipment); red
                                                                                                                    by additional 25%
Alternative surface preparation methods                                      Novel wafer cleaning technologies implemented; maintain or improve che

Plasma etch processing                                                   Alternatives with improved ESH impacts. Maintain or improve chemical utiliza
                                                                                                            process emissions and byproducts.
Non-silicon, active substrates (channel)                                 Maintain or improve chemical utilization* by 10% and characterize process em

Novel memory materials                                                   Maintain or improve chemical utilization* by 10% and characterize process em

Lithography

193 nm immersion lithography                                                Minimal ESH impact from immersion fluids, processes, equipment and con
                                                                         improve chemical utilization* by 10% and characterize process byproducts; lo
                                                                                                               solvents, PFAS-free resists.
EUV                                                                      Minimal ESH impact from ionizing radiation, ergonomics, energy consumption
                                                                              or improve chemical utilization* by 10% and characterize process emiss
Imprint                                                                          Minimal ESH impact from processes, equipment and consumables; mainta
                                                                                            utilization* by 10% and characterize process emissions and b

Mask cleaning                                                                 Novel mask cleaning technologies evaluated and optimized to minimize ESH
                                                                               improved ESH impacts (PFAS-free). Maintain or improve chemical utilizatio
                                                                                                             process emissions and byproducts
Assembly and Packaging

Die thinning                                                                 Alternatives with improved ESH impacts. Maintain or improve chemical utiliza
                                                                                                                  process emissions and byproducts
Assembly and packaging wastes                                                Alternatives with improved ESH impacts. Maintain or improve chemical utiliza
                                                                                                                  process emissions and byproducts
Through-silicon via etch using PFCs (e.g., 3D)                                   Alternative processes and equipment with improved ESH impacts. Mainta
                                                                                                utilization* by 10%; characterize process emissions and byp
Emerging Research Materials

Nanomaterials                                                                                 Conduct ESH risk assessment of materials, processes and e

Biological materials and their waste                                                          Conduct ESH risk assessment of materials, processes and e

Materials for novel logic and memory                                                          Conduct ESH risk assessment of materials, processes and e

New Equipment Design

Eco-design                                                                     Design process and ancillary equipment to minimize environmental footprin
                                                                                                                              impact
Design for Maintenance                                                       Design equipment so that commonly serviced components and consumable i
                                                                                                                             accessed
Energy Consumption [1]                                                       Characterize energy requirements for process and ancillary equipment. Optim
                                                                                Add idle capability to ancillary equipment (pumps, etc.); reduce energy req
                                                                                                                         technology node
Water and other utilities [1]                                                Characterize water and utilities requirements for process. Optimize consump
                                                                                  for water recycle/reclaim; reduce water and utilities requirements 15% p

Chemicals [1]                                                                Conduct ESH risk assessment of processes and equipment. Maintain or imp
                                                                              characterize process emissions and byproducts; reduce chemical consump
                                                                                                                           node
Consumables**                                                                 Optimize processes to minimize consumables and waste; reduce consuma
                                                                                                                     technology node

Equipment thermal management                                                  Reduce heat rejection from process and        Reduce heat rejection from
                                                                              ancillary equipment to cleanroom air by         equipment to cleanroom a
                                                                                           additional 15%
Design for End-of-Life                                                                    Design process and ancillary equipment for disassembly and re

* Utilization = [(Feed - Output)/Feed] x 100%
** Consumables = CMP pads, post-CMP brushes, filters, chamber liners, etc. (i.e., items that create solid waste)
       2
[1] cm per wafer out


                 Manufacturable solutions exist, and are being optimized
                                       Manufacturable solutions are known
                                               Interim solutions are known   
                                Manufacturable solutions are NOT known
 ment Technology Requirements—Long-term Years



                        2020            2021              2022



        Maintain or improve chemicals utilization* by 5%;
        characterize process emissions and byproducts

 copper processes to reduce consumables by additional 25%

 by 10% and characterize process emissions and byproducts


 eduction in consumables per year

 r for planarization (e.g., reduction, re-use, recycle)

 P emissions; improved utilization*) without increasing ESH

 P emissions; improved utilization*) without increasing ESH

 s and water usage per year; recycle/reclaim

ts. Maintain or improve chemical utilization* by 10% and
terize process emissions
WP emissions; improved utilization*) without increasing ESH
mprove chemical utilization by 10%


 ans processes; maintain or improve chemical utilization* by
 ze process emissions and byproducts
ocess and ancillary equipment); reduce energy requirements
 by additional 25%
 opant materials and processes

ocess and ancillary equipment); reduce energy requirements
 by additional 25%
 processes and tools incorporated into manufacturing
 e chemical and water usage by 10%

ocess and ancillary equipment); reduce energy requirements
 by additional 25%
plemented; maintain or improve chemical usage by 10%.

Maintain or improve chemical utilization* by 10%; characterize
 emissions and byproducts.
  10% and characterize process emissions and byproducts

  10% and characterize process emissions and byproducts




 ids, processes, equipment and consumables; maintain or
 characterize process byproducts; low-hazard/non-hazardous
ents, PFAS-free resists.
 , ergonomics, energy consumption and source gas; maintain
0% and characterize process emissions and byproducts
quipment and consumables; maintain or improve chemical
aracterize process emissions and byproducts

 ted and optimized to minimize ESH impact; alternatives with
 ntain or improve chemical utilization* by 10%; characterize
  emissions and byproducts


Maintain or improve chemical utilization* by 10%; characterize
 emissions and byproducts
Maintain or improve chemical utilization* by 10%; characterize
 emissions and byproducts
with improved ESH impacts. Maintain or improve chemical
acterize process emissions and byproducts


ment of materials, processes and equipment

ment of materials, processes and equipment

ment of materials, processes and equipment




 to minimize environmental footprint and safety and health
       impact
ced components and consumable items are easily and safely
     accessed
 ess and ancillary equipment. Optimize energy consumption.
nt (pumps, etc.); reduce energy requirements by 15% per
 technology node
nts for process. Optimize consumption. Determine feasibility
ter and utilities requirements 15% per technology node

 es and equipment. Maintain or improve chemical utilization*;
 oducts; reduce chemical consumption 15% per technology
       node
 ables and waste; reduce consumables and waste 15% per
  technology node

        Reduce heat rejection from process and ancillary
         equipment to cleanroom air by additional 15%

 equipment for disassembly and re-use/reclaim
         Table ESH5                                                                    Facilities Energy and Water Optimization Technology Requ

         Year of Production                                                                2007            2008           2009          2010

         Facilities Design
                                                                                       Design facilities to minimize environmental    Meet a recognized standard fo
         Eco-friendly facility design
                                                                                                  footprint and impact                                      facility;
                                                                                        Comprehend and implement potential re-        Meet a recognized standard for
         Design for end-of-life re-use
                                                                                          use scenarios during facility design
         Water
                                                     2                                                      6.5                                         5.4
  IS     Total fab* water consumption (liters/cm ) [1]
                                                                                         Establish      Reduce total consumption
DELETE   Total site water consumption reduction                                                                                       Reduce total consumption addit
                                                                                         baseline       10% from baseline levels
                                             2                                                               8                                           7
         Total UPW consumption (liters/cm ) [1]
  IS     UPW recycled/reclaimed** (% of use)                                                                70                                           75

         Energy (electricity, natural gas, etc.)

  IS     Total fab* energy consumption (% of 2007 baseline)                                                 100                                          85
                                                                                         Establish      Reduce total consumption
DELETE   Total site energy consumption reduction                                                                                      Reduce total consumption addit
                                                                                         baseline       10% from baseline levels
                                                                                                                                      Reduce heat rejection from pro
DELETE   Cleanroom thermal management                                                                Establish baseline               ancillary equipment to cleanroo
                                                                                                                                                 15% from baseline
         Waste
                                                 2                                                          50                                           45
         Non-hazardous solid waste (g per cm ) [1]
                                     2                                                                       6                                           5
         Hazardous waste (g per cm ) [1]
         Air Emissions

                                                                                       Baseline DRE and utilities (exhaust, natural   Maximize DRE while minimizing
         Exhaust and abatement optimization
                                                                                                      gas, etc.).                      consumption by 10% from ba
                                                           2                                                0.1                                         0.08
         Volatile Organic Compounds (VOCs) (g per cm ) [1]
                                                                                       10% absolute reduction from 1995 baseline by 2010 as
         Perfluorocompounds (PFCs)
                                                                                       agreed to by the World Semiconductor Council (WSC)


         Notes for Table ESH5a and b:
         *Fab = manufacturing space + support systems
         **Recycle = Re-use after treatment
         **Reuse = Use in secondary application (without treatment)
         **Reclaim = Extracting a useful component from waste
         [1] cm2 per wafer out


                          Manufacturable solutions exist, and are being optimized
                                                 Manufacturable solutions are known
                                                         Interim solutions are known   
                                         Manufacturable solutions are NOT known
imization Technology Requirements

                   2011            2012          2013          2014             2015        2016           2017           2018          2019



  Meet a recognized standard for designing and rating a reduced environmental impact       Meet a recognized standard for designing and rating a reduced environmental impact fa
                        facility; e.g., LEED, Green Globes, etc.                                                              LEED, Green Globes, etc.
  Meet a recognized standard for reduced environmental impact through building re-use;
                                                                                         Meet a recognized standard for reduced environmental impact through building re-use; e.g
                                    e.g., LEED, etc.


                    5.4                                         4.4                                         3.6                                                 3
                                                                                          Reduce total consumption by additional
  Reduce total consumption additional 10%     Reduce total consumption additional 10%                                                      Reduce total consumption by additiona
                                                                                                          10%
                     7                                           6                                           5                                                 5.5

                    75                                           80                                         85                                                  90



                    85                                           70                                         60                                                  50

  Reduce total consumption additional 10%     Reduce total consumption additional 10%    Reduce total consumption by additional 5%          Reduce total consumption by addition

  Reduce heat rejection from process and       Reduce heat rejection from process and     Reduce heat rejection from process and
                                                                                                                                         Reduce heat rejection from process and
  ancillary equipment to cleanroom air by      ancillary equipment to cleanroom air by    ancillary equipment to cleanroom air by
                                                                                                                                          equipment to cleanroom air by addition
             15% from baseline                              additional 15%                             additional 15%


                    45                                           40                                         30                                                  25

                     5                                           4                                          3.5                                                 3


                                              Maximize DRE while minimizing resource      Maximize DRE while minimizing resource
  Maximize DRE while minimizing resource                                                                                             Maximize DRE while minimizing resource co
                                               consumption by additional 10% from          consumption by additional 10% from
   consumption by 10% from baseline.                                                                                                            additional 10% from baseline
                                                           baseline.                                   baseline
                    0.08                                       0.075                                       0.07                                               0.065

                           Maintain 10% absolute reduction from 1995 baseline                                     Maintain 10% absolute reduction from 1995 baseline
                      2020            2021           2022



ng and rating a reduced environmental impact facility; e.g.,
 D, Green Globes, etc.

nvironmental impact through building re-use; e.g., LEED, etc.



                                3

          Reduce total consumption by additional 10%

                               5.5

                               90



                               50

          Reduce total consumption by additional 5%

        Reduce heat rejection from process and ancillary
         equipment to cleanroom air by additional 15%



                               25

                                3



    Maximize DRE while minimizing resource consumption by
               additional 10% from baseline

                              0.065

solute reduction from 1995 baseline
Table ESH6                                                         Sustainability and Product Stewardship Technology Requirement

Year of Production                                                 2007                2008            2009           2010

Sustainability Metrics
                                                                    Develop eco-design criteria, establishing
Facilities Eco-design                                                  metrics and targets for minimized                                                   D
                                                                      environmental footprint and impact

Carbon footprint                                                   Identify common metrics and establish baseline

                                                                      Develop key environmental performance
Product Eco-design                                                                                                  Reduce KEPIs* 10% from baseline leve
                                                                     indicators (KEPIs)* and establish baseline
Design for ESH
                                                                      Develop key environmental performance
                                                                                                                    Reduce KEPIs* 10% from baseline leve
                                                                     indicators (KEPIs)* and establish baseline
Materials
                                                                                                                                       Early assessment of ES


                                                                                                                    Reduce KEPIs* 10% from baseline leve
                                                                      Develop key environmental performance
Processes                                                            indicators (KEPIs)* and establish baseline
                                                                                                                             Alternative low-ESH impact pro

                                                                                                                                      Early assessment of ES

Improved integration of ESH into factory and equipment design                                                                             Incorporate ESH d

End-of-Life
Ease of decommissioning and decontamination for facility re-        Comprehend and implement potential re-
                                                                                                                               Reduce environmental impa
use/re-claim                                                          use scenarios during facility design
Ease of decommissioning and decontamination for equipment re-
                                                                                                                                                        Des
use/re-claim

*KEPIs = Key Environmental Performance Indicators such as energy and water consumption, product content, human toxicity, ozone depletion, global wa
depletion potential, etc.

** LEED = Leadership in Energy and Environmental Design (a U.S. "Green Building" rating system)




        Manufacturable solutions exist, and are being optimized
                             Manufacturable solutions are known
                                     Interim solutions are known   
                         Manufacturable solutions are NOT known
ardship Technology Requirements

                     2011            2012            2013            2014            2015            2016              2017          2018           2019




                                            Design facilities, process and ancillary equipment to minimize environmental footprint, and safety and health impact


                                                                                            Reduce carbon footprint.


   Reduce KEPIs* 10% from baseline levels               Reduce KEPIs* additional 10%                   Reduce KEPIs* additional 10%                             Reduce KEPIs* additional 10%




   Reduce KEPIs* 10% from baseline levels               Reduce KEPIs* additional 10%                   Reduce KEPIs* additional 10%                             Reduce KEPIs* additional 10%


                      Early assessment of ESH impacts during the very early stages of R&D (when materials are being compared and selected)


   Reduce KEPIs* 10% from baseline levels               Reduce KEPIs* additional 10%                   Reduce KEPIs* additional 10%                             Reduce KEPIs* additional 10%


           Alternative low-ESH impact processes for planarization and deposition                                                     Paradigm shift to additive processing

                     Early assessment of ESH impacts during the very early stages of R&D (when processes are being compared and selected)

                         Incorporate ESH design guidelines, methodology, and criteria into tool and factory design, e.g., LEED**




              Reduce environmental impact through building design for re-use                                           Reduce environmental impact through building design for re-use


                                       Design process and ancillary equipment for disassembly and re-use/reclaim


, human toxicity, ozone depletion, global warming potential, photochemical oxidation potential, resource
                         2020         2021         2022




 ety and health impact




                    Reduce KEPIs* additional 10%




                    Reduce KEPIs* additional 10%




                    Reduce KEPIs* additional 10%


m shift to additive processing




 impact through building design for re-use
                              Table YE1                Definitions for the Different Interface Points
                            POS                   POD                      POC                    POE                   PO
                     Delivery Point of                                Submain or               Entry to
                                          Outlet of Central                                                        Entry
                      Gas/Chemical                                   VMB/VMP Take          Equipment or Sub
                                          Facility System                                                        Process
                         Supplier                                      off Valve              Equipment



                      SEMI Standards      ITRS Factory Integration Facilities Group          ITRS Factory Integration Eq
     Interfaces
                        Focus Area                      Focus Area                                   Group Focus Area



                                                                                                                 Inlet of w
                                                                                                                 bath, spr
                                          Outlet of final                                                        or conne
                                                                    Outlet of submain      Inlet of wet bench
 Ultrapure water     Raw water            filtration in UPW                                                      point to p
                                                                    take off valve         or subequipment
                                          plant                                                                  which is
                                                                                                                 for other
                                                                                                                 chemical


                     Chemical             Outlet of final                                  Inlet of wet bench    Inlet of w
                                                                    Outlet of VMB
 Process chemicals   drum/tote/bulk       filtration of chemical                           or intermediate       bath or s
                                                                    valve
                     supply               distribution unit                                tank                  nozzle

                     Gas cylinder or      Outlet of final
                                                                    Outlet of VMB                                Inlet of c
 Specialty gases     bulk specialty gas   filtration of gas                                Inlet of equipment
                                                                    valve                                        (outlet of
                     systems              cabinet

                     Bulk gas delivered                             Outlet of submain      Inlet of
                                          Outlet of final                                                        Inlet of c
 Bulk gases          on site or gas                                 take off valve or      equipment/
                                          filtration/purification                                                (outlet of
                     generator                                      VMB valve              subequipment

                                                                                           Inlet to mini-
                                                                                           environment or
 Cleanroom and                            Outlet of make-up         Outlet of filters in   sub equipment for     Gas/air i
                     Outside air
 AMC                                      air handling unit         cleanroom ceiling      AMC, outlet of        to wafer/
                                                                                           the tool filter for
                                                                                           particles

       POD—point of delivery POC—point of connection POE—point of entry POU—point of use V
VMP— valve manifold post UPW—ultra pure water MFC—mass flow controller AMC—airborne
SMC—surface molecular contamination
Different Interface Points
                POE                   POU                  POP
r            Entry to
                                 Entry to the          Contact with
ake      Equipment or Sub
                               Process Chamber           Wafer
            Equipment

                                                      ITRS Front End
                                                         Processes,
roup       ITRS Factory Integration Equipment
                                                        Lithography,
                   Group Focus Area
                                                     Interconnect TWG
                                                         Focus Area

                               Inlet of wet bench
                               bath, spray nozzle,
                               or connection
main     Inlet of wet bench                          Wafer in
                               point to piping,
         or subequipment                             production
                               which is also used
                               for other
                               chemicals


         Inlet of wet bench    Inlet of wet bench
B                                                    Wafer in
         or intermediate       bath or spray
                                                     production
         tank                  nozzle


B                              Inlet of chamber      Wafer in
         Inlet of equipment
                               (outlet of MFC)       production

main     Inlet of
                               Inlet of chamber      Wafer in
 or      equipment/
                               (outlet of MFC)       production
         subequipment

         Inlet to mini-
         environment or
                                                     Wafer/substrate in
s in     sub equipment for     Gas/air in vicinity
                                                     production (AMC/
ling     AMC, outlet of        to wafer/substrate
                                                     SMC)
         the tool filter for
         particles

     of entry POU—point of use VMB— valve manifold box
    flow controller AMC—airborne molecular contamination
                                  Table YE2                   Yield Enhancement Difficult Challenges
Difficult Challenges ≥ 22 nm                               Summary of Issues
Detection of multiple killer defect types / signal to      Existing techniques trade-off throughput for sensitivity, but at expected d
noise ratio – The detection of multiple killer defect          throughput and sensitivity are necessary for statistical validity.
types and simultaneous differentiation at high             Reduction of inspection costs and increase of throughput is crucial in view
capture rates, low cost of ownership and throughput
is required. The need of higher sensitivity of in-line     Detection particles at critical size may not exist.
inspections is leading to a dramatic increase of           Detection of line edge roughness due to process variation.
defect counts. It is a challenge to find small but yield
                                                           Electrical and physical failure analysis for killer defects at high capture ra
relevant defects under a vast amount of nuisance
                                                               throughput and high precision.
and false defects.
                                                           Filtering and use of Automatic Defect Classification (ADC) is a potential
                                                                reduction of noise.
                                                           Reduction of background noise from detection units and samples to impro
                                                              sensitivity of systems.
                                                           Improvement of signal to noise ratio to delineate defect from process vari
                                                           Where does process variation stop and defect start?
Wafer edge and bevel control and inspection —              Find a for production suitable inspection of wafer edge, bevel and apex on
Defects and process problems around wafer edge                 and backside.
and wafer bevel are identified to cause yield loss.
Process stability versus absolute contamination        Methodology for employment and correlation of fluid/gas types to yield o
level including the correlation to yield — Test            structure/product
structures, methods, and data are needed for           Relative importance of different contaminants to wafer yield.
correlating process fluid contamination types and
levels to yield and determine required control limits. Define a standard test for yield/parametric effect.
                                                       Definition of maximum process variation (control limits).
Linking systematic yield loss to layout attributes —       SMLY should be efficiently identified and tackled through logic diagnosi
The irregularity of features makes logic areas very           designed into products and systematically incorporated in the test flo
sensitive to Systematic Mechanisms Limited Yield              issues can arise due to: a) Accommodation of different Automatic Te
(SMLY) such as patterning marginalities across the            Generation (ATPG) flows. b) Automatic Test Equipment (ATE) arch
lithographic process window.                                  might lead to significant test time increase when logging the number
                                                              necessary for the logic diagnosis to converge. c) Logic diagnosis run
                                                              Statistical aggregation of diagnosis results for building a layout-depe
                                                              yield model.
                                                           Test pattern generation has to take into account process versus layout mar
                                                               (hotspots) which might cause systematic yield loss, and has to improv
                                                               coverage.
High aspect ratio inspection (HARI) — The                  Poor transmission of energy into bottom of via and back out to detection s
requirement for high-speed and cost-effective high         Rapid detection of defects at ½× Ground Rule (GR) associated with high-
aspect ratio inspection tools remains as the work              contacts, vias, and trenches, and especially defects near or at the bott
around using e-beam inspection does not at all meet            features
requirement for throughput and low cost. Sensitivity
requirements are leading to a dramatic increase of         Large number of contacts and vias per wafer
defect counts. The major challenge is to find the
yield relevant defect types under the vast amount of
defects.
Difficult Challenges < 22 nm                               Summary of Issues
In-line defect characterization and analysis —             The probe for sampling should show minimum impact as surface damage
Alternatives to Energy Dispersive X-ray (EDX)                  from SEM image resolution.
analysis systems are required for in-line defect           It will be recommended to supply information on chemical state and bond
characterization and analysis for defects smaller               organics.
100 nm [1]. The focus has to be on light elements,
small amount of samples due to particle size               Small volume technique adapted to the scales of technology generations.
following the miniaturization, and microanalysis.          Capability to distinguish between the particle and the substrate signal.
Development of model-based design-manufacturing            Development of test structures for new technology generations
interface — Due to Optical Proximity Correction            Address complex integration issues
(OPC) and the high complexity of integration, the
models must comprehend greater parametric                  Model ultra-thin film integrity issues
sensitivities, ultra-thin film integrity, impact of        Improve scaling methods for front-end processes including increased tran
circuit design, greater transistor packing, etc.               density
          [1] Cross-link to Metrology chapter
analysis systems are required for in-line defect      It will be recommended to supply information on chemical state and bond
characterization and analysis for defects smaller          organics.
100 nm [1]. The focus has to be on light elements,
small amount of samples due to particle size          Small volume technique adapted to the scales of technology generations.
following the miniaturization, and microanalysis.     Capability to distinguish between the particle and the substrate signal.
Development of model-based design-manufacturing       Development of test structures for new technology generations
interface — Due to Optical Proximity Correction       Address complex integration issues
(OPC) and the high complexity of integration, the
models must comprehend greater parametric             Model ultra-thin film integrity issues
sensitivities, ultra-thin film integrity, impact of   Improve scaling methods for front-end processes including increased tran
circuit design, greater transistor packing, etc.          density
          [1] Cross-link to Metrology chapter
Difficult Challenges

 oughput for sensitivity, but at expected defect levels, both
 re necessary for statistical validity.
 d increase of throughput is crucial in view of CoO.
 e may not exist.
 s due to process variation.
nalysis for killer defects at high capture rate, high
on.
Defect Classification (ADC) is a potential solution for

 from detection units and samples to improve the

 ratio to delineate defect from process variation.
 op and defect start?
 spection of wafer edge, bevel and apex on the wafer front


 nd correlation of fluid/gas types to yield of a standard test

 contaminants to wafer yield.
parametric effect.
 variation (control limits).
ntified and tackled through logic diagnosis capability
systematically incorporated in the test flow. Potential
ccommodation of different Automatic Test Pattern
b) Automatic Test Equipment (ATE) architecture which
t time increase when logging the number of vectors
nosis to converge. c) Logic diagnosis run time per die. d)
agnosis results for building a layout-dependent systematic

 ke into account process versus layout marginalities
 se systematic yield loss, and has to improve their

o bottom of via and back out to detection system.
  Ground Rule (GR) associated with high-aspect-ratio
  and especially defects near or at the bottoms of these

 as per wafer




 how minimum impact as surface damage or destruction
 .
 y information on chemical state and bonding especially of

d to the scales of technology generations.
 n the particle and the substrate signal.
 or new technology generations
 ues
ssues
 nt-end processes including increased transistor packing
y information on chemical state and bonding especially of

d to the scales of technology generations.
n the particle and the substrate signal.
or new technology generations
ues
ssues
nt-end processes including increased transistor packing
     Table YE3 Defect Budget Technology Requirement Assumptions

           Product             MPU             DRAM             Flash
                                              Volume
      Yield Ramp Phase   Volume Production   Production   Volume Production
     YOVERALL                  75%              85%             85%
     YRANDOM                   83%            89.50%           89.50%
     YSYSTEMATIC               90%              95%             95%
     Ymaterial                >99%             >99%            >99%

IS   Chip Size               140mm2          107mm2           144mm2

     Cluster Parameter           2               2                2
     Table YE4       Yield Model and Defect Budget MPU Technology Requirements

     Year of Production                                  2007           2008            2009             2010             2011
     MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                  68              59              52               45              40
IS   MPU Physical Gate Length (nm)                        32             29               27              24               22

     Critical Defect Size (nm)                            34             30               26              23               20
     Chip Size (mm2) [B]                                 140             111              88              140             111
     Overall Electrical D0 (faults/m2) at Critical
     Defect Size Or Greater [C]                          2210           2210            2210             2210             2210
     Random Electrical D0 (faults/m2) [D]                1395           1395            1395             1395             1395
     Random Faults/Mask                                   42             40               40              40               40
     MPU Random Particles per Wafer pass (PWP) Budget (defects/m2) for Generic Tool Type Scaled to 34 nm Critical Defect Size or Greater
IS                                     CMP insulator     840             600             455              345             274

IS                                 Coat/develop/bake     149             107              81              61               49

IS                                  CVD oxide mask       986             704             534              404             321

IS                                      Furnace CVD      421             301             228              173             137

IS                               Furnace oxide/anneal    245             175             133              100              80

IS                      Implant low/medium current       299             214             162              123              98

IS                                      Inspect visual   328             234             178              135             107

IS                                Lithography stepper    240             172             130              99               78

IS                                      Measure film     245             175             133              100              80

IS                                        Metal CVD      449             321             243              184             146

IS                                         Metal etch    1012            723             548              415             330

IS                                       Plasma etch     919             656             497              377             299

IS                                         RTP CVD       272             195             148              112              89

IS                                               Test     69             49               37              28               22

IS                                    Wafer handling      28             20               15              12               9
                        2012   2013   2014   2015   2016   2017   2018   2019
                        36     32     28     25     22.5   20.0   17.9   15.9
                         20     18    17     15     14.0   12.8   11.7   10.7

                         18     16     14     13    11.3   10.0   8.9    8.0
                         88    140    111     88    140    111     88    140

                        2210   2210   2210   2210   2210   2210   2210   2210
                        1395   1395   1395   1395   1395   1395   1395   1395
                         40     38     38     38     38     36     36     36
efect Size or Greater
                        217    163    129    103     82     61     49     39
                         39     29     23     18     14     11     9      7
                        255    191    152    121     96     72     57     45
                        109     82     65     51     41     31     24     19
                         63     48     38     30     24     18     14     11
                         77     58     46     37     29     22     17     14
                         85     64     51     40     32     24     19     15
                         62     47     37     29     23     18     14     11
                         63     48     38     30     24     18     14     11
                        116     87     69     55     44     33     26     21
                        262    196    156    124     98     74     59     47
                        237    178    142    112     89     67     53     42
                         70     53     42     33     26     20     16     13
                         18     13     11     8      7      5      4      3
                         7      5      4      3      3      2      2      1
2020   2021   2022
14.2   12.6   11.3

9.7    8.9    8.1

7.1    6.3    5.6
111     88    140

2210   2210   2210
1395   1395   1395
 36     36     36


 31     24     19
 5      4      3
 36     29     23
 15     12     10
 9      7      6
 11     9      7
 12     10     8
 9      7      6
 9      7      6
 16     13     10
 37     29     23
 34     27     21
 10     8      6
 3      2      2
 1      1      1
      Table YE5        Yield Model and Defect Budget DRAM/Flash Technology Requirements

      Year of Production                                 2007     2008     2009           2010   2011

IS    DRAM ½ Pitch (nm) (contacted)                       68       59       52             45     40


      Flash ½ Pitch (nm) (un-contacted Poly)(f)           54       45       40             36     32
      Critical Defect Size (nm)                           34       30       26             23     20
      DRAM Product Table
IS    Chip Size (mm2) [B]                                 107      81       61            93      74
      Cell array area at production (% of chip
                                                         56.08%   56.08%   56.08%     56.08%     56.08%
      size) §
      Overall Electrical D0 (faults/m2)
                                                         3606     3606     3606       3606       3606
IS    at critical defect size or greater [C]
IS    Random Electrical D0 (faults/m2) [D]               2430     2430     2430       2430       2430

IS    Random Faults/Mask                                  101      101      101           93      93

IS                                         CMP clean     1157      877      664           465     369

IS                                        CMP metal      1374     1041      789           552     438

IS                                     CVD insulator      991      751      569           398     316

IS                                    Dielectric track    499      379      287           201     159

IS                                  Furnace fast ramp     643      488      370           259     205

IS                                Implant high current    598      453      344           240     191

IS                                       Inspect PLY      781      592      449           314     249

IS                                    Lithography cell    668      506      384           268     213

IS                                       Measure CD       667      506      383           268     213

IS                                   Measure overlay      610      462      350           245     195

IS                                  Metal electroplate    477      361      274           192     152

IS                                        Metal PVD       690      523      396           277     220

IS                                        Plasma strip    942      714      541           379     300

IS                                  RTP oxide/anneal      449      340      258           180     143

IS                                  Vapor phase clean    1308      991      751           525     417

IS                                         Wet bench      934      708      536           375     298
      Chip Size (mm2) [B]                                 144      102      81            128     102
      Non-core Area (mm2)                                 46       32       26            41      32
ADD   Random Electrical D0 (faults/m2) [D]               2503     2503     2503       2503       2503

ADD   Random Faults/Mask                                  74       74       78            78      83
2012     2013      2014     2015     2016     2017     2018     2019

 36       32        28       25      22.5     20.0     17.9     15.9


 28       25        22       20      17.9     15.9     14.2     12.6
 18       16        14       13      11.3     10.0     8.9      8.0


 59       93       74       59       93       74       59       93

56.08%   56.08%   56.08%   56.08%   56.08%   56.08%   56.08%   56.08%

3606     3606     3606     3606     3606     3606     3606     3606

2430     2430     2430     2430     2430     2430     2430     2430
 93       93       93       93       93       93       93       93
 293      232      184      146      116      92       73       58
 348      276      219      174      138      110      87       69
 251      199      158      125      100      79       63       50
 126      100      80       63       50       40       32       25
 163      129      103      81       65       51       41       32
 151      120      95       76       60       48       38       30
 198      157      125      99       78       62       49       39
 169      134      107      85       67       53       42       34
 169      134      106      84       67       53       42       34
 154      123      97       77       61       49       39       31
 121      96       76       60       48       38       30       24
 175      139      110      87       69       55       44       35
 239      189      150      119      95       75       60       47
 114      90       72       57       45       36       28       23
 331      263      209      166      131      104      83       66
 236      188      149      118      94       74       59       47
 81       128      102      81       128      102      81       128
 26       41       32       26       41       32       26       41
2503     2503     2503     2503     2503     2503     2503     2503
 83      72-89    72-89     72       72       72       72       72
 2020     2021     2022

 14.2     12.6     11.3


 11.3     10.0     8.9
 7.1      6.3      5.6


 74       59       93

56.08%   56.08%   56.08%

3606     3606     3606

2430     2430     2430
 93       93       93
 46       37       29
 55       43       35
 40       31       25
 20       16       13
 26       20       16
 24       19       15
 31       25       20
 27       21       17
 27       21       17
 24       19       15
 19       15       12
 27       22       17
 38       30       24
 18       14       11
 52       41       33
 37       30       23
 102      81       128
 32       26       41
2503     2503     2503
 72       72       72
         Table YE6                                                                     Defect Inspection on Patterned Wafer Technology Requirements

         Year of Production                                                                2007     2008              2009            2010           2011            2012           2013            2014
DELETE   Defect coordinate precision [µm]                                                   68       59                 52             45              40             36              32             28
         Flash ½ Pitch (nm) (un-contacted Poly)                                             54       45                 40             36              32             28              25             22
         Patterned Wafer Inspection, PSL Spheres * at 90% Capture, Equivalent Sensitivity (nm) [A, B]
         Process R&D at 300 cm2/hr                                                      27          22,5              20             18              16             14             12.5            11
         (0,4 “300 mm wafer”/hr)
         Process R&D at 300 cm2/hr                                                         16.2    13,5               12            10.8            9.6            8.4             7.5            6.6
  IS     Yield ramp at 1200 cm2/hr                                                         43.2      36                 32            28.8            25.6           22.4            20             17.6
         (1,7 “300 mm wafer”/hr)
         (4,3 “300 mm wafer”/hr)
         Tool matching (% variation tool to tool) [E]                                       10       10                 5              5               5              5               5              5
         Defect coordinate precision [µm]                                                  1.89     1.575              1.4            1.26            1.12           0.98           0.875           0.77
         Cost of ownership ($/cm2)                                                         0.08     0.08               0.08           0.08            0.08           0.08           0.08            0.08


  IS     Sensitivity for voltage contrast application without speed requirement (nm)        65       45                 40             36              32             28              25             22
  IS     Speed for voltage contrast applications [cm2/hr]                                   50       100               100             100            300             300            300             300
         CoO HARI ($/cm2)                                                                  0.388    0.388             0.388           0.388          0.388           0.388          0.388           0.388
         Critical Defect Size (µm) for large defects                                        50       20                20              20             10              10             10              10
         Critical Defect Size (nm) for total defects                                        325      285               250             225            200             175            160             140



                           Manufacturable solutions exist, and are being optimized
                                               Manufacturable solutions are known
                                                        Interim solutions are known    
                                         Manufacturable solutions are NOT known


         Notes for Tables YE6, YE7, YE8 a and b:

                                                                          2                                      2
         [A] Patterned wafer scan speed is required to be at least 300 cm /hour for process R&D mode, 1,200 cm       /hour for yield ramp mode, and, at least, 3,000 cm 2 /hour for volume production mode. Existing solutions do not achieve
         these targets at the above mentioned sensitivity requirement.
[B] Patterned wafer nuisance defect rate shall be lower than 5% in all process phases. False counts in the R&D phase less than 5%, and less than 1% in the yield ramp and volume production phase. Nuisance is defined as an event
indicated and a defect is present, just not the type of interest. These maybe significant and could be studied at a later date. The defect classifier must consider the defect type and assign significance. False is defined at an event is
indicated, but no defect can be seen using the review optics path of the detection tool, which supports recipe setup validation.)

[C] Metric % variation tool-to-tool in number of non-matching defects/total number of defects from standard tool.

Procedure: Recipe sensitivity set on first (standard) tool with false <5. Transfer this recipe without changes and perform ten runs with a wafer containing a minimum of 30 defects.

[D] High Aspect Ration is defined as for contacts 15:1.

[E] HARI defects are already considered “killers” at any process stage, but defined at the contact/via levels for full feature size capture. Hence, minimum defect sensitivity was stipulated as 1.0× technology generation at all stages
of production. Physically uninterrupted coverage of the bottom of a contact by a monolayer of material or more is the model to be detected. If in the future, detection tools can determine size, shape, or remaining material on the
order of 0.3× technology generation, this will more adequately match known experience for resistance changes. Scan speed for HARi tools have been broken out into process verification and volume production types. Process
verification usually refers to SEM-type tools (but not necessarily in the future) and includes voltage contrast capability. The table indicates the approximate number of 200 mm wafers per hour. To obtain the approximate 300 mm
wafers per hour, multiple the wafers/hour rate by .435.

F] Un-patterned wafer defect detection tools will be required to scan 200 (300 mm or equivalent) wafers per hour at nuisance and false defect rates lower than 5%, for each individually.

[G] Must meet haze and crystal originated pit (COP) requirements specified in the Front End Processes chapter Starting Materials section of the Roadmap.

[H] Sensitivity requirement agreed with Lithography TWG. Might need to be revised with implementation of EUV lithography. Optical review capability of backside results is a requirement.

[I] Resolution of defect review is defined as 0.05 × Sensitivity at pattern inspection R&D.

[J] Driver is the defect size.

[K] Assumptions: 5,000 wafer starts per week, defects per wafer based on surface preparation at front end of line (FEOL), leading to defects per hour that need review, 100% ADC.

[L] Defect classifications need to meet: Repeatability 95 %, Accuracy 90 %, Purity 90 %.

[M] Defect classifications need to meet: Repeatability 95 %, Accuracy 80 %, Purity 80 %.

[N] Review capability: optical review capability at the tool but also offline SEM review is necessary.

[O] An industry standard result file is needed also for SEM review capability. Result file containing coordinate and angular information to also allow prior level subtraction, also add images from tool in result file.

[P] The first three ADC classes to start with: chips, surface particle large, surface particle small. The fourth ADC class should be blisters.

[Q] 50 % capture rate is calculated with 10 scans

[R] Speed is considered the time needed for full wafer scan including load and unload

[S] Redetection at minimum defect size at a minimum capture rate of 50 %
[T] Speed is considered the time needed including load and unload for review of 2 wafer / lot and 50 defects / wafer

[U] Inspection of full and partial printed chips, as well as chip free area. A size binning of defects is necessary
                       2015           2016         2017    2018    2019    2020    2021    2022
                        25            22.5         20.0    17.9    15.9    14.2    12.6    11.3
                        20             18           16      14      13      11      10      9

                        10
                                        9            8       7      6.5     5.5     5       4.5
                        6              5.4          4.8     4.2     3.9     3.3     3       2.7
                        16                                                                         change in colors
                                      14.4         12.8    11.2    10.4     8.8     8       7.2

                        5              5            5       5       5        5      5        5
                       0.7            0.7          0.63    0.56    0.49    0.455   0.35    0.315
                       0.08           0.08         0.08    0.08    0.08    0.08    0.08     0.08

                        20             18           16      14      13      11      10      9      change in colors
                       500             500         500     500     500     500     500     500     change in text
                      0.388           0.388        0.388   0.388   0.388   0.388   0.388   0.388
                       10              10           10      10      10      10      10      10
                       125             110          100     100     100     100     100     100




oduction mode. Existing solutions do not achieve
production phase. Nuisance is defined as an event
 ssign significance. False is defined at an event is




 lated as 1.0× technology generation at all stages
 ermine size, shape, or remaining material on the
erification and volume production types. Process
 ers per hour. To obtain the approximate 300 mm


ally.



rement.




d images from tool in result file.
         Table YE7                                                                     Defect Inspection on Unpatterned Wafers, Macro, and Bevel Inspection Technology Requirements

         Year of Production                                                                2007         2008   2009       2010       2011       2012      2013       2014
DELETE   DRAM ½ Pitch (nm) (contacted)                                                     68           59      52         45         40         36        32         28
         Flash ½ Pitch (nm) (un-contacted Poly)(f)                                          54           45     40         36         32         28        25         22
DELETE   Patterned Wafer Inspection, PSL Spheres * at 90% Capture, Equivalent Sensitivity (nm) [A, B]
 ADD     Unpatterned Wafer Inspection, PSL Spheres at 90% Capture, Equivalent Sensitivity (nm) [A, B]
  IS     Films (like Poly Si and metal films )                                             64.8    54          48        43.2       38.4       33.6       30        26.4
         Bare silicon                                                                      28.5    25,5        20         18         16         14        12.5       11
  IS     Throughput at highest sensitivity for all layers [wfr/hrs]                         60    70           70         80         80         90        90         100
         Back surface particle diameter: (nm) [C]                                                       120     100       100        100        100        75         75
         Wafer edge exclusion (mm)                                                          2            2       2         2          2          2         2          2
         PSL spheres at 90% capture rate, Equivalent sensitivity (nm) [E]
         Sensitivity[nm] at 100 wafer/hrs                                                               2000   1400       1260       1120       980        875        770
         Coordinate accuracy [nm]                                                          2250     2000       1800       1600       1400       1250      1100       1000
         CoO [$/300 mm wafer]                                                               1     0,9          0.8        0.8        0.8        0.8       0.8        0.8
         Edge line measurement f.e. EBR
         Number of measured points                                                                      360     360       360        360        360        360        360
         Macro Inspection on product wafer, PSL Spheres * at 90% Capture, Equivalent Sensitivity (µm)
         speed [w/hrs] at sensitivity                                                150              150       150       170        170        170        170        200
         Tool matching (% variation tool to tool) [G]                                 10              10        10        10         10         10         10         10
         Critical Defect Size (µm) for large defects                                  50              20        20        20         10         10         10         10
         Critical Defect Size (nm) for total defects                                 325              285       250       225        200        175        160        140



                           Manufacturable solutions exist, and are being optimized
                                                 Manufacturable solutions are known
                                                         Interim solutions are known   
                                          Manufacturable solutions are NOT known


         Notes for Tables YE6, YE7, YE8 a and b:
                                                                   2                                          2
[A] Patterned wafer scan speed is required to be at least 300 cm /hour for process R&D mode, 1,200 cm             /hour for yield ramp mode, and, at least, 3,000 cm 2 /hour for volume production mode. Existing solutions do not achieve
these targets at the above mentioned sensitivity requirement.


[B] Patterned wafer nuisance defect rate shall be lower than 5% in all process phases. False counts in the R&D phase less than 5%, and less than 1% in the yield ramp and volume production phase. Nuisance is defined as an event
indicated and a defect is present, just not the type of interest. These maybe significant and could be studied at a later date. The defect classifier must consider the defect type and assign significance. False is defined at an event is
indicated, but no defect can be seen using the review optics path of the detection tool, which supports recipe setup validation.)

[C] Metric % variation tool-to-tool in number of non-matching defects/total number of defects from standard tool.

Procedure: Recipe sensitivity set on first (standard) tool with false <5. Transfer this recipe without changes and perform ten runs with a wafer containing a minimum of 30 defects.

[D] High Aspect Ration is defined as for contacts 15:1.

[E] HARI defects are already considered “killers” at any process stage, but defined at the contact/via levels for full feature size capture. Hence, minimum defect sensitivity was stipulated as 1.0× technology generation at all stages
of production. Physically uninterrupted coverage of the bottom of a contact by a monolayer of material or more is the model to be detected. If in the future, detection tools can determine size, shape, or remaining material on the
order of 0.3× technology generation, this will more adequately match known experience for resistance changes. Scan speed for HARi tools have been broken out into process verification and volume production types. Process
verification usually refers to SEM-type tools (but not necessarily in the future) and includes voltage contrast capability. The table indicates the approximate number of 200 mm wafers per hour. To obtain the approximate 300 mm
wafers per hour, multiple the wafers/hour rate by .435.

F] Un-patterned wafer defect detection tools will be required to scan 200 (300 mm or equivalent) wafers per hour at nuisance and false defect rates lower than 5%, for each individually.

[G] Must meet haze and crystal originated pit (COP) requirements specified in the Front End Processes chapter Starting Materials section of the Roadmap.

[H] Sensitivity requirement agreed with Lithography TWG. Might need to be revised with implementation of EUV lithography. Optical review capability of backside results is a requirement.

[I] Resolution of defect review is defined as 0.05 × Sensitivity at pattern inspection R&D.

[J] Driver is the defect size.

[K] Assumptions: 5,000 wafer starts per week, defects per wafer based on surface preparation at front end of line (FEOL), leading to defects per hour that need review, 100% ADC.

[L] Defect classifications need to meet: Repeatability 95 %, Accuracy 90 %, Purity 90 %.

[M] Defect classifications need to meet: Repeatability 95 %, Accuracy 80 %, Purity 80 %.

[N] Review capability: optical review capability at the tool but also offline SEM review is necessary.

[O] An industry standard result file is needed also for SEM review capability. Result file containing coordinate and angular information to also allow prior level subtraction, also add images from tool in result file.

[P] The first three ADC classes to start with: chips, surface particle large, surface particle small. The fourth ADC class should be blisters.

[Q] 50 % capture rate is calculated with 10 scans
[R] Speed is considered the time needed for full wafer scan including load and unload

[S] Redetection at minimum defect size at a minimum capture rate of 50 %

[T] Speed is considered the time needed including load and unload for review of 2 wafer / lot and 50 defects / wafer

[U] Inspection of full and partial printed chips, as well as chip free area. A size binning of defects is necessary
nology Requirements

                2015   2016   2017   2018   2019   2020   2021   2022
                 25    22.5   20.0   17.9   15.9   14.2   12.6   11.3
                 20     18     16     14     13     11     10     9



                 24    21.6   19.2   16.8   15.6   13.2   12     10.8   color change
                 10     10     9      8      7     6.5     5     4.5    color change
                100    110    110    120    120    130    130    130    color change
                 75     50     50     50     50     50     50     50    change of numbers
                 2      2      2      2      2      2       2     2
                                                                        change of text
                 700   630    560    490    455    385    350    315    change in numbers
                 900   800    700    650    550    500    450
                 0.7   0.7    0.7    0.7    0.7    0.7    0.7    0.7    change in colors

                360    360    360    360    360    360    360    360

                200    200    200    200    200    200    200    200
                10     10     10     10     10     10     10     10
                10     10     10     10     10     10      10     10
                125    110    100    100    100    100    100    100
 oduction mode. Existing solutions do not achieve



production phase. Nuisance is defined as an event
 ssign significance. False is defined at an event is




 lated as 1.0× technology generation at all stages
 ermine size, shape, or remaining material on the
erification and volume production types. Process
 ers per hour. To obtain the approximate 300 mm


ally.



 ement.




d images from tool in result file.
         Table YE8                                                                   Defect Review and Automated Defect Classification Technology Requirements

         Year of Production                                                              2007      2008               2009            2010           2011            2012           2013            2014
DELETE   DRAM ½ Pitch (nm) (contacted)                                                   68        59                  52              45             40              36             32              28
         Flash ½ Pitch (nm) (un-contacted Poly)                                           54        45                 40              36             32              28             25              22
         Defect Review (Patterned Wafer)
  IS     Coordinate accuracy (nm) at resolution [A]                                                450                 400            360             320            280             250             220
  IS     Redetection: minimum defect size (nm) [E]                                                 18                  16             14.4            12.8           11.2             10             8.8
         Number of defect types [B]                                                      10        10                  10              10             10              10             10              10
         Speed w/elemental (defects/hours)                                               360       360                360             360            360             360            360             360
         Number of defect types (inline ADC) [C]                                         10        10                  10              10             10              10             10              10
         Coordinate accuracy (nm) at resolution [A]                                      3250      2850               2500            2250           2000            1750           1600            1400
         Number of defect types [B]                                                       5         5                  10              10              10             10              10             10
         Speed w/elemental (defects/hours)                                               360       360                 360            360             360            360             360             360
         Coverage of bevel-zone areas (non destructive)                              3              3                   4               4              5               5              5               5
         Optical review on bevel edge : top and bottom bevel, APEX and 5 mm wafer edge exclusion
         Redetection: minimum defect size (nm) [E]                                   75             75                 100            100             125            125             125             125
         Imaging: maximum magnification [F]                                              600       700                 800            900            1000            1100           1200            1300
         Speed (defects/hours) w ADC [D]                                                           1500               1500            1500           1500            1500           1500            1500
         Resolution [um]                                                                  1         1                   1              0.8            0.8             0.4            0.4             0.2



                           Manufacturable solutions exist, and are being optimized
                                              Manufacturable solutions are known
                                                      Interim solutions are known    
                                        Manufacturable solutions are NOT known



         Notes for Tables YE6, YE7, YE8 a and b:
                                                                          2                                      2
         [A] Patterned wafer scan speed is required to be at least 300 cm /hour for process R&D mode, 1,200 cm       /hour for yield ramp mode, and, at least, 3,000 cm 2 /hour for volume production mode. Existing solutions do not achieve
         these targets at the above mentioned sensitivity requirement.
[B] Patterned wafer nuisance defect rate shall be lower than 5% in all process phases. False counts in the R&D phase less than 5%, and less than 1% in the yield ramp and volume production phase. Nuisance is defined as an
event indicated and a defect is present, just not the type of interest. These maybe significant and could be studied at a later date. The defect classifier must consider the defect type and assign significance. False is defined at an
event is indicated, but no defect can be seen using the review optics path of the detection tool, which supports recipe setup validation.)

[C] Metric % variation tool-to-tool in number of non-matching defects/total number of defects from standard tool.

Procedure: Recipe sensitivity set on first (standard) tool with false <5. Transfer this recipe without changes and perform ten runs with a wafer containing a minimum of 30 defects.

[D] High Aspect Ration is defined as for contacts 15:1.

[E] HARI defects are already considered “killers” at any process stage, but defined at the contact/via levels for full feature size capture. Hence, minimum defect sensitivity was stipulated as 1.0× technology generation at all stages
of production. Physically uninterrupted coverage of the bottom of a contact by a monolayer of material or more is the model to be detected. If in the future, detection tools can determine size, shape, or remaining material on the
order of 0.3× technology generation, this will more adequately match known experience for resistance changes. Scan speed for HARi tools have been broken out into process verification and volume production types. Process
verification usually refers to SEM-type tools (but not necessarily in the future) and includes voltage contrast capability. The table indicates the approximate number of 200 mm wafers per hour. To obtain the approximate 300 mm
wafers per hour, multiple the wafers/hour rate by .435.

F] Un-patterned wafer defect detection tools will be required to scan 200 (300 mm or equivalent) wafers per hour at nuisance and false defect rates lower than 5%, for each individually.

[G] Must meet haze and crystal originated pit (COP) requirements specified in the Front End Processes chapter Starting Materials section of the Roadmap.

[H] Sensitivity requirement agreed with Lithography TWG. Might need to be revised with implementation of EUV lithography. Optical review capability of backside results is a requirement.

[I] Resolution of defect review is defined as 0.05 × Sensitivity at pattern inspection R&D.

[J] Driver is the defect size.

[K] Assumptions: 5,000 wafer starts per week, defects per wafer based on surface preparation at front end of line (FEOL), leading to defects per hour that need review, 100% ADC.

[L] Defect classifications need to meet: Repeatability 95 %, Accuracy 90 %, Purity 90 %.

[M] Defect classifications need to meet: Repeatability 95 %, Accuracy 80 %, Purity 80 %.

[N] Review capability: optical review capability at the tool but also offline SEM review is necessary.

[O] An industry standard result file is needed also for SEM review capability. Result file containing coordinate and angular information to also allow prior level subtraction, also add images from tool in result file.

[P] The first three ADC classes to start with: chips, surface particle large, surface particle small. The fourth ADC class should be blisters.

[Q] 50 % capture rate is calculated with 10 scans

[R] Speed is considered the time needed for full wafer scan including load and unload

[S] Redetection at minimum defect size at a minimum capture rate of 50 %

[T] Speed is considered the time needed including load and unload for review of 2 wafer / lot and 50 defects / wafer
[U] Inspection of full and partial printed chips, as well as chip free area. A size binning of defects is necessary
                       2015           2016         2017   2018   2019   2020   2021   2022
                        25            22.5         20.0   17.9   15.9   14.2   12.6   11.3
                        20             18           16     14     13     11     10     9


                       200             180         160    140    130    110    100     90    change in numbers
                         8             7.2         6.4    5.6    5.2    4.4     4     3.6    change in numbers
                        10             10           10    10     10     10     10     10
                       360             360         360    360    360    360    360    360
                        10             10           10    10     10     10     10     10
                       1250           1100         1000   900    800    700    650    550
                        10             10           10     10     10     10     10     10
                       360             360         360    360    360    360    360    360
                         5              5           5      5      5      5      5      5

                       125             125         125    125    125    125    125    125
                       1400           8000         8000   8000   8000   8000   8000   8000
                       1500           1500         1500   1500   1500   1500   1500   1500
                        0.2            0.2         0.2    0.2    0.2    0.15   0.15   0.15




oduction mode. Existing solutions do not achieve
ume production phase. Nuisance is defined as an
pe and assign significance. False is defined at an




 lated as 1.0× technology generation at all stages
 ermine size, shape, or remaining material on the
erification and volume production types. Process
 ers per hour. To obtain the approximate 300 mm


ually.



irement.




dd images from tool in result file.
ITRS




         Table YE9 Technology Requirements for Wafer Environmental Contamination Control

         Year of Production                                              2007          2008            2009             2010              2011      2012      2013      2014      2015      2016      2017      2018      2019      2020      2021      2022

         Flash ½ Pitch (nm) (un-contacted Poly)(f)                        54            45               40              36                32        28        25        23        20        18        16        14        13        11        10        9
         DRAM ½ Pitch (nm) (contacted)                                    65            57               50              45                40        36        32        28        25        23        20        18        16        14        13        11
         MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                               68            59               52              45                40        36        32        28        25        23        20        18        16        14        13        11
         MPU Printed Gate Length (nm) ††                                  42            38               34              30                27        24        21        19        17        15        13        12        11        9         8         8
         MPU Physical Gate Length (nm)                                    25            23               20              18                16        14        13        11        10        9         8         7         6         6         5         4
         Wafer Environment Control such as Cleanroom, SMIF POD, FOUP, etc….not necessarily the cleanroom itself but wafer environment.
Add      Critical particle size (nm) [1]                                  32.5         28.3              25             22.5               20       17.9      15.9      14.2      12.6      11.3       10        8.9        8        7.1       6.3       5.6
                                  3                                     ISO CL 2     ISO CL 2        ISO CL 2         ISO CL1            ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1   ISO CL1
         Number of particles (/m ) [1] [2]
         Airborne Molecular Contaminants in Gas Phase (pptV V for Volume)) [3, 7, 12,13,14,15,33].
         Lithography (cleanroom ambient) [23]
         Total Inorganic Acids                                           5000          5000            5000             5000              5000      5000      5000      5000      5000      5000      5000      5000      5000      5000      5000      5000
         Total Organic Acids [30]                                        TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         Total bases                                                    50,000        50,000          50,000           50,000            50,000    50,000    50,000    50,000    50,000    50,000    50,000    50,000    50,000    50,000    50,000    50,000
         Condensable organics (w/ GCMS retention times ≥
                                                                         26000         26000           26000           26000             26000     26000     26000     26000     26000     26000     26000     26000     26000     26000     26000     26000
         benzene, calibrated to hexadecane) [31]

         Refractory compounds (organics containing S, P, Si)              100           100             100             100               100       100       100        100      100       100       100       100       100       100       100       100

         SMC (surface molecular condensable) refractory
                                                                           2             2               2                2                 2         2         2         2         2         2         2         2         2         2         2         2
         compounds on wafers, ng/cm2/day [12]
         Gate/Furnace area wafer environment (cleanroom/POD/FOUP ambient)
         Total metals [8]                                                  1             1               1               0.5               0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5
         Dopants [4] (front end of line only)                             10            10               10              10                10        10        10        10        10        10        10        10        10        10        10        10
         SMC (surface molecular condensable) organics on wafers,
                                                                           2             2               2               0.5               0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5
         ng/cm2/day [12]
         Salicidation Wafer Environment (Cleanroom/POD/FOUP ambient)
         Total Inorganic Acids                                            100           100             100              10                10        10        10        10        10        10        10        10        10        10        10        10
         Total Organic Acids [30]                                        TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         Exposed Copper Wafer Environment (Cleanroom/POD/FOUP ambient)
         Total Inorganic Acids                                            500           500             500             500               500       500       500        500      500       500       500       500       500       500       500       500
         Total Organic Acids [30]                                        TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         Total other corrosive species [32]                              1000          1000            1000             1000              1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000
ADD      H2S                                                             1000          1000            1000             1000              1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000
ADD      Total sulphur compounds                                         10000         10000           10000           10000             10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000
         Exposed Aluminum Wafer Environment (Cleanroom/POD/FOUP ambient)
         Total Inorganic Acids                                            500           500             500             500               500       500       500        500      500       500       500       500       500       500       500       500
         Total Organic Acids [30]                                        TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         Total other corrosive species [32]                              1000          1000            1000             1000              1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000
         Reticle Exposure (Cleanroom/POD/Box ambient)
         Total Inorganic Acids                                            500           500             500             TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         Total Organic Acids [30]                                        TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         Total bases                                                     2500          2500            2500             TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         SMC (surface molecular condensable) organics on wafers,
                                                                           2             2               2               0.5               0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5       0.5
         ng/cm2/week [12]
ADD      Critical metrology (cleanroom ambient) [23]
ADD      Total Inorganic Acids                                           5000          5000            5000             5000              5000      5000      5000      5000      5000      5000      5000      5000      5000      5000      5000      5000
ADD      Total Organic Acids [30]                                        TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
ADD      Total bases                                                     50000         50000           50000           50000             50000     50000     50000     50000     50000     50000     50000     50000     50000     50000     50000     50000
         Condensable organics (w/ GCMS retention times ≥
ADD                                                                      26000         26000           26000           26000             26000     26000     26000     26000     26000     26000     26000     26000     26000     26000     26000     26000
         benzene, calibrated to hexadecane) [31]

ADD      Refractory compounds (organics containing S, P, Si)              100           100             100             100               100       100       100        100      100       100       100       100       100       100       100       100

         SMC (surface molecular condensable) refractory
ADD                                                                        2             2               2                2                 2         2         2         2         2         2         2         2         2         2         2         2
         compounds on wafers, ng/cm2/day [12]
ADD      Critical areas (Litho, Metrology)
         Temperature range in +/-K at POE [37]                            1.0           1.0             1.0              1.0               1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0
         Maximum short term temperature variation at POE in +/-
                                                                          1.0           1.0             1.0              1.0               1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0
         K/5 min [37]
         Maximum long term temperature variation in +/-K/hour at
                                                                          1.0           1.0             1.0              1.0               1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0       1.0
         POE [37]

WAS      Humidity range in +/- % relative humdity r.H. at POE [37]        3.0           3.0             3.0              3.0               3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0

         Humidity range in +/- % relative humidity r.H. at POE
 IS                                                                       3.0           3.0             3.0              3.0               3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0       3.0
         [37]
         Maximum short term humidity variation in +/-r.H./5 min at
                                                                          2.0           2.0             2.0              2.0               2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0
         POE [37]
         Non-critical areas (others than Litho, Metrology)
         Temperature range on +/-K at POE [37]                            2.0           2.0             2.0              2.0               2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0       2.0

WAS      Humidity range in +/- % relative humdity r.H. at POE [37]        5.0           5.0             5.0              5.0               5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0

         Humidity range in +/- % relative humidity r.H. at POE
 IS                                                                       5.0           5.0             5.0              5.0               5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0       5.0
         [37]
         Process Critical Materials [5,7]
         Ultrapure Water [29]
         Resistivity at 25°C (MOhm-cm)                                    18.2         18.2             18.2            18.2              18.2      18.2      18.2      18.2      18.2      18.2      18.2      18.2      18.2      18.2      18.2      18.2
         Total oxidizable carbon (ppb) [22]                               <1            <1               <1              <1                <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1
ADD      Critical Organics as C (ppb) [41]                               TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         Bacteria (CFU/liter) [38]                                        <1            <1               <1              <1                <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1
         Total silica (ppb) as SiO2 [18]                                  <0.5         <0.5             <0.5            <0.5              <0.3      <0.3      <0.3      <0.3      <0.3      <0.3      <0.3      <0.3      <0.3      <0.3      <0.3      <0.3
WAS      Number of particles > 0.05 µm (/ml) [26]                         <0.9         <0.9            < 0.3            < 0.3             < 0.3     < 0.2     < 0.2     < 0.2     < 0.1     < 0.1     < 0.1    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03
         Number of particles >critical particle size (see above)
 IS
         (#/L) [26]
                                                                          100           100             100             100               100       300       200        200      200       200       200       200       200       200       200       200      Updated
         Dissolved oxygen (ppb) (contaminant based) [16] POE              <10           <10             <10             <10               <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10

         Dissolved nitrogen (ppm) [10]                                   8–12          8–18            8–18             8–18              8–18      8–18      8–18      8–18      8–18      8–18      8–18      8–18      8–18      8–18      8–18      8–18
         Critical metals (ppt, each) [6]                                  <1.0         <1.0             <1.0            <1.0              <1.0      <1.0      <1.0      <1.0      <1.0      <1.0      <1.0      <1.0      <1.0      <1.0      <1.0      <1.0
         Other critical ions (ppt each) [24]                              <50           <50             <50             <50               <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50
ADD      Boron (ppt) [24]                                                 <50           <50             <50             <50               <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50
         Temperature stability (K)                                        ±1            1              1               1                1        1        1        1        1        1        1        1        1        1               
         Temperature gradient in K/10 minutes [22] for immersion
                                                                          <0.1         <0.1             <0.1            <0.1              <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1
         photolithography
         Liquid Chemicals

         49% HF: number of particles/ml >0.065um [1] [11]                 10             4               4                4                 3         3         3         1         1         1        0.5       0.5       0.5       0.5       0.5       0.5

ADD      49% HF: number of particles/ml >critical particle size           80            50               70             100               100       140       200        100      140       190       140       190       270       380       550       780

         37% HCl: number of particles/ml >0.065um [1] [11]                10             4               4                4                 3         3         3         1         1         1        0.5       0.5       0.5       0.5       0.5       0.5

ADD      37% HCl: number of particles/ml >critical particle size          80            50               70             100               100       140       200        100      140       190       140       190       270       380       550       780

WAS      30% H2O2: number of particles/ml >0.065um [1] [11]              1000           400             400             400               300       300       300        100      100       100        50        50        50        50        50        50

 IS      30% H2O2: number of particles/ml >0.065um [1] [11]               10             4               4                4                 3         3         3         1         1         1        0.5       0.5       0.5       0.5       0.5       0.5

ADD      30% H2O2: number of particles/ml >critical particle size         80            50               70             100               100       140       200        100      140       190       140       190       270       380       550       780

         29% NH4OH: number of particles/ml >0.065um [1] [11]             1000           400             400             400               300       300       300        100      100       100        50        50        50        50        50        50

ADD      29% NH4OH: number of particles/ml >critical particle size       8000          5000            7000            10000             10000     14000     20000     10000     14000     19000     14000     19000     27000     38000     55000     78000

         100% IPA: number of particles/ml >0.065um [1] [11]              1000           400             400             400               300       300       300        100      100       100        50        50        50        50        50        50

ADD      100% IPA: number of particles/ml >critical particle size        8000          5000            7000            10000             10000     14000     20000     10000     14000     19000     14000     19000     27000     38000     55000     78000

ADD      Ethylene glycol: number of particles/ml >0.065um [1] [11]        10             4               4                4                 3         3         3         1         1         1        0.5       0.5       0.5       0.5       0.5       0.5

ADD      EG: number of particles/ml >critical particle size               80            50               70             100               100       140       200        100      140       190       140       190       270       380       550       780
         49% HF: Na, K, Fe, Ni, Cu, Cr, Co, Ca, (Ag, Au, Pd, Pt,
                                                                          150           150             150             150               150       150       150        150      150       150       150       150       150       150       150       150
         Ru, Mo) (ppt, each) [21]
         49% HF: Cl (ppt)                                                10000         10000           10000           10000             10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000
         30% H2O2: Al, Na, K, Fe, Ni, Cu, Cr, Co, Ca, (Ag, Au, Ba,
         Cd, Mg, Mn, Mo, Pb, Pd, Pt, Ru, Sn, Ti, V, W, Zn) (ppt,          150           150             150             150               150       150       150        150      150       150       150       150       150       150       150       150
         each) [21]
         30% H2O2: SiO2 (ppt) [27]                                       5000          5000            5000             5000              5000      5000      5000      5000      5000      5000      5000      5000      5000      5000      5000      5000
         29% NH4OH: Al, Na, K, Fe, Ni, Cu, Cr, Co, Ca, (Au, Ba,
         Cd, Mg, Mn, Mo, Pb, Pd, Pt, Ru, Sn, Ti, V, W, Zn) (ppt,          150           150             150             150               150       150       150        150      150       150       150       150       150       150       150       150
         each) [21]

         100% IPA: Na, K, Fe, Ni, Cu, Cr, Co, Ca (ppt, each) [28]         150           150             150             150               150       150       150        150      150       150       150       150       150       150       150       150

         100% IPA: Cl (ppt) [28]                                        100000        100000          100000          100000             100000    100000    100000    100000    100000    100000    100000    100000    100000    100000    100000    100000
         100% IPA: Br (ppt) [28]                                        100000        100000          100000          100000             100000    100000    100000    100000    100000    100000    100000    100000    100000    100000    100000    100000
         100% IPA: F (ppt) [28]                                         100000        100000          100000          100000             100000    100000    100000    100000    100000    100000    100000    100000    100000    100000    100000    100000
         49% HF: All other metals not listed in row above (ppt,
                                                                          500           500             500             500               500       500       500        500      500       500       500       500       500       500       500       500
         each) [20]
         30% H2O2: All other metals not listed in row above (ppt,
                                                                          500           500             500             500               500       500       500        500      500       500       500       500       500       500       500       500
         each) [21]
         29% NH4OH: all other metals not listed in row above (ppt,
                                                                          500           500             500             500               500       500       500        500      500       500       500       500       500       500       500       500
         each) [21]
         100% IPA: all other metals not listed in row above (ppt,
                                                                          500           500             500             500               500       500       500        500      500       500       500       500       500       500       500       500
         each) [21]
WAS      30% H2O2: total oxidizable carbon (ppb)                         TBD           TBD             TBD              TBD               TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD


6c401391-7dff-4f12-b68c-5db004ffe385.xls,2008_YE9             117/167
ITRS


         Year of Production                                                 2007      2008      2009      2010      2011      2012      2013      2014      2015      2016      2017      2018      2019      2020      2021      2022

         Flash ½ Pitch (nm) (un-contacted Poly)(f)                           54        45        40        36        32        28        25        23        20        18        16        14        13        11        10        9
         DRAM ½ Pitch (nm) (contacted)                                       65        57        50        45        40        36        32        28        25        23        20        18        16        14        13        11
         MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                  68        59        52        45        40        36        32        28        25        23        20        18        16        14        13        11
 IS      30% H2O2: total oxidizable carbon (ppb)                           20000     20000     20000     20000     20000     20000     20000     20000     20000     20000     20000     20000     20000     20000     20000     20000
         100% IPA – Specific organic acids: formate, acetate,
                                                                            TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         citrate, proprionate, oxalate (ppt, each)
WAS      IPA: High molecular weight organics (ppb)                          TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD      Remark deleted
 IS      IPA: High molecular weight organics (ppb)                          500       500       500       500       500       500       500       500       500       500       500       500       500       500       500       500
WAS      30%H2O2: resin byproducts (ppb)                                    TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD

 IS      30%H2O2: resin byproducts (ppb) e.g. total amines [39]              5         5         5         5         5         5         5         5         5         5         5         5         5         5         5         5       Remark deleted
         37% HCl: K, Ni, Cu, Cr, Co, (ppt, each)                            1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000
         96% H2SO4: K, Ni, Cu, Cr, Co, (ppt, each)                          1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000
         37% HCl: all other metals not listed in row above (ppt,
                                                                           10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000
         each) [20]
         96% H2SO4: all other metals not listed in row above (ppt,
                                                                           10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000
         each) [20]
         Ethylene glycol: Critical ions (Cu, Au, Ag, Pt, Pt, Mo, Ru)
ADD
         (ppt each)
                                                                            500       500       500       500       500       500       500       500       500       500       500       500       500       500       500       500      Remark deleted
ADD      Ethylene glycol: Other metal (ppt each)                            1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000     Remark deleted
WAS      BEOL solvents, strippers K, Li, Na, (ppt, each)                   10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000
         BEOL solvents, strippers K, Li, Na, other metals, (ppt,
 IS                                                                        10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000     10000
         each)
         CMP slurries: scratching particles (/ml > key particle size)
                                                                            TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         [9] [17]
         Post-CMP clean chemicals: particles>critical size (/ml) [1]
WAS                                                                         TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD
         [9] [17]
         Post-CMP clean chemicals: particles >0.065 (/ml)
 IS
         [1] [9] [17]
                                                                           < 100      < 40      < 40      < 40      < 30      < 30      < 30      < 10      < 10      < 10       <5        <5        <5        <5        <5        <5      Remark deleted

WAS      Post-CMP clean chemicals: elements TBD (ppt, each) [17]            TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD

 IS      Post-CMP clean chemicals: elements TBD (ppt, each) [17]            1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000      1000

         Plating chemicals: particles > critical size (/ml) [1] [9] [17]    TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD       TBD      Remark deleted
         ILD CVD Precursors (e.g., Trimethylsilane,
 IS
         Tetramethylsilane) [25]
 IS      Metals except B, Au, Ag (ppb, each)                                 <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5
 IS      B, Au, Ag (ppb, each)                                              <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10
 IS      H2O (ppm)                                                           <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1
 IS      CO, CO2 (ppm)                                                      < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5
 IS      Non-methane hydrocarbons C2-C4 (ppm)                                <4        <4        <4        <4        <4        <4        <4        <4        <4        <4        <4        <4        <4        <4        <4        <4
 IS      Nitrogen (ppm)                                                      <2        <2        <2        <2        <2        <2        <2        <2        <2        <2        <2        <2        <2        <2        <2        <2
 IS      Ar+O2 (ppm)                                                        < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5
 IS      Chloride (ppm)                                                      <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1
 IS      CVD Precursors (e.g., Trimethylaluminum) [25]
 IS      Metals each element (ppb)                                          <150      <150      <150      <150      <150      <150      <150      <150      <150      <150      <150      <150      <150      <150      <150      <150
 IS      O2 (ppm)                                                           <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10
 IS      Silicon (ppm)                                                       <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1
 IS      Hydrocarbons (ppm)                                                  <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5
         Bulk Gases (Contaminants, ppbv) [5]
         N2 (O2, H2, H2O, CO, CO2, THC) [34]                                 <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5
         O2 (N2)                                                            <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50
ADD      O2 (Ar)                                                           <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000
         O2 (H2, H2O, CO, CO2, THC)                                         <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10
         Ar (N2, O2, H2, H2O, CO, CO2, THC) [34]                             <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5        <5
         H2 (N2)                                                            <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50       <50
         H2 (O2, H2O, CO, CO2, THC)                                         <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10
         He (N2, O2, H2, H2O, CO, CO2, THC)                                 <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10       <10
         CO2 (CO, H2O, O2, THC)                                            <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000
WAS      Lithography Purge Gases
 IS      Lithography and Critical Metrology Purge Gases (ppbv)
         Critical clean dry air (H2O)                                      <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000     <1000
         Critical clean dry air (H2, CO)                                   <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000

         Critical clean dry air (organics (molecular weight >
WAS                                                                          <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3
         benzene) normalized to hexadecane equivalent) (ppb)

         Critical clean dry air (organics (molecular weight >
 IS                                                                          <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3
         benzene) normalized to hexadecane equivalent)
WAS      Critical clean dry air (total base as NH3) (ppb)                    <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1
 IS      Critical clean dry air (total base as NH3)                          <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1        <1
WAS      Critical clean dry air (NH3 (as NH3)) (ppb)                        < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     <0.1      <0.1
 IS      Critical clean dry air (NH3 (as NH3))                              < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     <0.1      <0.1
         Critical clean dry air (total acid including SO2 (as SO4))
WAS                                                                         < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     <0.1      <0.1
         (ppb)

 IS      Critical clean dry air (total acid including SO2 (as SO4))         < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     <0.1      <0.1

WAS      Critical clean dry air (SO4 (as SO4)) (ppb)                       < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    <0.03     <0.03
 IS      Critical clean dry air (SO4 (as SO4))                             < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    < 0.03    <0.03     <0.03
         Critical clean dry air (Each refractory compound (0rganics
                                                                            < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     < 0.1     <0.1      <0.1
         containing S, P, Si)
         Lithography nitrogen tool/maintenance purging gas supply
WAS                                                                         <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500
         (H2O, O2, CO2) (ppb)
         Lithography nitrogen tool/maintenance purging gas supply
 IS                                                                         <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500      <500
         (H2O, O2, CO2)
         Lithography nitrogen tool/maintenance purging gas supply
WAS                                                                        <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000
         (CO) (ppb)
         Lithography nitrogen tool/maintenance purging gas supply
 IS                                                                        <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000
         (CO)
         Lithography nitrogen tool/maintenance purging gas supply
WAS                                                                        <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000
         (H2) (ppb)
         Lithography nitrogen tool/maintenance purging gas supply
 IS                                                                        <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000     <2000
         (H2)
         Lithography nitrogen tool/maintenance purging gas supply
WAS      (organics (molecular weight > benzene) normalized to                <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3
         hexadecane equivalent) (ppb)
         Lithography nitrogen tool/maintenance purging gas supply
 IS      (organics (molecular weight > benzene) normalized to                <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3
         hexadecane equivalent)
         Lithography nitrogen tool/maintenance purging gas supply
WAS                                                                        < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    <0.15     <0.15
         (total base (as NH3)) (ppb)
         Lithography nitrogen tool/maintenance purging gas supply
 IS                                                                        < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    <0.15     <0.15
         (total base (as NH3))

         Lithography nitrogen tool/maintenance purging gas supply
WAS                                                                        < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   <0.025    <0.025
         (total acid (as SO4) including SO2) (ppb)

         Lithography nitrogen tool/maintenance purging gas supply
 IS                                                                        < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   <0.025    <0.025
         (total acid (as SO4) including SO2)

         Lithography nitrogen tool/maintenance purging gas supply
WAS      (refractory compounds (organics containing S, P, Si, etc.)         <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1
         normalized to hexadecane equivalent) (ppb)


         Lithography nitrogen tool/maintenance purging gas supply
 IS      (refractory compounds (organics containing S, P, Si, etc.)         <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1
         normalized to hexadecane equivalent)

         Lithography helium tool/maintenance purging gas supply
WAS                                                                        <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500
         (H2O) (ppb)
         Lithography helium tool/maintenance purging gas supply
 IS                                                                        <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500     <3500
         (H2O)
         Lithography helium tool/maintenance purging gas supply
WAS                                                                        <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000
         (O2, CO2) (ppb)
         Lithography helium tool/maintenance purging gas supply
 IS                                                                        <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000     <4000
         (O2, CO2)
         Lithography helium tool/maintenance purging gas supply
WAS                                                                        <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000
         (CO, H2) (ppb)
         Lithography helium tool/maintenance purging gas supply
 IS                                                                        <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000    <10000
         (CO, H2)
         Lithography helium tool/maintenance purging gas supply
WAS      (organics(molecular weight > benzene) normalized to                 <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3
         hexadecane equivalent) (ppb)
         Lithography helium tool/maintenance purging gas supply
 IS      (organics(molecular weight > benzene) normalized to                 <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3        <3
         hexadecane equivalent)
         Lithography helium tool/maintenance purging gas supply
WAS                                                                        < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15
         (total base (as NH3)) (ppb)
         Lithography helium tool/maintenance purging gas supply
 IS                                                                        < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15    < 0.15
         (total base (as NH3))
         Lithography helium tool/maintenance purging gas supply
WAS                                                                        < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025
         (total acid including SO2 (as SO4)) (ppb)
         Lithography helium tool/maintenance purging gas supply
 IS                                                                        < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025   < 0.025
         (total acid including SO2 (as SO4))

         Lithography helium tool/maintenance purging gas supply
WAS      (refractory compounds (organics containing S, P, Si, etc.)         <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1
         normalized to hexadecane equivalent) (ppb)



6c401391-7dff-4f12-b68c-5db004ffe385.xls,2008_YE9               118/167
ITRS


         Year of Production                                                 2007                2008                 2009                   2010             2011             2012              2013             2014              2015     2016      2017      2018      2019      2020      2021      2022

         Flash ½ Pitch (nm) (un-contacted Poly)(f)                           54                  45                      40                  36               32                28               25                23               20       18        16        14        13        11        10        9
         DRAM ½ Pitch (nm) (contacted)                                       65                  57                      50                  45               40                36               32                28               25       23        20        18        16        14        13        11
         MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                  68                  59                      52                  45               40                36               32                28               25       23        20        18        16        14        13        11

         Lithography helium tool/maintenance purging gas supply
 IS      (refractory compounds (organics containing S, P, Si, etc.)         <0.1                 <0.1                <0.1                   <0.1             <0.1              <0.1             <0.1              <0.1             <0.1     <0.1      <0.1      <0.1      <0.1      <0.1      <0.1      <0.1
         normalized to hexadecane equivalent)

         Number of particles > critical size (/M3) [1]                       100                 100                     100                100               100              100               100              100              100      100       100       100       100       100       100       100
ADD      Number of particles > 0.1 µm (/M3) [1]                              <5                  2.3                     1.6                 1.1             0.80              0.57             0.40              0.29             0.20     0.14      0.10      0.07      0.05      0.036     0.025     0.018
         Specialty Gases
         Etchants (Corrosive, e.g., BCl3, Cl2, HBr)
         O2, H2O (ppbv)                                                     <500                <500                 < 500                 < 500             < 500            < 500            < 500             < 500            < 500     < 500     < 500     < 500     < 500     < 500     < 500     < 500
         Critical specified metals/total metals (ppbw) [19]           <10/1000          <1/1000                    <1/1000                <1/1000          <1/1000           <1/1000          <1/1000          <1/1000           <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000
         Etchants (Non-corrosive, e.g., C5F8, C4F8, C4F6, CH2F2)
         O2, H2O (ppbv)                                                 <1000            <1000                      <1000                 < 1000            < 1000           < 1000            < 1000           < 1000            < 1000   < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
         Etchants (e.g. Xe)
         O2, H2O (ppbv)                                                < 1000            < 1000                     < 1000                < 1000            < 1000           < 1000            < 1000           < 1000            < 1000   < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
ADD      Interconnect low k CVD Precursors - Bulk film/Dielectric Barrier/Etchstop [25]
ADD      Alkylsilanes (e.g., Trimethylsilane [993-07-7] , Tetramethylsilane [75-76-3], DMDMOS [1112-39-6], OMCTS [556-67-2]) [25]
ADD      Metals except B, Au, Ag (ppb, each)                                 <5                  <5                      <5                  <5               <5                <5               <5                <5               <5       <5        <5        <5        <5        <5        <5        <5
ADD      B, Au, Ag (ppb, each)                                               <10                 <10                 <10                    <10               <10              <10               <10              <10              <10      <10       <10       <10       <10       <10       <10       <10
ADD      H2O (ppm)                                                           <1                  <1                      <1                  <1               <1                <1               <1                <1               <1       <1        <1        <1        <1        <1        <1        <1
ADD      CO, CO2 (ppm)                                                      < 0.5               < 0.5                < 0.5                  < 0.5            < 0.5            < 0.5             < 0.5            < 0.5             < 0.5    < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5
ADD      Non-methane hydrocarbons C2-C4 (ppm)                                <4                  <4                      <4                  <4               <4               <4                <4               <4                <4       <4        <4        <4        <4        <4        <4        <4
ADD      Nitrogen (ppm)                                                      <2                  <2                      <2                  <2               <2               <2                <2               <2                <2       <2        <2        <2        <2        <2        <2        <2
ADD      Ar+O2 (ppm)                                                        < 0.5               < 0.5                < 0.5                  < 0.5            < 0.5            < 0.5             < 0.5            < 0.5             < 0.5    < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5     < 0.5
ADD      Chloride (ppm)                                                      <1                  <1                      <1                  <1               <1                <1               <1                <1               <1       <1        <1        <1        <1        <1        <1        <1
ADD      CVD Interconnect Metal/Barrier/Glue layers
ADD      Tungsten Hexafluoride [7783-82-6]
ADD      Critical specified metals/total metals (ppbw) [19]               <1/1000              <1/1000             <1/1000                <1/1000          <1/1000           <1/1000          <1/1000          <1/1000           <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000
ADD      O2, H2O (ppbv)                                                    < 1000              < 1000               < 1000                < 1000            < 1000           < 1000            < 1000           < 1000            < 1000   < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
ADD      TDMAT [3275-24-9]
ADD      Critical specified metals/total metals (ppbw)                       tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      O2, H2O (ppbv)                                                    < 1000              < 1000               < 1000                < 1000            < 1000           < 1000            < 1000           < 1000            < 1000   < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
ADD      Hydrocarbons (ppm)                                                  tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
         Tantalum Amides (e.g., PDMAT [19824-50-0], TBTDET
ADD
         [169896-41-7])
ADD      Critical specified metals/total metals (ppbw)                       tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      O2, H2O (ppbv)                                                    < 1000              < 1000               < 1000                < 1000            < 1000           < 1000            < 1000           < 1000            < 1000   < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
ADD      Hydrocarbons (ppm)                                                  tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      CVD/ALD High k gate dielectric Precursors
ADD      Trimethylaluminum (TMAl) [25]
ADD      Metals each element (ppb)                                          <150                <150                 <150                   <150             <150             <150              <150             <150              <150     <150      <150      <150      <150      <150      <150      <150
ADD      O2 (ppm)                                                            <10                 <10                 <10                    <10               <10              <10               <10              <10              <10      <10       <10       <10       <10       <10       <10       <10
ADD      Silicon (ppm)                                                       <1                  <1                      <1                  <1               <1                <1               <1                <1               <1       <1        <1        <1        <1        <1        <1        <1
ADD      Hydrocarbons (ppm)                                                  <5                  <5                      <5                  <5               <5                <5               <5                <5               <5       <5        <5        <5        <5        <5        <5        <5
ADD      Hafnium Amides (e.g. TEMAH [352535-01-4])
ADD      Zr (ppm)                                                            tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      Metals each element (ppb)                                           tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      Hydrocarbons (ppm)                                                  tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      Chloride (ppm)                                                      tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      Hydroloysis product (alkylamine)                                    tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
         Sweep and bubbler gases for ALD/CVD volatile chemical
ADD      delivery e.g., N2 (O2, H2, H2O, CO, CO2, THC) (ppb)                 <5                  <5                      <5                  <5               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
         [34]
ADD      Hafnium Chloride [13499-05-3]
ADD      Zr (ppm)                                                            tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      Other Metals each element (ppb)                                     tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      Hydrocarbons (ppm)                                                  tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
ADD      Hydroloysis product (alkylamine)                                    tbd                 tbd                     tbd                tbd               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
         Sweep and bubbler gases for ALD/CVD volatile chemical
ADD      delivery e.g., N2 (O2, H2, H2O, CO, CO2, THC) ppb)                  <5                  <5                      <5                  <5               tbd              tbd               tbd              tbd               tbd      tbd       tbd       tbd       tbd       tbd       tbd       tbd
         [34]
WAS      Deposition gases (e.g., SiH4, (CH3)3SiH)
 IS      Deposition gases (e.g., SiH4)
         O2, H2O (ppbv)                                                    <1000                <1000               <1000                 < 1000            < 1000           < 1000            < 1000           < 1000            < 1000   < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
         Critical specified metals/total metals (ppbw) [19]           <10/1000                 <1/1000             <1/1000                <1/1000          <1/1000           <1/1000          <1/1000          <1/1000           <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000
         Dopants (ppbv)                                                  <1                      <1                  <1                     <1               <1                <1               <1               <1                <1        <1        <1        <1        <1        <1        <1        <1
         Deposition gases (e.g. NH3)
         O2, H2O (ppbv)                                                < 1000                   < 1000              < 1000                 < 1000           < 1000            < 1000           < 1000           < 1000            < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
         Critical specified metals/total metals (ppbw) [19]           <1/1000                  <1/1000             <1/1000                <1/1000          <1/1000           <1/1000          <1/1000          <1/1000           <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000
         Deposition gases (e.g., N2O, NO)
         O2, H2O (ppbv)                                                < 1000                   < 1000              < 1000                 < 1000           < 1000            < 1000           < 1000           < 1000            < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
         Critical specified metals/total metals (ppbw) [19]           <1/1000                  <1/1000             <1/1000                <1/1000          <1/1000           <1/1000          <1/1000          <1/1000           <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000
WAS      Deposition gases (e.g., WF6)
WAS      O2, H2O (ppbv)                                                < 1000                   < 1000              < 1000                 < 1000           < 1000            < 1000           < 1000           < 1000            < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
WAS      Critical specified metals/total metals (ppbw) [19]           <1/1000                  <1/1000             <1/1000                <1/1000          <1/1000           <1/1000          <1/1000          <1/1000           <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000   <1/1000
         Deposition gases - electrical dopants (e.g. AsH3, PH3, B2H6)
         O2, H2 (ppb [36]                                               <500                    <500                 < 500                 < 500             < 500            < 500            < 500             < 500            < 500     < 500     < 500     < 500     < 500     < 500     < 500     < 500
         Other dopants (ppbv)                                            <1                       <1                   <1                    <1                <1               <1               <1                <1               <1        <1        <1        <1        <1        <1        <1        <1
         Mixing tolerance for mixtures (relative variance)             +/-1%                    +/-1%                +/-1%                 +/-1%             +/-1%            +/-1%            +/-1%             +/-1%            +/-1%     +/-1%     +/-1%     +/-1%     +/-1%     +/-1%     +/-1%     +/-1%
         Deposition gases - GeH4
         O2, H2O (ppbv)                                                 <500                    <500                 < 500                 < 500             < 500            < 500            < 500             < 500            < 500     < 500     < 500     < 500     < 500     < 500     < 500     < 500
         Other dopants (ppbv)                                            <1                       <1                   <1                    <1                <1               <1               <1                <1               <1        <1        <1        <1        <1        <1        <1        <1
         Mixing tolerance for mixtures                                 +/-1%                    +/-1%                +/-1%                 +/-1%             +/-1%            +/-1%            +/-1%             +/-1%            +/-1%     +/-1%     +/-1%     +/-1%     +/-1%     +/-1%     +/-1%     +/-1%
         Implant gases - AsH3, PH3, BF3
         O2, H2O (ppbv)                                                 <500                    <500                 < 500                 < 500             < 500            < 500            < 500             < 500            < 500     < 500     < 500     < 500     < 500     < 500     < 500     < 500
         Other dopants (ppbv)                                            <1                      <1                   <1                    <1                <1               <1               <1                <1               <1        <1        <1        <1        <1        <1        <1        <1
         Laser gases - Litho, (e.g. F2/Kr/Ne)
         O2, H2O (ppbv)                                                < 1000                   < 1000              < 1000                 < 1000           < 1000            < 1000           < 1000           < 1000            < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000    < 1000
         Mixing tolerance for F2 (relative variance)                   +/-4%                    +/-4%               +/-4%                  +/-4%            +/-4%             +/-4%            +/-4%            +/-4%             +/-4%     +/-4%     +/-4%     +/-4%     +/-4%     +/-4%     +/-4%     +/-4%
         Other constituents (ppbv)                                    < 25000                  < 25000             < 25000                < 25000          < 25000           < 25000          < 25000          < 25000           < 25000   < 25000   < 25000   < 25000   < 25000   < 25000   < 25000   < 25000

                                               Manufacturable solutions exist, and are being optimized
                                                                 Manufacturable solutions are known
                                                                          Interim solutions are known 
                                                           Manufacturable solutions are NOT known



         Notes for Tables YE9a and b:

         [1] Critical particle size is based on ½ design rule. All defect densities are “normalized” to critical particle size. Critical particle size does not necessarily mean “killer” particles. Because of instrumentation
         limitations, particle densities at the critical dimension for < 90 nm will need to be estimated from measured densities of larger particles and an assumed particle size distribution or determined empirically and
         extrapolated. The particle size distribution will depend on the fluid (e.g. water, clean room air, gases), f(x)=K*1/X^n (where n=2.2 for air/gases, n varies significantly for liquids from 1 to 4, empirical
         determination is recommended) [1] ,   [2]




         [2] Airborne particle requirements are based on ISO 14644-1 at “at rest”.[3]

         [3] Ion/species indicated is basis for calculation. Exposure time is 60 minutes with starting surface concentration of zero. Basis for lithography projections is defined by lithography tool suppliers. Metals and
         organics scale as defined in the surface preparation roadmap for metallics and organics. Values listed in table are based on experience, however, all airborne molecular contaminants can be calculated as
         S=E*(N*V/4); where S is the arrival rate (molecules/second/cm 2 ), E is the sticking coefficient (between 0 and 1), N is the concentration in air (molecules/cm 3 ); and V is the average thermal velocity (cm/second).
                                                                                  -5                  -6                 -5
         The following sticking coefficients have been proposed; SO4 = 1x10            , NH3 = 1x10        , Cu = 2x10        . The sticking coefficients for organics vary greatly with molecular structure and are also dependent on
         surface termination.

         [4] Includes P, B, As, Sb

         [5] Contaminant targets apply up to POE (point-of-entry). POE is defined as the entry point to the equipment or subequipment, see also the text. Benchmark data has been collected both at Point of Delivery (POD)
         or Point of Entry (POE), which typically show only minor differences.


         [6] Critical metals and ions may include: Al, As, Ba, Ca, Co, Cu, Cr, Fe, K, Li, Mg, Mn, Na, Ni, Pb, Sn, Ti, Zn. Three different case studies were reviewed where the levels of Ca, Fe, and Ni in the UPW resulted in
         levels of problem densities (atoms/sq cm) on the wafer. These were reduced to acceptable levels by reducing the level of these elements in the UPW to levels well below 10 ppt. In only one case does the data exist
         that showed success by obtaining values below 0.5 ppt. These results drive the 1.0 ~ 0.5 ppt values.

         [7] Units on all contaminants in WECC Table are often given as ppb (or ppm or ppt, we use ppb here solely for demonstration purposes). The reader should be aware that these units of parts per billion (ppb) may
         be ppb by mass, volume, or molar ratios. Where not designated, the following guidelines apply: Chemicals and UPW are typically ppb by mass, gases and clean room are typically ppb by volume. In the case of
         the fluid acting as an ideal gas, ppb by volume is equal to ppb molar. The notable exception to the above is metals in gases that are ppb by mass.




         Some parameters in the tables may be considered process variables rather than contaminants in the classical meaning. They are marked by an asterix. The limits are sometimes fluent.

         [8] Detection of metals at the levels indicated will be dependent on sampling time and flow rate. Sticking Coefficients vary widely for metals. It is generally believed that Cu has a sticking coefficient 10x of other
         metals, and therefore the guideline for Cu could be lower.


         [9] Key particle size for scratching particles depends on mean particle size of slurry. Target level will be specific to slurry and wafer geometry sensitivity.

         [10] The Dissolved Nitrogen range is solely for the physical process needs of megasonics cleaning. Processes without megasonics cleaning can ignore the line item. The concentration is process specific and needs
         to be determined by the end user. Factors to consider include UPW temperature, partial pressure in the gas phase and megasonic energy input at the tool. Other gases, such as oxygen and hydrogen, may be used
         with different optimum levels. Process enhancements through chemistry associated with the other gases or other chemicals are outside of the scope of this chapter.




         [11] As of the current year's update the finest sensitivity liquid particle sensor for chemicals is 0.065 µm. Values obtained by these particle counters are not directly comparable to the roadmap values and need to
         be normalized to critical particle size values in the roadmap using the equation and methods of Footnote A above. Interim solution to higher sensitivity particle counter is to collect data over longer time period to
         provide greater precision in the data near the threshold sensitivity of the counter. Most benchmark data has been collected at Point of Delivery (POD) or Point of Entry (POE) and is the basis for parameters.




6c401391-7dff-4f12-b68c-5db004ffe385.xls,2008_YE9             119/167
ITRS


         Year of Production                                                 2007              2008              2009             2010              2011              2012              2013              2014              2015         2016   2017   2018   2019   2020   2021   2022

         Flash ½ Pitch (nm) (un-contacted Poly)(f)                           54                45                40                36               32                28                25                23                20           18     16     14     13     11     10     9
         DRAM ½ Pitch (nm) (contacted)                                       65                57                50                45               40                36                32                28                25           23     20     18     16     14     13     11
         MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                  68                59                52                45               40                36                32                28                25           23     20     18     16     14     13     11
         [12] SMC Organics: Single wafer shall be oxidized to make organic-free, then wafer shall be exposed for 24 hours and top side analyzed by TD-GC-MS with 400°C thermal desorption, and quantitation based on
         hexadecane external standard. TIC response factor per SEMI MF 1982-1103 (formerly ASTM 1982-99).[4] Limits determined by above method are a guideline for many organics. Note higher limits can be used
         for process wafers oxidized or cleaned prior to subsequent process step. Processes such as gate oxide formation, or polysilicon deposition, may be more sensitive to organics, especially high boilers such as DOP.
         Silicon nitride nucleation may also be more sensitive than above for some processes. Please note dopants requirement is covered in earlier section. Contamination levels are time based, and samples should be
         exposed for a weeks time for better sensitivity; ng/cm2/week. Total contamination level on reticles that cause problems also vary with energy exposure. These guidelines subject to change with new data currently
         being generated.



         [13] SMC Dopants: Single wafer is first stripped with HF to yield dopant-free surface and than exposed for 24 hours. Topside of wafer is analyzed by methods known to give reliable recovery of boron. This is a
         guideline for dopants based on sampling in operating running fabs. Lower specifications may be required for key FEPs, especially for smaller geometries, lower thermal budgets, and for lightly-doped devices. If
         wafers are stripped with HF or BOE immediately prior to next thermal process, then steps may become less sensitive to surface molecular dopants, and higher limits apply. Note that BEPs tend to be orders of
         magnitude less sensitive to dopants than FEPs.



         [14] SMC Metals: Single wafer known to meet the ITRS FEP spec of 1E10 atoms/cm 2 , from the Starting Materials table, is exposed to a clean environment for 24 hours. Subsequent analysis of top surface by VPD-
         ICP-MS or VPD-GFAA. Lower specifications may be required for key FEPs, especially for smaller geometries. If wafers are cleaned prior to the next thermal process, then air exposure during earlier steps may be
         less of an issue. Note that majority of environmental metallic contaminants are particles, not molecular. If total particles on wafers are kept in spec than majority of metals, most metals from the environment
         should be within specifications. Back-end processes (BEPs) tend to be less sensitive to metals that FEPs provided not particles. Specs of twice the incoming wafer specs are readily achievable and readily
         measurable in case of wafers exposed for 24 hours.

         [15] SMC General: A 24-hour exposure will accentuate the contamination per wafer as wafers are often exposed too much shorter times in actual processing. The above SMC (surface molecular contamination)
         limits are preliminary, and no single value applies to all process steps or types of organics, dopants or metals. The SMC limits can vary substantially from process to process, and local air purification or purges
         may be needed to control contaminant levels.




         [16] Dissolved oxygen (DO) has an effect on pre-gate oxide cleaning and the etch rate of non H-passivated SiO2 and copper structures. The level in the table is that of the most stringent. It is expected that slightly
         higher levels within the same order of magnitude would not have any significant effect on manufacturing processes. If the water for a specific processes need to remain at low oxygen concentrations lower levels of
         dissolved oxygen could provide somewhat larger process time windows before critical concentration levels are reached. It is known that some fabs consider DO a process variable and operate at DO levels 3
         orders of magnitude higher than stated in the table. Corrosion rates as a function of DO are not a linear relationship for all materials, specifically copper etch rates are near a maximum at 300 ppb DO.



         [17] Uncertain at this time what target levels might be set given the variety of chemistries used in the industry and unknown sensitivity of the wafer to particles or ionic contamination in the chemical. This parameter
         is identified as a potentially critical one that should be considered and work is ongoing to define the correct levels.


         [18] Total Silica in UPW is a source of wafer water spots. Silica dissolved from the wafer surface, and later deposited back, is also a significant source for water spotting. The values in the table are based on
         concentrations found in typical fabricators manufacturing 90 nm geometry devices. As device geometries shrink lower silica concentration requirements are expected. Research is needed to develop a clear
         correlation between UPW concentrations and water spots. Boron and Reactive Silica have been removed from the table as UPW operational parameters, values of 50ppt and 300ppt respectively. These two species
         remain valuable indicators of ion exchange resin removal capacity as they are the first two anions to leak from a mixed bed. They have been removed from the table as they are not process critical at typical UPW
         system concentrations.

         [19] The list of critical metals (e.g., Al, Ca, Cu, Fe, Mg, Ni, K, Si, Na) varies from process to process depending on the impact on electrical parameters such as gate oxide integrity or minority carrier lifetime as well
         as mobility of the metal in the substrate. The metals listed in note [G] for liquid process chemicals are of concern but the issues around metals in specialty gases are primarily around the potential for corrosion to
         add metal particles to the gas flow (e.g., Fe, Ni Co, P). The potential for volatile species containing metals must be considered for each specialty gas but are generally not present in the bulk gases.




         [20] The following is a complete list of metal ions of concern in certain liquid chemicals: Ag, Al, As, Au, Ba, Ca, Cd, Co, Cr, Cu, Fe, K, Li, Mg, Mn, Mo, Na, Ni, P, Pb, Pd, Pt, Ru, Sb, Sn, Sr, Ti, V, W, Zn.




         [21] Elements listed that are not in parentheses may cause high or some risk to device quality and may often be present in process chemicals. Elements listed that are in parentheses may cause high risk to device
         quality but are not typically present in process chemicals.


         [22] Immersion photolithography tool manufacturers have asked for TOC levels ranging from less than 0.5 to less than 1.0 ppb in UPW. Some manufacturers are supplying ancillary UPW processing equipment to
         achieve these targets. The concern is hazing of tool lenses. At this time no data has been presented to support the source of haze generating organics to be the UPW. Other sources of organics are the photoresists
         and topping chemistries. This temperature stability requirement is for immersion photolithography tools, using UPW as an immersion fluid, and based upon utility requirements projected by some tool
         manufacturers in 2005. It represents the maximum rate of change of the temperature of the cold UPW supplied to the tool in order for the tool to maintain process required temperature stability.



         [23] The photolithography AMC guidelines are for tools with ArF lasers only, and are based on inputs from the photolithography tool supplier. All photolithography tools should have chemical filters on the
         makeup air to the internals of the tools. These filters have a finite lifetime, which is dependent on the contaminant loading. Providing a chemically cleaner environment will extend the life of these filters.




         [24] Other critical ions may include inorganic ions such as Fluoride, Chloride, Nitrate, Nitrite, Phosphate, Bromide, Sulfate as well as ammonium. However no reference was currently found that these ions in
         typical concentrations found in ultrapure water up to 50 ppt have any impact on the process. Also for organic anions such as acetate, formate, propionate, citrate, and oxalate no harmful levels have been
         established up to now.

         [25] The variety of CVD and ALD precursors is continuously increasing as well as their applications. The contaminant types and levels vary widely due to the different chemical behavior. An overview about typical
         precursors is therefore given in attachment Precursor table.


         [26] Particle values for 2006 are based upon 2005 UPW benchmark studies of leading fabs manufacturing/developing 45 nm to 130 nm products measuring particles with optical lasers and Scanning Electron
         Microscopy (SEM). The values are dependent on the methods used for measurement. Values are based on the most widely used method of measurement namely, optical laser monitoring from various instrument
         manufacturers. Current optical laser technology is limited to particles >0.05 um, and incapable of detecting particles at critical size based on ½ design rule. Although a correlation between wafer surface counts
         and UPW particles has not been established a conservative position has been agreed upon which supports the Front End Process ITRS Roadmap for wafer surface counts. It is believed that particle chemical
         composition plays an increasing role with regard to the contamination effect.

          Dialog with the Surface Prep/FEP subcommittee has resulted in a reduction of the suggested maximum particle levels from the previous year. Although a correlation between wafer surface counts and UPW
         particles has not been established a conservative position has been agreed upon which supports the Front End Process ITRS Roadmap for wafer surface counts. Note that current optical laser technology is limited
         to particles >0.05 um, and is incapable of detecting particles at the critical size based on ½ design rule.

         [27] It needs to be considered that the total H2O2 anion concentration will impact the life time of the solution. Also the fluoride in the ppm range of the total chemical mixture can etch the wafer.




         [28] Concentrations higher than 100 ppb could cause corrosion especially in back end of line processes.

         [29] The ultrapure water parameters provided in this table are applicable for the most critical process unless otherwise identified by additional footnotes. Further information can be found in the Supplementary
         tables


         [30] Typical Organic Acids found in cleanroom environments that may be of concern include Acetate, Citrate, Formate, Glycolate, Lactate, Oxalate, and Proprionate. Others may also be of concern. These acids
         can be a significant load on acid removal filters.


         [31] Ideally, continuous monitoring using online instrumentation would be preferred when practical since this can give both long term averages and catch excursions. When online monitoring is not available, an
         average grab sample for at least 4 hours, and not more than 24 hours is recommended, to get an average, increase sensitivity of the analysis, and avoid short term transient effects


         [32] Other corrosive species include contaminants such as chlorine. Humidity is also of major concern, as it exacerbates corrosion. The humidity should be kept as low as possible in corrosive environments.




         [33] Calculations for expressing ng/L into ppt are; [(ng/(L of Air) * (24.4 L of Air)/mol Air / MW(ng/nmol)) * *1000picomol/nmol ] = picomol/mol of Air = ppt molar and/or ppt volume.

         [34] For certain processes such as sputtering POE purifiers may be required for N2 and Ar

         [35] CO2 here is assumed to be used for wet cleaning and other equipment, not for super critical CO2 applications or dry etching.

         [36] Epi – need to purify @ 45 nm; currently must add purifiers from B2H6/Germane/PH3/AsH3 - need 100 ppb

         [37] The variation is defined at one location over time in at rest conditions. As reference point for the POE a location is chosen 0.3 m below the ceiling panels. Common sense requires that sensitive equipment are
         not installed heat sources within the cleanroom, since they may impact the temperature control between the reference point and the actual inlet to the mini-environment/tool filter.


         [38] Bacteria level in clean UPW system is typically zero, therefore the target level of bacteria is less than 1 CFU/L. It should be noted that the that commonly used method of bacteria cultivation has it's limitations
         and slightly higher than 1 readings may be result of the sample contamination (see more details in the supplimental materials). See also Supplementary materials.




         [1] Cooper, D. W., “Comparing Three Environmental Particle Size Distributions,” Journal of the IES, Jan/Feb 1001, 21-24

         [2] Pui, D. Y. H. and Liu, B.Y.H., “Advances in Instrumentation for Atmospheric Aerosol Measurement,” TSI Journal of Particle Instrumentation, Vol 4. (2) Jul-Dec 1989, 3-2.

         [3] ISO 14644-1 Cleanrooms and Associated Controlled Environments-Part 1: Classification of Air Cleanliness.

         [4] SEMI MF1982-1103 (previously ASTMF 1982-99e1), Standard Test Methods for Analyzing Organic Contaminants on Silicon Wafer Surfaces by Thermal Desorption Gas Chromatography, SEMI.




6c401391-7dff-4f12-b68c-5db004ffe385.xls,2008_YE9             120/167
                                                   Table MET1                      Metrology Difficult Challenges
   Difficult Challenges ≥ 22 nm                                                    Summary of Issues
   Factory level and company wide metrology integration for real-time              Standards for process controllers and data manageme
   in situ, integrated, and inline metrology tools; continued development              Conversion of massive quantities of raw data to
   of robust sensors and process controllers; and data management that                 the yield of a semiconductor manufacturing proc
   allows integration of add-on sensors.                                               developed for trench etch end point, and ion spe
   Starting materials metrology and manufacturing metrology are                    Existing capabilities will not meet Roadmap specific
   impacted by the introduction of new substrates such as SOI. Impurity                be detected and properly sized. Capability for SO
   detection (especially particles) at levels of interest for starting materials       Challenges come from the extra optical reflectio
   and reduced edge exclusion for metrology tools. CD, film thickness,
   and defect detection are impacted by thin SOI optical properties and
   charging by electron and ion beams.
   Control of new process technology such as Dual Patterning                       Overlay measurements for Dual Patterning have tigh
   Lithography, complicated 3D structures such as capacitors and contacts             defines CD. 3D Interconnect comprises a numbe
   for memory, and 3D Interconnect are not ready for their rapid                      process control needs are not yet established. Fo
   introduction.                                                                      measurements will be required for trench structu
                                                                                      and contacts.
   Measurement of complex material stacks and interfacial properties               Reference materials and standard measurement meth
   including physical and electrical properties.                                       capacitor dielectrics with engineered thin films a
                                                                                       interconnect barrier and low-k dielectric layers,
                                                                                       measurement of gate and capacitor dielectric av
                                                                                       needs to characterize interfacial layers. Carrier m
                                                                                       needed for stacks with strained silicon and SOI
                                                                                       barrier layers. Metal gate work function characte
   Measurement test structures and reference materials.                            The area available for test structures is being reduced
                                                                                       Measurements on test structures located in scrib
                                                                                       die performance. Overlay and other test structur
                                                                                       and test structure design must be improved to en
                                                                                       measurements in the scribe line and on chip pro
                                                                                       rapid access to state of the art development and
                                                                                       fabricate relevant reference materials.
   Difficult Challenges < 22 nm
   Nondestructive, production worthy wafer and mask-level microscopy               Surface charging and contamination interfere with el
   for critical dimension measurement for 3D structures, overlay, defect                measurements must account for sidewall shape.
   detection, and analysis                                                              require measurement of trench structures. Proce
                                                                                        and etch bias will require greater precision and 3
   New strategy for in-die metrology must reflect across chip and across              Correlation of test structure variations with in-die
   wafer variation.                                                                difficult as device shrinks. Sampling plan optimizati
   Statistical limits of sub-32 nm process control                                 Controlling processes where the natural stochastic va
                                                                                      difficult. Examples are low-dose implant, thin-g
                                                                                      of very small structures.
   Structural and elemental analysis at device dimensions and                      Materials characterization and metrology methods ar
   measurements for beyond CMOS.                                                      layers, dopant positions, defects, and atomic con
                                                                                      dimensions. One example is 3D dopant profiling
                                                                                      assembling processes are also required.
   Determination of manufacturing metrology when device and                        The replacement devices for the transistor and struct
   interconnect technology remain undefined.                                           copper interconnect are being researched.
* SPC—statistical process control parameters are needed to replace inspection, reduce process variation, control defects, and re
gy Difficult Challenges
f Issues
or process controllers and data management must be agreed upon.
 sion of massive quantities of raw data to information useful for enhancing
 d of a semiconductor manufacturing process. Better sensors must be
ped for trench etch end point, and ion species/energy/dosage (current).
pabilities will not meet Roadmap specifications. Very small particles must
 cted and properly sized. Capability for SOI wafers needs enhancement.
nges come from the extra optical reflection in SOI and the surface quality.



asurements for Dual Patterning have tighter control requirements. Overlay
  CD. 3D Interconnect comprises a number of different approaches. New
  control needs are not yet established. For example, 3D (CD and depth)
 ements will be required for trench structures including capacitors, devices,
ntacts.
materials and standard measurement methodology for new high-κ gate and
or dielectrics with engineered thin films and interface layers as well as
nnect barrier and low-k dielectric layers, and other process needs. Optical
 ement of gate and capacitor dielectric averages over too large an area and
o characterize interfacial layers. Carrier mobility characterization will be
  for stacks with strained silicon and SOI substrates, or for measurement of
 layers. Metal gate work function characterization is another pressing need.
 ailable for test structures is being reduced especially in the scribe lines.
rements on test structures located in scribe lines may not correlate with in-
formance. Overlay and other test structures are sensitive to process variation,
t structure design must be improved to ensure correlation between
 ements in the scribe line and on chip properties. Standards institutions need
ccess to state of the art development and manufacturing capability to
te relevant reference materials.


rging and contamination interfere with electron beam imaging. CD
ements must account for sidewall shape. CD for damascene process may
 measurement of trench structures. Process control such as focus exposure
h bias will require greater precision and 3D capability.
on of test structure variations with in-die properties is becoming more
device shrinks. Sampling plan optimization is key to solve these issues.
 processes where the natural stochastic variation limits metrology will be
 t. Examples are low-dose implant, thin-gate dielectrics, and edge roughness
  small structures.
haracterization and metrology methods are needed for control of interfacial
dopant positions, defects, and atomic concentrations relative to device
ions. One example is 3D dopant profiling. Measurements for self-
 ling processes are also required.
ment devices for the transistor and structure and materials replacement for
interconnect are being researched.
process variation, control defects, and reduce waste.
Table MET2                                                                    Metrology Technology Requirements

Year of Production                                                                2007     2008         2009           2010

Microscopy

Inline, nondestructive microscopy process resolution (nm) for P/T=0.1             0.22      0.2          0.18           0.16

                                                                                   16       17            17            >20
Microscopy capable of measurement of patterned wafers having
maximum aspect ratio/diameter (nm) (DRAM contacts) [A]
                                                                                   76       67            60             50
Materials and Contamination Characterization
Real particle detection limit (nm) [B]                                             25       22            20             18
Minimum particle size for compositional analysis (dense lines on
                                                                                   22       19            17             15
patterned wafers) (nm)
Specification limit of total surface contamination for critical GOI surface
                                                                               5.00E+09   5.00E+09     5.00E+09      5.00E+09
materials (atoms/cm2) [C]
Surface detection limits for individual elements for critical GOI elements
                                                                               5.00E+08   5.00E+08     5.00E+08      5.00E+08
(atoms/cm2) with signal-to-noise ratio of 3:1 for each element



                Manufacturable solutions exist, and are being optimized
                                    Manufacturable solutions are known
                                             Interim solutions are known      
                               Manufacturable solutions are NOT known

Notes for Tables MET2a and b:

[A] Metal and via aspect ratios are additive for dual-Damascene process flow.

[B] This value depends on surface microroughness and layer composition.

[C] The requirements for metal contamination have been changed based on less stringent requirements found in Front End Processes chapter Surface Pre
                    2011          2012           2013           2014          2015      2016       2017       2018       2019



                    0.14           0.13          0.12            0.1          0.09       0.08       0.07       0.06       0.06

                    >20            >20           >20            >20            >20       >20        >20        >20        >20

                     40            35             30             28            25        23         20         18         16


                     16            14             13             11            10         9          8          7          6

                     13            12             11              9                8      7          6          6          5

                  5.00E+09      5.00E+09       5.00E+09      5.00E+09       5.00E+09   5.00E+09   5.00E+09   5.00E+09   5.00E+09


                  5.00E+08      5.00E+08       5.00E+08      5.00E+08       5.00E+08   5.00E+08   5.00E+08   5.00E+08   5.00E+08




End Processes chapter Surface Preparation Technology Requirements table, Note F.
 2020      2021   2022    Driver



  0.05                   MPU Gate

  >20                      D1/2

  14


   6                       MPU

   5                       D1/2

5.00E+09                 MPU Gate


5.00E+08                 MPU Gate
          Table MET3                                                                                                          Lithography Metrology (Wafer) Tec

          Year of Production                                                                                                     2007
          Flash ½ Pitch (nm) (un-contacted Poly)(f)                                                                               54
          DRAM ½ Pitch (nm) (contacted)                                                                                           68
          MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                                                                      68
          MPU Printed Gate Length (nm) ††                                                                                         42
          MPU Physical Gate Length (nm) [after etch]                                                                              32
          Wafer minimum Overlay control DRAM single litho tool (nm)                                                               14
          Wafer overlay output metrology uncertainty (nm, 3 s)* P/T=.2                                                            2.7
          Gate (MPU Physical Gate Length)
          Printed gate CD control (nm)
          Uniformity (variance) is 12% of CD
          Allowed lithography variance = 3/4 total variance of physical gate length *                                             3.3

                                                                                                                                 0.66
Formula   Wafer CD metrology tool uncertainty (nm) * 3s at P/T = 0.2 for isolated printed and physical lines [A]
          Etched Gate Line Width Roughness (nm, 3 s) < 8% of CD **                                                               2.55
          Wafer CD metrology tool uncertainty for LWR (nm), P/T=0.2                                                              0.51
          Dense Line (Flash 1/2 pitch, un-contacted poly)                                                                         54
          Wafer dense line CD control (nm) *
          Uniformity is 12% of CD
          Allowed lithography variance = 3/4 total variance                                                                       5.6
Formula   Wafer CD metrology tool uncertainty (nm) *
          (P/T = .2 for dense lines**)                                                                                           1.11
          Contacts
          Wafer minimum contact hole (nm, post etch) from lithography tables: Flash                                               54
Formula   Wafer CD metrology tool uncertainty (nm) *
          (P/T=.2 for contacts)***                                                                                                1.31
          Aspect Ratio Capability for Trench Structure CD Metrology                                                              15:01
          Double Patterning Metrology Requirements ****
          Double Exposure and Etch - Process Range (nm)                                                                           9.6
          Double Exposure and Etch - Uncertainty (nm)                                                                             1.9
          Image placement (nm, multipoint) for double patterning of independent layers                                            5.8
                                                                                   Metrology Uncertainty (nm, P/T=0.2)            1.2
          Difference in CD Mean-to-target for two masks as a double patterning set                                                2.7
                                                                                   Metrology Uncertainty (nm, P/T=0.2)            0.3

          Double exposure: image placement for each mask used for exposing mutually dependent layers (nm)                        2.4
                                                                                Metrology Uncertainty (nm, P/T=0.2)              0.5
          Double exposure: dual space, etch bias repeatability and uniformity                                                    1.6
                                                                                Metrology Uncertainty (nm, P/T=0.2)              0.32
          Spacer PEE process: first pass CD control (after etch) - carrier                                                        4.6
                                                                                Metrology Uncertainty (nm, P/T=0.2)               0.9
          Spacer PEE process: thickness deviation of final layer (mean)                                                          1.1
                                               Metrology Uncertainty (nm, P/T=0.2?), based on film thickness Metrology           0.22
          Spacer PEE process: thickness uniformity of final layer                                                                 2.2
                                                                                 Metrology Uncertainty (nm, P/T=0.2)              0.4
Formula   Side Wall Angle control - Double patterning (from litho tables)                                                        1.56
                                                                                        Metrology Uncertainty (nm, P/T=0.2)       0.3


          Notes for Table MET3a and b:


          * All uncertainty values are 3 Sigma in nm and include single tool precision, metrology tool-to-tool matching, and other component as discussed in the text. Requ
          section of this chapter above for further information.
**The Lithography roadmap has changed from line edge roughness (LER) to line width roughness (LWR). See SEMI standard for definition 11


LER—Local line-edge variation (3 sigma total, all frequency components included, both edges) evaluated along a distance that allows determination of spatial wa
LWR=sqrt(2)LER.

***Bottom CD for contacts presently requires measurement by FIB.


****Double patterning done using carrier structure and spacers have standard gate process ranges and CD controls for carrier and spacers. The best case scena
and B to A. This is not mentioned here. Process Range will be in the order of Single Machine Overlay.


                                                      Manufacturable solutions exist, and are being optimized
                                                                         Manufacturable solutions are known
                                                                                  Interim solutions are known   
                                                                    Manufacturable solutions are NOT known
             Lithography Metrology (Wafer) Technology Requirements

                                   2008             2009            2010             2011             2012             2013            2014             2015
                                    45               40              36               32               28               25              22               20
                                    59               52              45               40               36               32              28               25
                                    59               52              45               40               36               32              28               25
                                    38               34              30               27               24               21              19               17
                                    29               27              24               22               20               18              17               15
                                    12               10               9                8                7                6               6                5
                                    2.4              2.1             1.8              1.6              1.4              1.3             1.1              1.0




                                    3.0              2.8              2.5             2.3              2.1              1.9              1.7             1.6

                                   0.60             0.55             0.50             0.46            0.42             0.38             0.35             0.32

                                   2.32             2.12             1.94            1.77             1.61             1.47             1.34            1.23
                                   0.46             0.42             0.39            0.35             0.32             0.29             0.27            0.25
                                    45               40               36              32               28               25               22              20



                                    4.7              4.2              3.7             3.3              2.9              2.6              2.3             2.1

                                   0.94             0.83             0.74             0.66            0.59             0.52             0.46             0.42

                                    45               40               36               32              28               25               22               20

                                    1.10            0.98             0.87             0.78            0.69             0.62             0.54             0.49
                                   15:01           15:01            15:01            15:01           15:01            20:01            20:01            20:01

                                    8.1              7.1              6.4             5.7              5.1              4.5              4.0             3.5
                                    1.7              1.5              1.3             1.1              1.0              0.9              0.8             0.7
                                    5.8              5.0              4.4             3.8              3.4              3.0              2.7             2.4
                                    1.2              1.0              0.9             0.8              0.7              0.6              0.5             0.5
                                    2.4              2.1              1.8             1.6              1.4              1.3              1.1             1.0
                                    0.2              0.2              0.2             0.2              0.1              0.1              0.1             0.1

                                   2.1              1.8              1.6              1.4             1.2              1.1              1.0              0.9
                                   0.4              0.4              0.3              0.3             0.2              0.2              0.2              0.2
                                   1.4              1.2              1.0              0.9             0.8              0.7              0.7              0.6
                                   0.28             0.24             0.21             0.19            0.17             0.15             0.13             0.12
                                    3.9             3.5               3.0             2.7              2.4              2.1             1.9              1.7
                                    0.8              0.7              0.6             0.5              0.5              0.4              0.4             0.3
                                   0.9              0.80             0.70            0.62             0.56             0.55            0.49             0.44
                                   0.18             0.16             0.14             0.12            0.11             0.11             0.10             0.09
                                    1.8             1.6              1.4              1.2              1.1              1.1             1.0             0.87
                                    0.4              0.3             0.3              0.2              0.2              0.2             0.2              0.2
                                   1.56             1.56            1.56             1.56             1.56             1.56            1.56             1.56
                                    0.3              0.3             0.3              0.3              0.3              0.3             0.3              0.3




matching, and other component as discussed in the text. Requirement is for uncertainty value at top, middle, and bottom CD. See the Explanation of Uncertainty
LWR). See SEMI standard for definition 11


 ated along a distance that allows determination of spatial wavelength equal to two times the technology generation dimension. LWR is defined as




and CD controls for carrier and spacers. The best case scenario is shown here assuming alignment of A to X and B to X. Worst case scenario is alignming A to X
.
2016    2017    2018    2019    2020    2021   2022
17.9    15.9    14.2    12.6    11.3    10.0    8.9
22.5    20.0    17.9    15.9    14.2    12.6   11.3
22.5    20.0    17.9    15.9    14.2    12.6   11.3
15.0    13.4    11.9    10.7     9.7     8.9    8.1
14.0    12.8    11.7    10.7     9.7     8.9    8.1
  5       4       4       3       3      3      2
 0.9     0.8     0.7     0.6     0.6    0.5    0.5




 1.5     1.3     1.2     1.1     1.0    0.9    0.8

0.29    0.27    0.24    0.22    0.20    0.18   0.17

1.12    1.02    0.93    0.85    0.78    0.71   0.65
0.22    0.20    0.19    0.17    0.16    0.14   0.13
17.9    15.9    14.2    12.6    11.3    10.0   8.9



 1.9     1.7     1.5     1.3     1.2    1.0    0.9

0.37    0.33    0.29    0.26    0.23    0.21   0.19

 18      16      14      13      11      10     9

 0.44    0.39    0.35    0.31    0.28   0.25   0.22
20:01   20:01   20:01   20:01   20:01

 3.1     2.8     2.6     2.3    1.98    0.00   0.00
 0.6     0.6     0.5     0.5    0.40    0.36   0.32
 2.1     1.9     1.7     1.5    1.35    1.20   1.07
 0.4     0.4     0.3     0.3    0.27    0.24   0.21
 0.9     0.8     0.7     0.6    0.57    0.51   0.45
 0.1     0.1     0.1     0.1    0.06    0.05   0.05

0.8     0.7     0.6     0.6     0.49    0.44   0.39
0.2     0.1     0.1     0.1     0.10    0.09   0.08
0.5     0.5     0.4     0.4     0.33    0.29   0.26
0.10    0.09    0.08    0.07    0.07    0.06   0.05
 1.6    1.4     1.3     1.1     1.01    0.90   0.80
 0.3     0.3     0.3     0.2    0.20    0.18   0.16
0.35    0.31    0.28    0.25    0.22    0.20   0.18
0.07    0.06    0.06    0.05    0.04    0.04   0.04
0.70    0.62    0.56    0.49    0.44    0.39   0.35
 0.1    0.1     0.1     0.1     0.09    0.08   0.07
1.56    1.56    1.56    1.56    1.56    1.56   1.56
0.3     0.3     0.3     0.3     0.31    0.31   0.31
Table MET4a and b                                                        Lithography Metrology (Mask) Technology Requirements:

Year of Production                                                            2007           2008            2009           2010
MPU gate in resist (nm)                                                        42             38              34             30
DRAM/Flash CD control (3sigma) (nm)                                            6.6            5.9             5.3            4.7
CD uniformity (nm, 3 sigma) isolated lines [H]                                  3             2.6             2.4            2.2
Wafer overlay control (nm)                                                     11             10               9              8

Wafer contact CD control (nm)*, Uniformity is 13.5% of CD = minimum
contact hole size. Allowed lithography variance = 3/4 total variance           7.5            6.6             5.9            5.3
Mask nominal image size (nm) [B]                                               170            151             135            120
Mask minimum primary feature size [D]                                          119            106             94             84
Optical Section
Minimum OPC size (opaque at 4, nm) [D]                                        70              64             56
Image placement (nm, multi-point) [F]                                           7             6.1             5.4            4.8
Dual Patterning image Placement (nm) [F}                                       4.9            4.3             3.8            3.4

Difference in CD mean-to-target for two masks as a dual patterning set         2.6                                           1.8
CD uniformity allocation to mask (assumption)                                  0.4            0.4             0.4            0.4
MEEF isolated lines [G]                                                        1.6            1.8              2             2.2
MEEF dense lines [G]                                                           2.2            2.2             2.2            2.2
MEEF contacts [G]                                                              3.5             4               4              4
Mask CD uniformity (nm, 3 sigma) isolated lines [H]                            2.6             2              1.7            1.4
Mask CD uniformity (nm, 3 sigma) dense lines [J]                               4.8            4.3             3.8            3.4
Mask contact CD control (nm)*, Uniformity is 12% of CD = minimum
contact hole size
Allowed lithography variance = 3/4 total variance                               3             2.4             2.1            1.9
Mask image placement metrology uncertainty, P/T=0.1                            0.7            0.6             0.5            0.5
Mask CD uncertainty (nm, 3 sigma) isolated lines, [H] (P/T=0.2 for
isolated lines, binary**)                                                      0.5             0.4            0.3             0.3
Mask CD uncertainty (nm, 3 sigma) dense lines [J]                             0.96            0.86           0.77            0.68
Mask contact CD uncertainty (nm)*, Uniformity is 12% of CD =
minimum contact hole size
Allowed lithography variance = 3/4 total variance                              0.6            0.5             0.4            0.4
Specific Requirements (altPSM, attPSM)
Alternated PSM phase mean deviation                                             1              1               1              1
Phase metrology uncertainty, P/T=0.2                                           0.2            0.2             0.2            0.2

Attenuated PSM phase mean deviation from 180º (± degree) [S]                    3              3               3              3
Phase uniformity metrology uncertainty, P/T=0.2*                               0.6            0.6             0.6            0.6
* All uncertainty values are 3 Sigma in nm and include single tool precision, metrology tool-to-tool matching, and other component as discussed in the tex


Notes for Table MET4a and b:

[A] The designation for CD measurement for isolated lines in the near term is a result of roadmap process range and the need for tool matching in the pr
to achieve. A work-around for isolated line CD measurement is to use a single tool and avoid tool matching. Long term, CD measurement for 25 nm
extension of known methods may not be possible.

[B] Mask Nominal Image Size—Equivalent to wafer minimum feature size in resist multiplied by the mask reduction ratio that equals 4  .

[C] Mask Minimum Primary Feature Size—Minimum printable feature after OPC application to be controlled on the mask for CD placement and defects.

[D] Mask OPC Feature size—Minimum width of the smallest non-printing features on the mask.
[E] The CD process range for isolated gate lithography is 4/5 of the total CD process range of 1/10 the CD at 3 s .

The CD process range is 4/5 of the 15% of CD for dense lines and 2/3 the 15% for contact/via. Process ranges are variances. It is important to note that t
40% of the total lithography process range. The mask error factor (MEF) reduces the CD process range, and its effect is calculated by dividing the process


[F] The mask error factor for isolated lines on a binary mask changes from 1.4 to 1.6 at 65 nm.

[G] Values in the table are for binary and attenuated phase shift masks. The Mask Error Factor for alternating phase shift masks is 1.

[H] The Mask Error Factor for dense lines is 2 from 100nm to 70nm. It is 2.5nm at 65nm, and is 3 for 57 and 50 nm. Values are for binary and attenuating

[I] The mask error factor for contact and via lines is 3 from the 100nm to 70 nm. It is 3.5 at 65 nm, and is 4 for 57 and 50 nm.

[J] Values are for binary and attenuated phase shift masks.
Technology Requirements: Optical

                        2011          2012           2013           2014            2015           2016      2017   2018   2019
                         27            24             21             19              17             15        13     12     11
                         4.2           3.7            3.3             3              2.6            2.3       2.1    1.9    1.7
                        1.9            1.7            1.6             1.3            1.2            1.1       1     0.8    0.7
                         7              6              6               5              5              4        4      3      3



                        4.7            4.2            3.7            3.3              3             2.6      2.3    2.1    1.9
                        107            95             85              76             67             60        54     48     42
                        75             67             59              53             47             42        37     33     30



                        4.3            3.8            3.4              3             2.7            2.4      2.1    1.9    1.7
                         3             2.7            2.4             2.1            1.9            1.7

                                       1.3
                        0.4            0.4            0.4            0.4             0.4            0.4      0.4    0.4    0.4
                        2.2            2.2            2.2            2.2             2.2            2.2      2.2    2.2    2.2
                        2.2            2.2            2.2            2.2             2.2            2.2      2.2    2.2    2.2
                         4              4              4              4               4              4        4      4      4
                        1.2            1.1             1             0.8             0.8            0.7      0.6    0.5    0.5
                         3             2.7            2.4             2.1            1.9            1.7      1.5    1.4    1.2



                        1.7            1.5            1.3            1.2             1.1            0.9      0.8    0.7    0.7
                        0.4            0.4            0.3

                         0.2           0.2            0.2             0.2            0.2            0.1      0.1     0.1    0.1
                        0.61          0.54           0.48            0.43           0.38           0.34      0.3    0.27   0.24



                        0.3            0.3            0.3            0.2             0.2            0.2      0.2    0.1    0.1

                         1              1              1
                        0.2            0.2            0.2

                         3              3              3              3               3              3
                        0.6            0.6            0.6            0.6             0.6            0.6
er component as discussed in the text. Requirement is for uncertainty value at top, middle, and bottom CD.




 the need for tool matching in the precision requirement makes this requirement very difficult
g term, CD measurement for 25 nm linewidths requires a technology breakthrough because


tio that equals 4  .

mask for CD placement and defects.
riances. It is important to note that the mask part of the lithography process range is allowed
is calculated by dividing the process range by the MEF.




shift masks is 1.

alues are for binary and attenuating phase shift masks.

50 nm.
2020   2021   2022
  9     8.4    7.5
 1.5
0.7
 3



1.7
 38
 26



1.5




0.4
2.2
2.2
 4
0.5
1.1



0.6



 0.1
0.21



0.1
Table MET4c and d                                                         Lithography Metrology (Mask) Technology Requirements: E

Before 22 nm; grey-colored cells indicate the transition to EUV technology.
Year of Production                                                          2007           2008           2009            2010
Flash ½ Pitch (nm) (Un-contacted Poly)                                                      45             40              36
Image placement error (nm, multipoint)                                                      6.1            5.4             4.8
CD Uniformity (3 sigma at 4  , nm)

Isolated lines, Uniformity is 10% of CD, MEEF varies with year                              3.4              3             2.7

Dense lines, Uniformity is 15% of CD, MEEF varies with year                                 8.2             7.3            6.5

Contact/Vias, Uniformity is 10% of CD, MEEF varies with year                                 7.6            6.8            4.8
Mask CD metrology tool uncertainty isolated lines*, **                                      0.68           0.61           0.54
Mask CD metrology tool uncertainty dense lines*, **                                          1.6            1.5            1.3
Mask CD metrology tool uncertainty contacts*, **                                             1.5            1.4             1
Specific EUV Requirements
Mean peak reflectivity                                                                      65%            66%            66%
Peak reflectivity uniformity (3s %)                                                        0.69%          0.58%          0.47%
Absorber sidewall angle tolerance (degrees)                                                   1              1            0.75
Absorber LER (3 sigma, nm)                                                                  3.2            2.8            2.5
Mask substrate flatness (peak-to-valley, nm)                                                 75             60             50
Metrology mean peak reflectivity uncertainty (P/T=0.2, %)                                  1.30%          1.30%          1.30%

Peak reflectivity uniformity metrology uncertainty (3s, P/T = 0.2)                         0.14%          0.12%          0.09%

Absorber sidewall angle metrology uncertainty (degrees 3s, P/T = 0.2)                        0.2            0.2           0.15
Absorber LER metrology uncertainty (3s, P/T=0.2)                                            0.64           0.57            0.5

Mask substrate flatness metrology uncertainty (nm 3s, P/T=0.2)                               15             12             10
*All uncertainty values are 3 sigma in nm and include metrology tool-to-tool matching.
**Measurement tool performance needs to be independent of target shape, material, and density. See the Explanation of Uncertainty section of this chapte


               Manufacturable solutions exist, and are being optimized
                                   Manufacturable solutions are known
                                            Interim solutions are known   
                             Manufacturable solutions are NOT known
Technology Requirements: EUV


                      2011            2012            2013               2014   2015    2016    2017    2018    2019
                       32              28              25                 22     20      18      16      14      13
                       4.3             3.8             3.4                 3     2.7     2.4     2.1     1.9     1.7



                        2.4            2.1             1.9               1.7     1.5     1.3     1.2     1.1      1

                       5.8             5.2             4.6               4.1     3.7     3.3     2.9     2.6     2.3

                        4.3            3.8             3.4                 3     2.7     1.8     1.6     1.4     1.3
                       0.48           0.43            0.38               0.34    0.3    0.27    0.24    0.21    0.19
                        1.2             1             0.92               0.82   0.73    0.65    0.58    0.52    0.46
                       0.86           0.76            0.68               0.61   0.54    0.36    0.32    0.29    0.26

                       66%             67%            67%             67%        67%     67%     67%     67%     67%
                      0.42%           0.37%          0.33%           0.29%      0.26%   0.23%   0.21%   0.19%   0.17%
                       0.69            0.62            0.5             0.5        0.5     0.5     0.5     0.5     0.5
                       2.2              2             1.8             1.6        1.4     1.3     1.1       1     0.9
                        41             36              32              29         26      23      20      18      16
                      1.30%          1.30%           1.30%           1.30%      1.30%   1.30%   1.30%   1.30%   1.30%

                      0.08%          0.07%           0.07%           0.06%      0.05%   0.05%   0.04%   0.04%   0.03%

                       0.14           0.12             0.1                0.1    0.1     0.1     0.1     0.1     0.1
                       0.45            0.4            0.36               0.32   0.28    0.25    0.22     0.2    0.18

                       8.2             7.3             6.5               5.8     5.1     4.6     4.1     3.6     3.2


 of Uncertainty section of this chapter above for further information.
2020    2021   2022
 11      10      9
 1.5



 0.9

 2.1

 1.1
0.17
0.41
0.23

 67%
0.15%
  0.5
 0.8
  14
1.30%

0.03%

 0.1
0.16

 2.9
      Table MET5a                                                                    Front End Processes Metrology Technology Requirements—Near-term Years

      Grey cells indicate transition years of technologies.

      Cell colors indicate this is an overarching metrology for metal gate thickness and composition that are critical challenges during the long-term years.
      Year of Production                                                                2007         2008           2009           2010            2011          2012         2013         2014
      Surface control limits for trace metals for bulk silicon and SOI top silicon
      layer.                                                                                   10           10             10             10              10            10           10           10
                                                                                       0.5x10       0.5x10        0.5x10          0.5x10         0.5x10         0.5x10       0.5x10       0.5x10
      FEP Table 68 Critical GOI metals (concentration in atoms/cm2)

      EOT (Extended planar bulk) for High Performance MPU/ASIC for
WAS                                                                                      1.1          0.5
      1.5E20 doped Poly-Si [FEP Table 69]
      EOT (Extended planar bulk) for High Performance MPU/ASIC for 1.0
IS                                                                                       1.1           1              1
      E20 doped Poly-Si [FEP Table 69]
      EOT (FDSOI) High Performance MPU/ASIC for metal gate [FEP Table
WAS                                                                                                                                 0.7             0.6          0.55          0.5          0.5
      69]
      EOT (FDSOI) High Performance MPU/ASIC for metal gate [FEP Table
IS                                                                                                                                                                             0.7         0.65
      69]
      EOT (multi-gate) High Performance MPU/ASIC for metal gate [FEP
WAS                                                                                                                                                 0.8           0.7          0.6          0.6
      Table 69]
      EOT (multi-gate) High Performance MPU/ASIC for metal gate [FEP
IS
      Table 69]
      Low operating power EOT (bulk) for 1.5E20 doped poly-Si [FEP Table
WAS                                                                                      1.2          0.8            0.7            0.6             0.5           0.5
      69]
      Low operating power EOT (bulk) for 1.5E20 doped poly-Si [FEP Table
IS                                                                                       1.3          1.2            1.1            0.7             0.7           0.6          0.5
      69]

WAS   Low operating power EOT (multi gate using metal-gate) FEP Table 69                                                                            0.9           0.9          0.9          0.8

IS    Low operating power EOT (multi gate using metal-gate) FEP Table 69                                                                                                       0.9          0.9

WAS   Low operating power EOT (FD-SOI) (metal gate) [FEP Table 69]                                                                                  0.9           0.9          0.8          0.8

IS    Low operating power EOT (FD-SOI) (metal gate) [FEP Table 69]                                                                                                             0.9         0.85

      ± 3s dielectric process range (EOT) (nm)                                           4%          4%            4%            4%             4%           4%          4%          4%

      EOT measurement precision 3s (nm) [B]                                            0.0044       0.0040         0.0040         0.0028          0.0028        0.0024       0.0020       0.0026
      Gate Dielectric Elemental Composition including Nitrogen Concentration
                                                                                    0.1             0.1              0.1              0.1             0.1             0.1             0.1       0.1
      Metrology for Patterned Wafers Precision (at %)
                                                                                   Cylinder        Cylinder        Cylinder        Cylinder        Cylinder        Cylinder      Pedestal     Pedestal
      Capacitor structure                                                       /Pedestal MIM   /Pedestal MIM   /Pedestal MIM   /Pedestal MIM   /Pedestal MIM   /Pedestal MIM      MIM          MIM


      Dielectric constant                                                            40              43               49              65              78              98              130      130

      teq at 25fF (nm)                                                             1.15             0.9              0.8              0.6             0.5             0.4             0.3       0.3
      teq = 3.9*E0*(total capacitor area)/25fF [G]
      DRAM stacked capacitor dielectric physical thickness (nm) calcaulted
                                                                                   11.79             10               10              10              10              10              10        10
      using t eq and dielectric constant

       3 s process range                                                           4%             4%               4%             4%             4%             4%             4%

      DRAM capacitor dielectric physical thickness measurement precision
                                                                                   0.05            0.04              0.04            0.04            0.04            0.04            0.04      0.04
      (nm 3s) [C]

      Uniform channel concentration (cm–3), for Vt=0.4 [W]                      2.5–5.0E18 NA                   NA              NA              NA              NA              NA

      Dopant atom                                                                P, As, B        P, As, B        P, As, B        P, As, B        P, As, B        P, As, B        P, As, B

      Metrology for junction depth [based on drain extension] of (nm) Note
WAS                                                                                 12.5             11               10               9               8               7
      change to different structure for 2008

IS    Drain extension X j (nm) for bulk MPU/ASIC [F]                                 11             9.5              10.9            11.9            10.8             10               9        8.5

WAS   Extension lateral abruptness (nm/decade) [M]                                  2.5             2.3               2               1.8             1.8             1.4


IS    Extension lateral abruptness for bulk MPU/ASIC (nm/decade) [H]                3.5             3.2              2.8              2.4             2.3              2              1.8       1.7

IS    Lateral/depth spatial resolution for 2D/3D dopant profile (nm)                3.5             3.2              2.8              2.4             2.3              2              1.8       1.7

      At-line dopant concentration precision (across concentration range) [D]       4%              4%               4%               2%              2%              2%              2%        2%

      Metrology for metal gate thickness and composition*

      Metal gate work function for bulk MPU/ASIC |Ec,v – fm| (eV) [***] FEP
WAS                                                                                                <0.2              <0.2            <0.2            <0.2            <0.2
      Table 69
      Metal gate work function for FDSOI MPU/ASIC f m – E i (eV)
IS    NMOS/PMOS [S]

      Metal gate work function for FDSOI MPU/ASIC                                                                                     0.15           0.15           0.15           0.15    0.15

      Metal gate work function for multi-gate MPU/ASIC, FEP Table 69 [***]                                                                        midgap          midgap         midgap       midgap
Metal gate work function for bulk low operating power |Ec,v – fm| (eV),
                                                                                        < 0.2   < 0.2   < 0.2   < 0.2    < 0.2
FEP Table 69 [***]
Metal gate workfunction for FDSOI and multi-gateLOP, FEP Table
                                                                                                                midgap   midgap     midgap     midgap
69[***]

Metal gate work function for bulk LSTP |Ec,v – fm| (eV) [***]                           <0.2    <0.2    <0.2     <0.2     <0.2       <0.2

Metal gate work function for FDSOI and multi-gate LSTP | fm - Ei| (eV)|
                                                                                                                         + / -0.1   + / -0.1   + / -0.1
NMOS/PMOS, FEP Table 69 [***]
Elemental Composition Metrology for Metal Gate on Test Wafers
                                                                                        0.1     0.1      0.1     0.1      0.1        0.1        0.1
Precision (at %)
Elemental Composition Metrology for Metal Gate on Patterned Wafers
                                                                                        0.1     0.1      0.1     0.1      0.1        0.1        0.1
Precision (at %)
Starting silicon layer thickness (SOI) (fully depleted) (tolerance ± 5%, 3s)
                                                                                                         5.5     5.2       4.5         4         3.5
(nm) PIDS requirement in FEP Table 69[M]

SOI Si thickness precision (3s in nm)                                                                   0.028   0.026    0.023       0.02      0.018

Metrology for stress/strain in channel and active area

Spatial resolution (nm) of off-line stress measurement at 50MPa
                                                                                   5     4.4     4       3.6     3.2       2.8        2.6        2.2
resolution

Spatial resolution (nm) of in-line stress measurement at 50MPa resolution          65    57      50      45      40        36         32         28

Throughput of in-line stress measurement (Wafers/hour at 25 sites/wafer)           2     2       2       2        2         2          2          2



                 Manufacturable solutions exist, and are being optimized
                                     Manufacturable solutions are known
                                               Interim solutions are known     
                                Manufacturable solutions are NOT known




Notes for Table MET5a and b:

[A] The use of SOI wafers requires metrology development.
[B] Precision calculated from P/T=0.1=6× precision/process range. The measurement requirements specify the equivalent thickness for a silicon dioxide dielectric film. It is expected that high dielectric constant
materials such as Hf-related oxides will be used at and after the 65 nm logic half pitch. The physical thickness of the high dielectric constant layer can be calculated by multiplying the ratio of the dielectric
constants ( ε high- κ / ε ox ) by the effective oxide thickness. The listed precision is based on equivalent oxide thickness and must be multiplied by the ratio of the dielectric constant to obtain precision for the
dielectric of interest. The total capacitance of the dielectric stack also includes that of the dielectric layer plus the interfacial layer, quantum state effects at the channel interface, and that associated with
depletion of charge in the poly silicon gate electrode. Thus, the challenge to gate dielectric thickness measurement includes metrology for the interfacial layer.



[C] In the case of MIS structure, physical thickness, t (diel) , is calculated using the equation of t (diel) =(t eq.ox -1 nm) diel   ε high- κ / 3.9 in which oxide film formed at the interface of poly-silicon and dielectric
[D] High- annealing is taken into with low systematic of MIM structure, t
material inprecision measurements account. In the case error are required. diel is calculated using the equation of t diel = t eq.ox      ε high- κ / 3.9 . Here teq.ox is equivalent oxide thickness, and t diel is dielectric
 2015


        10
0.5x10




  0.5

 0.575

  0.6

 0.77




  0.8

 0.85

  0.8

  0.8

  4%

0.0023
  0.1

Pedestal
  MIM


  98

  0.3

  7.5




 0.03




  7.7




  1.5

  1.5

  2%




 0.15

midgap
midgap




+ / -0.1

 0.1

 0.1

  3.2

0.016




   2

  25

   2
hat high dielectric constant
g the ratio of the dielectric
 to obtain precision for the
e, and that associated with




 poly-silicon and dielectric
and t diel is dielectric
Table MET5b                                                                    Front End Processes Metrology Technology Requiremen
Grey cells indicate transition years of technologies.

* Cell colors indicate this is an overarching metrology for metal gate thickness and composition that are critical challenges during the long-term years.
Year of Production                                                              2016           2017           2018            2019

Surface control limits for trace metals for bulk silicon and SOI top silicon
layer.                                                                         0.5x1010      0.5x1010       0.5x1010        0.5x1010
FEP Table 68 Critical GOI metals (concentration in atoms/cm2)

High-Performance EOT (Extended planar bulk)
High-performance EOT (FDSOI) MPU/ASIC for Metal Gate
High-performance EOT (multi-gate) MPU/ASIC for metal Gate [FEP
                                                                                0.55           0.55            0.55            0.5
Table 69]
Low power EOT (bulk)

Low operating power EOT (multi Gate using metal-Gate) [FEP Table 69]             0.8            0.7            0.7             0.7

Low operating power EOT (FD-SOI) (metal Gate) [FEP Table 69]                     0.7

± 3s dielectric process range (EOT) (nm)                                         4%            4%            4%            4%
EOT measurement precision 3s (nm) [B]                                          0.0022         0.0022         0.0022          0.002
                                                                               Pedestal       Pedestal       Pedestal        Pedestal
DRAM stacked capacitor structure including electrodes                            MIM            MIM            MIM             MIM
DRAM stacked capacitor electrodes (near term)
Capacitor dielelctric constant                                                   91             78              78             70
teq at 25fF (nm)
                                                                                 0.3            0.3            0.3            0.25
teq = 3.9*E0*(total capacitor area)/25fF [G]
DRAM stacked capacitor dielectric physical thickness (nm) calcaulted
                                                                                  7              6              6             4.49
using t eq and dielectric constant
 3 s process range                                                              4%            4%            4%             4%
DRAM capacitor dielectric physical thickness measurement precision (nm
                                                                                0.028         0.024           0.024           0.02
3s) [C]
                                    –3
Uniform channel concentration (cm ), for Vt=0.4 [W]                              NA             NA             NA
Dopant atom                                                                    P, As, B      P, As, B       P, As, B
Metrology for junction depth [based on drain extension] of (nm) Note
change to different structure for 2008
Extension lateral abruptness (nm/decade) [M]                                    TBD            TBD             TBD
Lateral/depth spatial resolution for 2D/3D dopant profile (nm)                  TBD            TBD             TBD
At-line dopant concentration precision (across concentration
                                                                                 2%             2%             2%
range) [D]
Metrology for metal gate thickness and composition*

Metal gate work function for bulk MPU/ASIC |Ec,v – fm| (eV) [***]

Metal gate work function for FDSOI MPU/ASIC | fm – Ei| (eV)|
NMOS/PMOS, FEP Table 69 [***]

Metal gate work function for multi-gate MPU/ASIC, FEP Table 69 [***]           midgap        midgap          midgap         midgap

Metal gate work function for bulk low operating power |Ec,v – fm| (eV)
[***]
Metal gate work function for FDSOI and multi-gate LOP [***]                    midgap        midgap          midgap         midgap
Metal gate work function for bulk LSTP |Ec,v - fm| (eV) [***]
Metal gate work function for FDSOI and multi-gate LSTP | Fm - Ei| (eV)|
                                                                                 0.1           0.1           0.1            0.1
NMOS/PMOS [***]
Elemental Composition Metrology for Metal Gate on Test Wafers
Precision (at %)
Elemental Composition Metrology for Metal Gate on Patterned Wafers
Precision (at %)
Si thickness for multi-gate (nm) FEP Table 69                                     5.4      4.5     4.2     3.8
SOI Si thickness precision (3s in nm)                                            0.027   0.0225   0.021   0.019
Metrology for stress/strain in channel and active area

Spatial resolution (nm) of off-line stress measurement at 50MPa resolution        1.8     1.6      1.4     1.2

Spatial resolution (nm) of in-line stress measurement at 50MPa resolution         22      20       18      16

Throughput of in-line stress measurement (Wafers/hour at 25 sites/wafer)          2        2       2       2


                 Manufacturable solutions exist, and are being optimized
                                    Manufacturable solutions are known
                                             Interim solutions are known     
                               Manufacturable solutions are NOT known
y Technology Requirements—Long-term Years


enges during the long-term years.
                      2020           2021       2022


                    0.5x1010        0.5x1010   0.5x1010




                       0.5            0.5        0.5



                       0.7            0.6        0.6



                      4%             4%        4%
                     0.002           0.002      0.002
                     Pedestal
                       MIM


                       80

                      0.2

                       4.1

                       4%            4%        4%

                      0.02




                    midgap          midgap     midgap



                    midgap          midgap     midgap


                       0.1           0.1       0.1
  3.5     3.2      3
0.0175   0.016   0.015


 1.2      1       0.9

 14       13      11

  2       2       2
Table MET6                                                                    Interconnect Metrology Technology Requirements

Year of Production                                                                2007     2008      2009       2010

Metrology for maintaining planarity requirements: lithography field
(mm × mm) for minimum interconnect CD (nm) [A]                                     500      500       500        500
Measurement of deposited barrier layer at thickness (nm)                           5.2      4.3       3.7        3.3
Process range (± 3 s )                                                           10%      10%       10%        10%
Precision s s (nm) for P/T=0.1 [B]                                                0.052    0.043     0.037      0.033

Metrology capability to measure Cu thinning at minimum pitch due to
erosion (nm), 10%  height, 50% areal density, 500 µm square array                 19       17        15         14

Detection of post deposition and anneal process voids at or exceeding
listed size (nm) when these voids constitute 1% or more of total metal
level conductor volume of copper lines and vias.                                   6.5      5.7        5         4.5
Detection of killer pore in ILD at (nm) size                                       6.5      5.7        5         4.5
Measure interlevel metal insulator bulk/effective dielectric constant ( k )
and anisotropy on patterned structures [C]                                       ≤ 2.4     ≤ 2.4     ≤ 2.2      ≤ 2.2
                                                                                2.7–3.0   2.7–3.0   2.5–2.8    2.5–2.8


                Manufacturable solutions exist, and are being optimized
                                  Manufacturable solutions are known
                                           Interim solutions are known        
                               Manufacturable solutions are NOT known
ogy Requirements

              2011      2012      2013      2014      2015      2016      2017      2018      2019



               500      500       500       500       500       500       500       500       500
               2.9      2.6       2.4       2.1       1.9       1.7       1.5       1.3       1.2
              10%      10%       10%       10%       10%       10%       10%       10%       10%
              0.029    0.026     0.024     0.021     0.019     0.017     0.015     0.013     0.012



               13        13        10        10        9         8         7         7         6




                   4     3.5       3.2       2.8       2.5       2.2       2         1.8       1.6
                   4     3.5       3.2       2.8       2.5       2.2       2         1.8       1.6

              ≤ 2.2     ≤ 2.0     ≤ 2.0     ≤ 2.0     ≤ 1.8     ≤ 1.8     ≤ 1.8     ≤ 1.6     ≤ 1.6
             2.5–2.8   2.3–2.6   2.3–2.6   2.3–2.6   2.1–2.4   2.1–2.4   2.1–2.4   1.9–2.2   1.9–2.2
 2020     2021   2022



 500
 1.1
10%
0.011



  6




  1.4
  1.4

 ≤ 1.6
1.9–2.2
     Table MS1       Modeling and Simulation Difficult Challenges
     Difficult Challenges ≥ 22 nm             Summary of Issues


       Lithography simulation including EUV     Experimental verification and simulation of ultra-high NA vector models, including
                                                polarization effects from the mask and the imaging system
                                                Models and experimental verification of non-optical immersion lithography effects (e.g.,
                                                topography and change of refractive index distribution)
                                                Simulation of multiple exposure/patterning
                                                Multi-generation lithography system models
                                                Simulation of defect influences/defect printing
                                                Optical simulation of resolution enhancement techniques including combined mask/source
                                                optimization (OPC, PSM) and including extensions for inverse lithography

                                                Models that bridge requirements of OPC (speed) and process development (predictive)
                                                including EMF effects and ultra-high NA effects (oblique illumination)

                                                Predictive resist models (e.g., mesoscale models) including line-edge roughness, etch
                                                resistance, adhesion, mechanical stability, and time-dependent effects in multiple exposure

                                                Resist model parameter calibration methodology (including kinetic and transport
                                                parameters)
                                                Simulation of ebeam mask making
                                                Simulation of directed self-assembly of sublitho patterns
                                                Modeling lifetime effects of equipment and masks
IS     Front-end process modeling for           Coupled diffusion/activation/damage/stress models and parameters including SPER and
       nanometer structures                     millisecond processes in Si-based substrate, that is, Si, SiGe:C, Ge, GaAs, SOI, epilayers,
                                                and ultra-thin body devices, taking into account possible anisotropy in thin layers


                                                Modeling of epitaxially grown layers: Shape, morphology, stress
                                                Modeling of stress memorization (SMT) during process sequences
                                                Characterization tools/methodologies for ultra shallow geometries/junctions, 2D low dopant
                                                level, and stress
                                                Modeling hierarchy from atomistic to continuum for dopants and defects in bulk and at
                                                interfaces
                                                Efficient and robust 3D meshing for moving boundaries
                                                Front-end processing impact on reliability
          Integrated modeling of equipment,        Fundamental physical data (e.g., rate constants, cross sections, surface chemistry for ULK,
          materials, feature scale processes and   photoresists and high-k metal gate); reaction mechanisms (reaction paths and (by-)products,
          influences on devices, including         rates ...) , and simplified but physical models for complex chemistry and plasma reaction
          variability
                                                   Linked equipment/feature scale models (including high-k metal gate integration, damage
                                                   prediction)
                                                   Removal processes: CMP, etch, electrochemical polishing (ECP) (full wafer and chip level,
                                                   pattern dependent effects)
                                                   Deposition processes: MOCVD, PECVD, ALD, electroplating and electroless deposition
                                                   modeling
                                                   Efficient extraction of impact of equipment - and/or process induced variations on devices
                                                   and circuits, using process and device simulation
          Ultimate nanoscale device simulation     Methods, models and algorithms that contribute to prediction of CMOS limits
          capability                               General, accurate, computationally efficient and robust quantum based simulators incl.
                                                   fundamental parameters linked to electronic band structure and phonon spectra

                                                   Models and analysis to enable design and evaluation of devices and architectures beyond
                                                   traditional planar CMOS
  IS                                               Models (incl. material models) to investigate new memory devices like MRAM,
                                                   PCM/PRAM, etc
                                                   Gate stack models for ultra-thin dielectrics
DELETED                                            Models for device impact of statistical fluctuations in structures and dopant distribution

                                                   Efficient device simulation models for statistical fluctuations of structure and dopant
                                                   variations and efficient use of numerical device simulation to assess the impact of
                                                   variations on statistics of device performance
                                                   Physical models for novel materials, e.g. high-k stacks, Ge and compound III/V channels …
                                                   : Morphology, band structure, defects/traps, ...
  IS                                               Treatment of individual dopant atoms and traps in (commercial) continuum and MC device
                                                   simulation
                                                   Reliability modeling for ultimate CMOS
                                                   Physical models for stress induced device performance
  IS      Thermal-mechanical-electrical modeling   Model thermal-mechanical, thermodynamic and electrical properties of low k, high k, and
          for interconnections and packaging       conductors for efficient on-chip and off-chip incl. SIP and wafer level packages, including
                                                   power management, and the impact of processing on these properties especially for
                                                   interfaces and films under 1 micron dimension
 ADD                                               Thermal modeling for 3D ICs and assessment of modeling tools capable of supporting 3D
                                                   designs. Thermo-mechanical modeling of Through Silicon Vias and thin stacked dies, and
                                                   their impact on active device properties (stress, expansion, keepout regions, …).
     for interconnections and packaging




                                                 Model effects which influence reliability of interconnects/packages incl. 3D integration
                                                 (e.g., stress voiding, electromigration, fracture, dielectric breakdown, piezoelectric effects)


IS                                               Models to predict adhesion on interconnect-relavant interfaces (homogeneous and
                                                 heterogeneous)
                                                 Simulation of adhesion and fracture toughness characteristics for packaging and die
                                                 interfaces
                                                 Models for electron transport in ultra fine patterned interconnects
     Circuit element and system modeling for     Supporting heterogeneous integration (SoC+SiP) by enhancing CAD-tools to simulate
     high frequency (up to 160 GHz)              mutual interactions of building blocks, interconnect, dies and package:
     applications                                - possibly consisting of different technologies,
                                                 - covering and combining different modelling and simulation levels as well as different
                                                 simulation domains
                                                 Scalable active component circuit models including non-quasi-static effects, substrate
                                                 noise, high-frequency and 1/f noise, temperature and stress layout dependence and parasitic
                                                 coupling
                                                 Scalable passive component models for compact circuit simulation, including interconnect,
                                                 transmission lines, RF MEMS switches, …
                                                 Physical circuit element models for III/V devices
                                                 Computer-efficient inclusion of variability including its statistics (including correlations)
                                                 before process freeze into circuit modeling, treating local and global variations consistently

                                                 Efficient building block/circuit-level assessment using process/device/circuit simulation,
                                                 including process variations
     Difficult Challenges < 22 nm              Summary of Issues
     Modeling of chemical,                     Computational materials science tools to predict materials synthesis, structure, properties,
     thermomechanical and electrical           process options, and operating behavior for new materials applied in devices and
     properties of new materials               interconnects, including especially for the following:
                                                  1) Gate stacks: Predictive modeling of dielectric constant, bulk polarization charge, surface
                                                  states, phase change, thermomechanical (including stress effects on mobility), optical
                                                  properties, reliability, breakdown, and leakage currents including band structure, tunneling
                                                  from process/materials and structure conditions.

                                                 2) Models for novel integrations in 3D interconnects including airgaps and data for
                                                 ultrathin material properties. Models for new ULK materials that are also able to predict
                                                 process impact on their inherent properties
                                                 3) Linkage between first principle computation, reduced models (classical MD or
                                                 thermodynamic computation) and metrology including ERD and ERM applications.
                                                 Modeling-assisted metrology.

                                                 4) Accumulation of databases for semi-empirical computation.
Nano-scale modeling for Emerging        Process Ab-initio modeling tools for the development of novel nanostructure materials and
Research Devices and interconnects      devices (nanowires, carbon nanotubes (including doping), nano-ribbons (graphene),
including Emerging Research Materials   quantum dots, molecular atomic electronics, multiferroic materials and structures, strongly
                                        correlated electron materials)
                                        Device modeling tools for analysis of nanoscale device operation (quantum transport,
                                        tunneling phenomena, contact effects, spin transport, …). Modeling impact of geometry,
                                        interfaces and bias on transport for carbon-based nanoelectronics

Optoelectronics modeling                Materials and process models for on-chip/off-chip optoelectronic elements (transmitters and
                                        receivers, optical couplers). Coupling between electrical and optical systems, optical
                                        interconnect models, semiconductor laser modeling.
                                        Physical design tools for integrated electrical/optical systems
NGL simulation
                                        • Simulation of mask less lithography by e-beam direct write (shaped beam / multi beam),
                                        including advanced resist modeling (low activation energy effects for low-keV writers (shot
                                        noise effects & impact on LER); heating and charging effects), including impact on device
                                        characteristics (e.g. due to local crystal damage by electron scattering or charging effects)
                                        • Simulation of nano imprint technology (pattern transfer to polymer = resist modeling,
                                        etch process)
      Table MS2A       Modeling and Simulation Technology Requirements: Capabilities—Near-term Years

      Year of Production                                    2007               2008               2009               2010               2011              2012               2013               2014             2015

      DRAM ½ Pitch (nm) (contacted)                          65                 57                 50                 45                 40                36                 32                 28               25

      MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)          68                 59                 52                 45                 40                36                 32                 28               25

      MPU Physical Gate Length (nm)                          25                 23                 20                 18                 16                14                 13                 11               10
      Lithography

                                                                                                    Simulation of EUV incl. optical flare, optical
                                                            Simulation of immersion
                                                                                             lithography for very high NA (about 1.7), ML2, imprint   NGL models and modeling of materials and components (immersion,
WAS   Exposure                                        lithography for high NA liquids (NA
                                                                                                 lithography options; models bridging OPC and                    EUV, ML2 lithographic processes, imprint)
                                                                 about 1.5) [1]
                                                                                                      predictive feature scale simulation [2]

                                                                                                    Simulation of EUV incl. optical flare, optical
                                                            Simulation of immersion
                                                                                             lithography for very high NA (about 1.7), ML2, imprint   NGL models and modeling of materials and components (immersion,
IS    Exposure                                        lithography for high NA liquids (NA
                                                                                                 lithography options; models bridging OPC and                    EUV, ML2 lithographic processes, imprint)
                                                                 about 1.5) [1]
                                                                                                      predictive feature scale simulation [2]




                                                          Predictive
                                                         chemically
                                                       amplified resist
                                                      models including
                                                                           Multiple exposure; EUV resists; finite polymer-size                                                              Non-conventional photoresist
                                                           LER and                                                                Meso-scale resist models with finite molecule effects;
WAS   Resist models                                                        effects; line collapsing; lithography on topography;                                                             models and coupling with etch
                                                      immersion (liquid-                                                                              resist flare
                                                                                         coupling with etch models                                                                                    models
                                                       solid interface),
                                                       and methods to
                                                       easily calibrate
                                                         parameters




                                                        Predictive chemically amplified
                                                                                              Multiple exposure; EUV resists;
                                                       resist models including LER and
                                                                                              finite polymer-size effects; line                                                              Models for non-conventional
                                                      immersion (liquid-solid interface),                                         Meso-scale resist models with finite molecule effects;
IS    Resist models                                                                              collapsing; lithography on                                                                photoresists models and coupling
                                                        and methods to easily calibrate                                                               resist flare
                                                                                              topography; coupling with etch                                                                       with etch models
                                                      parameters. Multiple exposure and
                                                                                                          models
                                                          lithography on topography
                                                              TCAD-based methods to detect weak spots in
IS    Large area lithography simulation*                  lithography and etching across chip whole exposure                          TCAD-based inverse lithography modeling
                                                                                 field *
      Front End Process Modeling

                                                          High-κ dielectrics and gate        Model material properties and electrical behavior of prioritized alternative dielectrics (e.g. Hf-    Modeling of new process steps /
IS    Gate stack*                                          materials (interfaces, impurity      based) and gates (interfaces, defects, impurities, stress, work function and band gap offset,          processing and properties of
                                                           diffusion, electrical barrier) [3]                        mobility, leakage - incl. metal gates and FUSI) [4]                                   alternative materials



                                                         Calibration of present models for Si
                                                                 based materials incl.
      Continuum diffusion and activation models           stress/strain,silicidation and new                     Refined and predictive models with better accuracy for upcoming process steps and applications
                                                          annealing steps (e.g. millisecond
                                                                        anneal)



                                                                                                    Inclusion of stress, extension to other materials used in active device, calibration of atomistic modeling on first-principle
      Atomistic modeling for activation and diffusion*    Speedup of Kinetic Monte-Carlo
                                                                                                                           calculations and experiments, integration with continuum process simulation

      Topography and Material Modeling [5]

                                                                                              Integration of feature-scale simulation with equipment
                                                           (Surface) physics based feature    (plasma) models; electrical properties and stress incl.           Including data beyond topography to also include surface and sub-
      Etching / deposition                               scale models (incl. redeposition and    microstructure in deposition; layout dependence;                 surface material property prediction, full molecular dynamcs (or
                                                                       stress)                   process integration (coupling of etch-deposition-                                atomistic) feature scale models
                                                                                                              plating-CMP-lithography)


                                                         Calculation of thermodynamic and        Calculation of mechanical properties; process impact on intrinsic material behavior, integrity and electrical performance under
      Alternative material modeling
                                                               electronic properties                                                                         strain

                                                                                                                        Computer engineered materials and process recipes; predictive manufacturability and yield; full process
      Equipment impact on process results including
                                                                                                                       integration models. Integrated equipment/feature scale modeling extended to include material information
      material properties
                                                                                                                                                                from the atomic scale

      Numerical Device Modeling [6]


                                                           Orientation-dependent mobility
                                                          models incl. field-dependent non-     Mobility models for high-κ gate
      Transport modeling [7]                                 linear strain effects, surface   stacks; efficient inclusion of quasi-                  Mobility models consistent with QM confinement in thin films (esp. SOI)
                                                         roughness effects of nitrided oxides          ballistic transport
                                                            and orientation of the channel



                                                         Device models to include additional                                                                                                           Nanoscale simulation capability
                                                                                                   Efficient quantum-mechanical simulation of 3D device structures, including thin films,
      Additional requirements for non-classical CMOS      interfaces (esp. w.r.t. mobility in                                                                                                         including accurate atomistic and
                                                                                                                            consistent with mobility models
                                                                      thin films)                                                                                                                             quantum effects


                                                             Single-cell modeling of
                                                                                                    Material properties and reliability modeling of novel     Modeling of nanowires, carbon-based nanoelectronics graphene, etc. and spin-
IS    Novel devices *                                        MRAMs, PCMs, FeRAMs and
                                                                                                                      memory devices                                                        based devices
                                                                 SONOS/NROMs


WAS   Reliability and noise modeling                       HF, 1/f and RTS noise modeling                                       Trap generation during operation (HCI, NBTI, PBTI, ….)


IS    Reliability and noise modeling                       HF, 1/f and RTS noise modeling                               Trap generation during operation (HCI, NBTI, PBTI, ….) for conventional and new gate stacks
      Circuit Component Modeling [8]



                                                      Compact models for non-
                                                                                               Circuit models for non-classical CMOS devices including reliability and influences of         Circuit models for nanoscale
WAS   Active devices*                               classical CMOS/ non-quasi-static
                                                                                                   statistics; circuit models for classical CMOS including quasi-ballistic effects            devices and interconnects
                                                            models for CMOS

                                                   Compact models for non-classical            Circuit models for non-classical CMOS devices including reliability and influences of
                                                                                                                                                                                             Circuit models for nanoscale
IS    Active devices*                              CMOS/ non-quasi-static models for        statistics; circuit models for classical CMOS devices including inhomogeneous doping and
                                                                                                                                                                                              devices and interconnects
                                                               CMOS                                              quasi-ballistic effects; include models for self-heating

                                                   Hierarchical process-aware full chip
OLD   Interconnects and integrated passives*                                                                               Include self-healing and reliability
                                                                 RLC [9]
                                                   Hierarchical process-aware full chip
IS    Interconnects and integrated passives*                                                                       Include em-coupling self-healing and reliability                              Include self-healing
                                                                 RLC [9]


                                                        Models that relate material properties (process related or fundamental) to electron
      Process and materials impact on electrical
                                                     transport (e.g. in conducting lines). Includes models for electron scattering. Models that
      performance of interconnects *
                                                          predict paths to material property repair (e.g. low-k repair, capacitance repair)




                                                                                                                                                       Robust and rapid
                                                                                                                                                        construction of
                                                                                                               Include EM and thermal coupling in         behavioural     Include EM and thermal coupling between building
ADD   Heterogeneous integration
                                                                                                                         device models                     models of                          blocks
                                                                                                                                                        building blocks
                                                                                                                                                         or subcircuits




      Package Modeling

                                                      Unified RLC extraction and
      Electrical modeling*                          multiscale modeling for package /              Reduced order models                      Full-wave analysis                   Mixed electrical/optical analysis
                                                                 chips
                                                     Thermo-
                                                     mechanical-        Include non-bulk and porous/air            Include reliability (esp. life
      Thermal-mechanical modeling *
                                                      integrated            gap materials properties                        prediction)
                                                        models



                                                    Improved material models (visco-
IS    Material properties *                           elasticity, creep, plasticity),                Full die simulation
                                                                interfaces



WAS   Numerical Analysis
 IS   General requirements on tools

                                                      Robust, reliable, efficient and user-friendly 3D grid
WAS   Meshing *
                                                          generation including moving boundaries


IS    Meshing *                                      Robust, reliable, efficient and user-friendly 3D grid generation including moving boundaries
                                                              More robust and more parallelizable   Discretization schemes alternative e.g.
      Algorithms                                                                                                                              Efficient atomistic/quantum methods; ab-initio or molecular dynamics based topography simulations
                                                                          algorithms                            to box methods




                                                                                                    Open documented file formats (synatax
ADD   Tool interoperability                                       Documented file formats [10]      and semantics), exchangability of data
                                                                                                         between different tools [10]




                         Manufacturable solutions exist, and are being optimized
                                            Manufacturable solutions are known
                                                    Interim solutions are known    
                                      Manufacturable solutions are NOT known



          * For 2007/2008, interim solutions are known but research is still needed towards mature commercial solutions
          In this table, red stands for "*: “Solution not known, but this does not stop manufacturing”

          Notes for table
          [1] Non-standard final lens / standard resists
          [2] Non-standard final lens / non-standard resists
          [3] Models that at least roughly predict effects like oxygen vacancies and Hf-Si interface states are required, as those effects cause flatband shifts and fermi-level pinning. Currently there are no commercial tools
          available in a typical TCAD environment. Thus very phenomenological, a posteriori approaches are used. They are limited also to only some effects and by using models that were originally not designed for those
          effects.
         [4] “Alternative” refers to materials so far not prioritized in PIDS
         [5] Emphasis in topography steps shifted to material aspects towards long-term years
         [6] In Numerical Device Modeling equations are solved that are typically based on fundamental physics and describe the electrical behavior on spatially fine resolved quantities. This means usually partial
         differential equations (with respect to spatial coordinates) are employed. The goal is technology optimization and device insight
         [7] This row includes all aspects important for all devices, that is, especially classical CMOS bulk devices
         [8] In Circuit Element Modeling no spatially resolved models are used. Approximately analytically solveable, physically based models give guidance for the used relations between electrical quantities. The goal is
         a description of device behavior (currents, charges, noise) in circuit simulators
         [9] This refers to a minimum of functional sub-circuits
ADD   [10] Open and documented file formats are needed to enable the user to combine tools from different sources
     Table MS2B Modeling and Simulation Technology Requirements: Capabilities—Long-term Years

     Year of Production                               2016                   2017                   2018

     DRAM ½ Pitch (nm) (contacted)                     22                     20                     18
     MPU/ASIC Metal 1 (M1) ½ Pitch
                                                       22                     20                     18
     (nm) (contacted)
     MPU Physical Gate Length (nm)                      9                     8                       7
     Lithography
IS   Exposure                                                   NGL models and modeling of materials and components (immersion, EUV, ML2 lithog
     Resist models                                                                  Models for non-conventional photo-resists and coupling with etch
     Front End Process Modeling
     Gate Stack                                                                Modeling of new process steps / processing and properties of alternativ
     Diffusion and activation models                                                                             New technology needed

     Topography and Material Modeling

IS   Alternative material modeling                                            Atomistic material model for prediction of electrical, mechanical, thermal and reliab

     Equipment impact on process results          Computer engineered materials and process recipes; predictive manufacturability and yield; full p
     including material properties                                 equipment/feature scale modeling extended to include material information fro

     Numerical Device Modeling [6]
     Additional requirements for non-
                                                                               Nanoscale simulation capability including accurate atomistic and quan
     classical CMOS

     Additional requirements for devices
                                                                       Nanoscale simulation capability including accurate atomistic and quantum effec
     beyond non-classical CMOS

     Circuit Component Modeling [8]
     Active devices                                                                           Circuit models for nanoscale devices and interconnects
     Interconnects and integrated
                                                 Mixed electrical/optical simulation                                           Reliability prediction in couple
     passives
     Package Modeling
     Electrical modeling                                                                               Reliability prediction in coupled modeling
     Numerical analysis

                                                   Multi-scale simulation (atomistic-continuum); fast coupling of equipment-topography-electrical-re
     Algorithms
                                                                                                                  simulation



                   For footnotes, see short-term challenges table

             Manufacturable solutions exist, and are being optimized
                                Manufacturable solutions are known
                                        Interim solutions are known    
                           Manufacturable solutions are NOT known
Capabilities—Long-term Years

                                       2019                    2020                     2021     2022

                                        16                       14                      13       11

                                        16                       14                      13       11

                                        6.3                     5.6                       5       4.5


deling of materials and components (immersion, EUV, ML2 lithographic processes, imprint)
odels for non-conventional photo-resists and coupling with etch models


ng of new process steps / processing and properties of alternative materials
                           New technology needed



 c material model for prediction of electrical, mechanical, thermal and reliability problems

and process recipes; predictive manufacturability and yield; full process integration models. Integrated
ature scale modeling extended to include material information from the atomic scale



scale simulation capability including accurate atomistic and quantum effects


ulation capability including accurate atomistic and quantum effects for ERD and ERM



         Circuit models for nanoscale devices and interconnects

                                          Reliability prediction in coupled modeling


                 Reliability prediction in coupled modeling



c-continuum); fast coupling of equipment-topography-electrical-reliability models; hierarchical full-chip
                               simulation
            Table MS3         Modeling and Simulation Technology Requirements: Accuracy [1] and Speed —Near-term Years

            Year of Production                                                2007        2008        2009        2010        2011        2012        2013        2014        2015

            DRAM ½ Pitch (nm) (contacted)                                       65          57          50          45          40          36          32          28          25
            MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted)                      68          59          52          45          40          36          32          28          25
            MPU Physical Gate Length (nm)                                       25          23          20          18          16          14          13          11          10
            Technology development costs reduction potential if
DELETED TCAD is appropriately used [2]                                         40%         40%         40%         40%         40%         40%         40%         40%         40%

            Estimated technology development cost reduction from use of
   ADD      TCAD (average across best-practice cases reported by               27%         27%         30%         32%         35%         37%         n.a.        n.a.        n.a.
            industry) [2]
            Estimated technology development time reduction from use of
   ADD      TCAD (average across best-practice cases reported by               30%         30%         32%         34%         37%         39%         n.a.        n.a.        n.a.
            industry) [2]
            Lithography Modeling

            Absolute CD prediction accuracy (incl. OP effects) for dense
  WAS       and isolated lines – % of actual CD (=printed gate length) [3]
                                                                               3%          3%          3%          3%          3%          3%          3%          3%          3%


            Absolute CD prediction accuracy (incl. OP effects) for dense
    IS      and isolated lines – % of actual CD (=printed gate length) [3]
                                                                               3%          3%          1%          1%          1%          1%          1%          1%          1%

            Accuracy of sensitivity of CD vs. relevant technology
  WAS       parameters (dose, defocus, pitch, ….) [4]
                                                                               10%         10%         10%         10%         10%         10%         10%         10%         10%

            Accuracy of sensitivity of CD vs. relevant technology
    IS      parameters (dose, defocus, pitch, ….) [4]
                                                                               10%         10%         10%         10%         10%         10%         10%         10%         10%

            Front End Process Modeling
            General dopant profile accuracy (% of relevant distances like
   ADD      design rules)
                                                                               20%         20%         20%         20%         20%         20%         20%         20%         20%

            Vertical junction depth simulation accuracy (% of physical         10%         10%         10%         10%         10%         10%         10%         10%         10%
  WAS       gate length                                                      (2.5 nm)    (2.3 nm)    (2.0 nm)    (1.8 nm)    (1.6 nm)    (1.4 nm)    (1.3 nm)    (1.1 nm)    (1.0 nm)
            Vertical junction depth simulation accuracy (% of physical         10%         10%         10%         10%         10%         10%         10%         10%         10%
    IS      gate length of node) [5] [6]                                     (2.5 nm)    (2.3 nm)    (2.0 nm)    (1.8 nm)    (1.6 nm)    (1.4 nm)    (1.3 nm)    (1.1 nm)    (1.0 nm)
            Lateral junction depth simulation accuracy: (% of physical
  WAS       gate length
                                                                               5%          5%          5%          5%          5%          5%          5%          5%          5%

            Lateral junction depth simulation accuracy: (% of physical
    IS      gate length of node) [5] [6]
                                                                               5%          5%          5%          5%          5%          5%          5%          5%          5%

            Accuracy of sensitivity of junction depth with respect to
                                                                               5%          5%          5%          5%          5%          5%          5%          5%          5%
            implantation and anneal conditions [3]

  WAS       Total source/drain series resistance (accuracy of activation)      10%         10%         10%         10%         10%         10%         10%         10%         10%

    IS      Total source/drain series resistance (accuracy of activation)      10%         10%         10%         10%         10%         10%         10%         10%         10%

            Topography Modeling
  WAS       Wafer scale deposition/etching/CMP accuracy [4]                    5%          5%          5%          5%          5%          5%          5%          5%          5%
            Wafer scale deposition/etching/CMP planarization local
    IS      thickness accuracy [7]
                                                                               5%          5%          5%          5%          5%          5%          5%          5%          5%

            General 2D/3D topography accuracy (% accuracy of feature
  WAS       dimensions)
                                                                               5%          5%          5%          5%          5%          5%          5%          5%          5%

            General 2D/3D topography accuracy (% accuracy of feature
    IS      dimensions) [8]
                                                                               5%          5%          5%          5%          5%          5%          5%          5%          5%

            Gate 2D/3D topography accuracy (% accuracy of the MPU             1.80%       1.80%       1.80%       1.80%       1.80%       1.80%       1.80%       1.80%       1.80%
  WAS       physical gate length)                                            (0.45 nm)   (0.40 nm)   (0.36 nm)   (0.32 nm)   (0.29 nm)   (0.25 nm)   (0.23 nm)   (0,20 nm)   (0,18 nm)

            Gate 2D/3D topography accuracy (% accuracy of the MPU              2%          2%          2%          2%          2%          2%          2%          2%          2%
    IS      physical gate length) [8]
                                                                             (0.5 nm)    (0.46 nm)   (0.4 nm)    (0.36 nm)   (0.32 nm)   (0.28 nm)   (0.26 nm)   (0.22 nm)   (0.2 nm)

            Gate sidewall spacer 2D/3D topography accuracy (% accuracy        5.00%        NA          NA          NA          NA          NA          NA          NA          NA
DELETED of sidewall width)
                                                                             (1.4 nm)      NA          NA          NA          NA          NA          NA          NA          NA

            Interconnect 2D/3D topography accuracy (% accuracy                 5%          5%          5%          5%          5%          5%          5%          5%          5%
  WAS       of MPU/ASIC Metal 1 (M1) ½ Pitch
                                                                             (3.4 nm)    (3.0 nm)    (2.6 nm)    (2.3 nm)    (2.0 nm)    (1.8 nm)    (1.6 nm)    (1.4 nm)    (1.3 nm)

            Interconnect 2D/3D topography (including contacts, vias, …)        5%          5%          5%          5%          5%          5%          5%          5%          5%
    IS      accuracy (% accuracy of MPU/ASIC Metal 1 (M1) ½ Pitch
                                                                             (3.4 nm)    (3.0 nm)    (2.6 nm)    (2.3 nm)    (2.0 nm)    (1.8 nm)    (1.6 nm)    (1.4 nm)    (1.3 nm)
            Numerical Device Modeling [9]
  WAS       Ion accuracy                                                       3%          3%          3%          3%          3%          3%          3%          3%          3%
   IS       Ion accuracy                                                       5%          5%          5%          5%         5%         5%          5%          5%          5%
            Leakage current accuracy incl. S/D gate leakage and band-to
  WAS       band tunneling
                                                                               30%         30%         30%         30%         30%         30%         30%         30%         30%

   IS       log(Ioff) accuracy                                                 5%          5%          5%          5%          5%          5%          5%          5%          5%
  WAS       Length-dependent Vt accuracy (mV) [10]                            10 mV       7 mV        7 mV        7 mV        7 mV        7 mV        7 mV        7 mV        7 mV
   IS       Length-dependent Vt accuracy (mV) [8][10][11]                     10 mV       7 mV        7 mV        7 mV        7 mV        7 mV        7 mV        7 mV        7 mV
  WAS       Width-dependent Vt accuracy (mV) [12]                             10 mV       7 mV        7 mV        7 mV        7 mV        7 mV        7 mV        7 mV        7 mV

    IS      Width-dependent Vt accuracy (mV) [8][11][12][13]                  10 mV      7 mV       7 mV       7 mV      7 mV       7 mV       7 mV       7 mV      7 mV

            Accuracy of Gm and Gd at Vt +150mV versus L, Vbs, Vds
  WAS       and T
                                                                               10%         10%         10%         10%         10%         10%         10%         10%         10%

            Accuracy of peak Gm and Gd at Vt +150mV versus L, Vbs,
    IS      Vds and T
                                                                               10%         10%         10%         10%         10%         10%         10%         10%         10%

  WAS       Accuracy of ft and fmax                                            10%         10%         10%         10%         10%         10%         10%         10%         10%
            Accuracy of ft and fmax (if parasitics are known &
    IS      characterized)
                                                                               10%         10%         10%         10%         10%         10%         10%         10%         10%

  WAS       Gate leakage accuracy (% of Ig) [14]                               25%         25%         25%         25%         25%         25%         25%         25%         25%
   IS       Gate leakage accuracy (% of log(Ig)) [14]                          5%          5%          5%          5%          5%          5%          5%          5%          5%
            Circuit Element Modeling/ECAD [15]
  WAS       I-V error in saturation region                                     6%          5%          5%          5%          5%          5%          5%          5%          5%
   IS       I-V error in saturation region                                     6%          5%          5%          5%          5%          5%          5%          5%          5%
  WAS       I-V error in linear region                                         3%          3%          3%          3%          3%          3%          3%          3%          3%
   IS       I-V error in linear region                                         3%          3%          3%          3%          3%          3%          3%          3%          3%
  WAS       Leakage current incl. Ioff and gate current accuracy               10%         10%         10%         10%         10%         10%         10%         10%         10%
            Leakage currents: gate, junction, incl. Ioff and gate current
    IS      accuracy
                                                                               10%         10%         10%         10%         10%         10%         10%         10%         10%

  WAS       Intrinsic MOS C-V accuracy                                         5%          5%          5%          5%          5%          5%          5%          5%          5%
   IS       Intrinsic MOS C-V accuracy                                         5%          5%          5%          5%          5%          5%          5%          5%          5%
WAS   Parasitic C-V accuracy                                                5%              5%            5%              5%           5%               5%           5%              5%               5%
 IS   Parasitic C-V accuracy                                                5%              5%            5%              5%           5%               5%           5%              5%               5%
      Accuracy of Gm and Gd at Vt +150mV versus L, Vbs, Vds
WAS   and T
                                                                            10%             10%          10%             10%          10%               10%          10%            10%               10%

      Accuracy of Gm and Gd at Vt +150mV versus L, Vbs, Vds
IS                                                                          10%          10%            10%             10%          10%               10%          10%            10%               10%
      and T

WAS   Circuit delay accuracy (% of 1/maximum chip frequency)                5%              5%            5%              5%           5%               5%           5%              5%               5%

IS    Circuit delay accuracy (% of 1/maximum chip frequency)                5%            5%             5%              5%           5%               5%           5%              5%               5%

      Package Modeling

      Package delay accuracy (% of 1/off-chip clock frequency)              1%              1%            1%              1%           1%               1%           1%              1%               1%

IS    Temperature and stress distribution for package (accuracy)            3%              3%            3%              3%           3%               3%           3%              3%               3%


                          Manufacturable solutions exist, and are being optimized
                                              Manufacturable solutions are known
                                                          Interim solutions are known   
                                        Manufacturable solutions are NOT known



ADD   [1] Accuracy refers to models and tools calibrated to a certain technology (at a company), NOT to a certain experimen t.
      [2] This line does not give a quantitative assessment of the industrial requirement but gives the average of estimates obtained from companies on cost reductions in best practice cases through use of
      TCAD in development
IS    [3] CD averaged - LER and lens distortion not included. After calibration of resist parameters
      [4] Influence of process parameters on CD, etc. should be predicted with that maximum relative error: E.g. 10% accuracy of sensitivity means that if the experimental data change e.g. by 20% due to
IS
      change in process data, the prediction from simulation should be between 18 and 22%
ADD   [5] In comparison with experiments on wide-channel devices (averaging across channel width to get rid of effects of dopant fluctuations)
ADD   [6] In case of not fully reproducible experiments (due to hidden parameters e.g. in thermal profile): Comparison with mean value of experiments
      [7] For gate oxide this means atomistic precision
ADD   [8]Result of simulation should be within stripe extending on each sides of the experimental result by the value given
      [9] In Numerical Device Modeling equations are solved which are typically based on fundamental physics and describe the electrical behavior on spatially fine resolved quantities. This means usually
      partial differential equations (with respect spatial coordinates) are employed. The goal is technology optimization and device insight
      [10] Difference between simulated and measured Vth for different channel lengths
ADD   [11] Compared with median value of statistically meaningful samples.
      [12] Difference between simulated and measured Vth for different channel width
ADD   [13] ZEBRA throughout years because of prohibitive effort for 3D calibration
      [14] Not including effects of high-k / metal gate
      [15] In Circuit Element Modeling no spatially resolved models are used. Approximately analytically solveable, physically based models give guidance for the used relations between electrical
      quantities. The goal is a description of device behavior (currents, charges, noise) in circuit simulators.

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:13
posted:8/12/2012
language:English
pages:167