VHDL

Document Sample
VHDL Powered By Docstoc
					        ENG6090
Reconfigurable Computing
        Systems


Hardware Description Languages
   Part 3: Modeling Behavior


            ENG6090 RCS          1
Topics



   Process
   Sequential Statements
   Signals and Variables
   Sequential State Machines


                  ENG6090 RCS   2
Modeling Behavior

   Behavioral architecture
    – describes the algorithm performed by the module
    – contains
       »process statements, each containing
           sequential  statements (if-then, loop etc), including
           signal assignment statements
              – Signals are objects in VHDL
                used to model a carrier
           wait statements


                           ENG6090 RCS                      3
Basic Modeling Concepts


   External
  Interface
              d0
                        REG_4       q0
              d1
              d2                    q1
              d3      Internal
                                    q2
                    Functionality
              en                    q3
              clk


                     ENG6090 RCS         4
 Basic Modeling Concepts

External Interface modeled by “entity” VHDL construct.
           Entity name               Port name

           entity reg4 is
    Port     port (do,d1,d2,d3,en,clk : in bit;
                   qo,q1,q3,q4: out bit);
           end entity reg4;
                                            Port mode
    VHDL’87 vs. VHDL’93
                       ENG6090 RCS                 5
 Behavior Example
            architecture behav of reg4 is
            begin
Label          storage : process
                   variable stored_d0, stored_d1,
                              stored_d2, stored_d3 : bit;
               begin                                        Sequential
                   if en = '1' and clk = '1' then
Variable                                                    statements
                       stored_d0 := d0;
assignment             stored_d1 := d1;
                       stored_d2 := d2;
                       stored_d3 := d3;
                   end if;
 Signal            q0 <= stored_d0 after 5 ns;              Process is
 assignment        q1 <= stored_d1 after 5 ns;
                   q2 <= stored_d2 after 5 ns;              forever
 Wait              q3 <= stored_d3 after 5 ns;              active
                   wait on d0, d1, d2, d3, en, clk;
 statement
               end process storage;
            end architecture behav; RCS
                                 ENG6090                                 6
Sensitivity list & wait stmt


• Sensitivity list is equivalent to a “wait on” statement
  before the “end process” statement.
• VHDL requires that the process statement either
   • have a sensitivity list or
   • one or more wait statements.




                        ENG6090 RCS                 7
Process stmt: example

            Equivalent statements


 p1: process is            p2: process (a, b) is
 begin                     begin
    c <= a and b;             c <= a and b;
    wait on a, b;          end process;
 end process;

• If the model requires one or more wait statements
  inside a process description then we cannot use
  the sensitivity list construct.
                         ENG6090 RCS             8
    The Process Construct
   Statements in a process are executed sequentially

   A process body is structured much like conventional C function
     – Declaration and use of variables
     – if-then, if-then-else, case, for and while constructs
     – A process can contain signal assignment statements

   A process executes concurrently with other concurrent signal
    assignment statements

   A process takes 0 seconds of simulated time to execute and
    may schedule events in the future

   We can think of a process as a complex signal assignment
    statement!
                              ENG6090 RCS                        9
Wait statements

wait_stmt <=
  [ label : ] wait [ on signal_name{ , … } ]
                   [ until boolean_expr ]
                   [ for time_expr ] ;

wait on a, b, c;
wait until x = 1;
wait for 100 ns;


                      ENG6090 RCS              10
Wait for


• “Wait for” results in the process being suspended
  for the time specified in the construct.


                  wait for 10 ns;




                      ENG6090 RCS                11
 Wait on

• “Wait on” results in the process being suspended
  until an event takes place on any one of the signals.
• The list of signals is also called a sensitivity list.


half_adder: process is           half_adder: process (a, b) is
begin                            begin
    s <= a xor b after 10 ns;        s <= a xor b after 10 ns;
    c <= a and b after 10 ns;        c <= a and b after 10 ns;
    wait on a, b;                end process;
end process;

                          ENG6090 RCS                      12
 Wait until
wait until condition;

• In the simple case the condition expression must
  contain at least one signal (maybe more), say “s1”.
• The “wait until” construct is then interpreted
   as follows:
                                  ONLY WHEN
wait on s1 until condition; SENSITIVITY LIST
                                  IS EMPTY!!!
• The list of signals (similar to s1) is also called the
   sensitivity list.
                         ENG6090 RCS                 13
Concurrent Processes: Full Adder
                                s1
          In1                                                 sum
                    Half                  Half
                   Adder                 Adder
          In2                                            s2


          c_in                                                           c_out
                                        s3

          port     Internal signal
                                                 Model using processes


     Each of the components of the full adder
      can be modeled using a process
     Processes execute concurrently
      – In this sense they behave exactly like concurrent
        signal assignment statements
     Processes communicate via signals
                                     ENG6090 RCS                                 14
Concurrent Processes: Full Adder

library IEEE;
                                                    HA2: process(s1,c_in) is
use IEEE.std_logic_1164.all;
                                                    begin
                                                    sum <= (s1 xor c_in) after delay;
entity full_adder is
                                                    s2 <= (s1 and c_in) after delay;
port (In1, c_in, In2: in std_logic;
                                                    end process HA2;
      sum, c_out: out std_logic);
end entity full_adder;
                                                    OR1: process (s2, s3) -- process
                                                    describing the two-input OR gate
architecture behavioral of full_adder is
                                                    begin
signal s1, s2, s3: std_logic;
                                                    c_out <= (s2 or s3) after delay;
constant delay:Time:= 5 ns;
                                                    end process OR1;
begin
                                                    end architecture behavioral;
HA1: process (In1, In2) is
begin
s1 <= (In1 xor In2) after delay;
s3 <= (In1 and In2) after delay;
end process HA1;
                                      ENG6090 RCS                                  15
Variables vs. Signals: Example
proc1: process (x, y, z) is -- Process 1           proc2: process (x, y, z) -- Process 2
variable var_s1, var_s2: std_logic;                begin
begin                                              L1: sig_s1 <= x and y;
L1: var_s1 := x and y;                             L2: sig_s2 <= sig_s1 xor z;
L2: var_s2 := var_s1 xor z;                        L3: res2 <= sig_s1 nand sig_s2;
L3: res1 <= var_s1 nand var_s2;                    end process;
end process;




                     variables                                      signals




   Distinction between the use of variables vs. signals
                                           ENG6090 RCS                                     16
 Sequential Statements
These statements can appear inside a process description:
   • if-then-else
   • case
   • loop
        • infinite loop
        • while loop
        • for loop
   • assertion and report
   • variable assignments
   • signal assignments
   • function and procedure calls
                            ENG6090 RCS                     17
If statement
if sel = 0 then
    result <= input_0; -- executed if sel = 0
else
    result <= input_1; -- executed if sel /= 0
end if;

if sel = 0 then
    result <= input_0; -- executed if sel = 0
elseif sel = 1 then
    result <= input_1; -- executed if sel = 1
else
    result <= input_2; -- executed if sel /= 0, 1
end if;
                           ENG6090 RCS              18
If Statement: Example
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
port (In0, In1, In2, In3: in std_logic_vector (7 downto 0);
     Sel: in std_logic_vector(1 downto 0);
     Z : out std_logic_vector (7 downto 0));
end entity mux4;

architecture behavioral-3 of mux4 is                         Sensitivity List

process (Sel, In0, In1, In2, In3) is
variable Zout: std_logic;                   Use of variables rather than signals

begin
     if (Sel = “00”) then Zout := In0;
                                                   Variable Assignment
     elsif (Sel = “01”) then Zout := In1;
     elsif (Sel = “10”) then Zout := In2;
     else Zout:= In3;
     end if;
     Z <= Zout;
end process;
                                   ENG6090 RCS                                     19
Case stmt: example
type alu_func is (pass1, pass2, add, sub);
case func is                                    Alternatives
   when pass1 => res := op1;                    selected
   when pass2 => res := op2;                    based on the
   when add => res := op1 + op2;                value of func.
   when sub => res = op1 – op2;
end case;

type opcodes is (nop, add, sub, ld, st, jmp, br, halt);
case opcode is
   when ld | add | sub => op := mem_op;
   when st | jmp => op := add_op;
   when others => op := 0;
end case;                ENG6090 RCS                      20
Concurrent Processes: Half Adder
library IEEE;
use IEEE.std_logic_1164.all;

entity half_adder is
                                             carry_proc: process (a,b) is
port (a, b : in std_logic;
                                             begin
sum, carry : out std_logic);
                                               case a is
end entity half_adder;
                                                 when ‘0’ =>
                                                     carry <= a after 5 ns;
architecture behavior of half_adder is
                                                 when ‘1’ =>
begin
                                                    carry <= b after 5 ns;
sum_proc: process (a,b) is
                                                when others =>
begin
                                                   carry <= ‘X’ after 5 ns;
   if (a = b) then
                                              end case;
      sum <= ‘0’ after 5 ns;
                                             end process carry_proc;
  else
      sum <= (a or b) after 5 ns;
                                              end architecture behavior;
 end if;
end process;                      ENG6090 RCS                          21
  Null statement
• Case statement requires an alternative for every value.
• Sometimes no action is required for a particular value.
• No action is specified by a “null” statement

  null_stmt <= [ label : ] null ;

  case opcode is
    when add => acc = acc + op;
    when sub => acc = acc – op;
    when nop => null;
  end case;
                           ENG6090 RCS             22
Loop statements

 VHDL provides three types of loop or iterative
 constructs:
   • infinite loop
   • while loop
   • for loop




                     ENG6090 RCS                  23
Infinite loop
• Construct for specifying infinite iterations.
infinite_loop_stmt <=
     [ loop_label : ]
   loop
       { sequential_stmt }
    end loop [ loop_label ] ;

p1: process is
begin
    …… -- some steps to be done once
    loop
       ……
       -- steps to be executed infinite number of times
       ……
    end loop;
    wait;                     ENG6090 RCS                 24
end process;
Exit statement

 • Can be used to “exit” or “jump out” of any loop.

exit_stmt <=
    [ label : ]
   exit [ loop_label : ] [ when boolean_expr ] ;



           exit ; -- jumps out of the inner most loop



                           ENG6090 RCS                  25
 Exit stmt: examples
loop
   …
   exit ; -- jumps out of the inner most loop
     …
end loop;
……         -- exit causes the execution to start from this statement onwards
……

exit loop1; -- jumps out of loop
             -- with label loop1


exit when x = 1; -- jumps out of inner
                      -- most loop when
                      -- condition is true
                                   ENG6090 RCS                       26
 Next statement
• Causes the start of the next iteration of the loop
next_stmt <=
   [ label : ]
   next [ loop_label : ] [ when boolean_expr ] ;

loop
   A: ………
   …
   next ; -- causes the execution to start from stmt label A
   B: …… -- statement B and those following it are skipped
   …
end loop;
                               ENG6090 RCS                     27
While loop
• Construct for specifying conditional iteration.
while_loop_stmt <=
    [ loop_label : ]
   while boolean_expr loop
        { sequential_stmt }
    end loop [ loop_label ] ;


p1: process is
begin
    ……
    while x = y loop
       ……
       -- stmts that modify x or y or both.
       ……
    end loop;
    ……                        ENG6090 RCS           28
end process;
 For loop
• Construct for specifying deterministic iteration.

for_loop_stmt <=                              Loop
    [ loop_label : ]                          parameter
   for id in discrete_range loop
        { sequential_stmt }
    end loop [ loop_label ] ;
discrete_range <= expr ( to | downto ) expr

for count in 0 to 127 loop
   count_out <= count;
   wait for 5 ns;
end loop;
                          ENG6090 RCS                 29
For loop: rules


• Loop parameter is a constant inside the loop body.
• It can be used in an expression but not written to.
• Loop parameter is not required to be explicitly decl.
• Loop parameter’s scope is defined by the loop body.
• Consequently, it hides any variable of the same name
  inside the loop body.


                          ENG6090 RCS                    30
For loop: example

P1: process is
                                       Not Defined
   variable i, j: integer;
begin
   i := loop_param;         -- ERROR   Cannot Assign a
   for loop_param in 1 to 10 loop      Value
       …
       loop_param := 5;    -- ERROR
                                        Not Defined
       …
   end loop;
   j := loop_param;        -- ERROR
end process;
                      ENG6090 RCS                31
Attributes
       Data can be obtained about VHDL objects such as
        types, arrays and signals.
            object’ attribute
       Example: consider the implementation of a signal
                         value-time pair



              driver



   What types of information about this signal are useful?
    – Occurrence of an event
    – Elapsed time since last event
    – Previous value, i.e., prior to the last event
                             ENG6090 RCS                   32
Attributes
  library IEEE;
  use IEEE.std_logic_1164.all;

  entity dff is
  port (D, Clk : in std_logic;
  Q, Qbar : out std_logic);
  end entity dff;
                                          signifies a value change on signal clk
  architecture behavioral of dff is
  begin
    output: process is
    begin
      wait until (Clk’event and Clk = ‘1’); -- wait for rising edge
      Q <= D after 5 ns;
      Qbar <= not D after 5 ns;
  end process output;

  end architecture behavioral;
                                 ENG6090 RCS                                 33
Classes of Attributes
   Value attributes
     – returns a constant value

   Function attributes
     – invokes a function that returns a value

   Signal attributes
     – creates a new signal

   Type Attributes
     – Supports queries about the type of VHDL objects

   Range attributes
     – returns a range
                              ENG6090 RCS                34
Value Attributes
    Return a constant value
     – type statetype is (state0, state1, state2 state3);
        » state_type’left = state0
        » state_type’right = state3
   Examples

      Value attribute                          Value
      type_name’left       returns the left most value of type_name in its
                                            defined range
      type_name’right     returns the right most value of type_name in its
                                            defined range
      type_name’high     returns the highest value of type_name in its range
      type_name’low      returns the lowest value of type_name in its range
     array_name’length      returns the number of elements in the array
                                           array_name
                              ENG6090 RCS                              35
 Function Attributes
                                         Change
S’event : True if there is an event on S in the
          current simulation cycle, false otherwise.
                                          Assignment
S’active : True if there is an transaction on S in the
           current simulation cycle, false otherwise.
S’last_event : Time interval since the last event on S.
S’last_active : Time interval since the last transaction
                on S.
S’last_value : The value of S just before the last
               event on S.
                        ENG6090 RCS                  36
 Signal Attributes
S’delayed(T) : a signal with same values as S
               but delayed by time T.
S’stable(T) : a boolean signal that is true if
               there has been no event on S
               in the time interval T up to current time.
S’quiet(T)    : a boolean signal that is true if
               there has been no transaction on S
               in the time interval T up to
               current time.
S’transaction : a signal of type bit that changes value
                from ‘0’ to ‘1’ or vice versa every time
                there is a transaction on S.
                        ENG6090 RCS                37
Signal Attributes: Example
architecture behavioral of attributes is
begin
                                                 These are real (in simulation) signals and
 outdelayed <= data'delayed(5 ns);                 can be used elsewhere in the model
 outtransaction <= data'transaction;
end attributes;




                                   ENG6090 RCS                                                38
4-to-1 Multiplexer
entity mux is
  port (
    a, b, c, d: in std_logic;
    s: in std_logic_vector(1 downto 0);
    y: out std_logic);
end entity mux;
                                             a

                                             b
architecture mux1 of mux is
                                                                  y
begin                                        c
   process (a, b, c, d, s)
   begin                                     d
      case s is
        when "00“ => y <= a;
        when "01" => y <= b;
        when "10" => y <= c;
        when "11" => y <= d;                     S(1) S(0)
      end case;
   end process;
end architecture mux1;


                               ENG6090 RCS                   39
Sequential Logic: D-Flip Flop

architecture rtl of D_FF is
begin
  process (Clock, Reset) is
  begin                                       Flip-flop
    if Reset = ‘1’ then
                                        D     D       Q   Q
      Q <= ‘0’;
    if rising_edge(Clock) then
      Q <= D;                         Clock
                                                  R
    end if;
  end process;
                                      Reset
end architecture rtl;




                        ENG6090 RCS                           40
  Binary Counter
entity counter is
  generic (n : integer := 4);
  port (
     clk : in std_logic;
     reset: in std_logic;
     count: out std_logic_vector(n-1 downto 0)
  );
end entity counter;
                                     use ieee.numeric_std.all;

                                     architecture binary of counter is
                                     begin
                                       process (clk, reset)
                                         variable cnt : unsigned(n-1 downto 0);
      This example is not             begin
                                         if reset = '1' then -- async reset
       explicit on the primitives          cnt := (others => '0');
       that are to be used to            elsif rising_edge(clk) then
       construct the circuit.              cnt := cnt + 1;
                                         end if;
      The “+” operator is used          count <= std_logic_vector(cnt);
       to indicate the increment       end process;
       operation.                    end architecture binary;


                                    ENG6090 RCS                           41
State Machines
                                                         0/1
                      Combinational     Outputs
            Inputs         logic
                                             1/0    s0         s1   0/1

                                                         1/0
                                       Next state
                      State

                     Clk



    Basic components
      – Combinational component: output function and
        next state function
      – Sequential component
    Natural process-based implementation
                               ENG6090 RCS                                42
State Machine
process (cur_state, trigger, accept) is
begin
                                                        trigger
                                                   S0             S1
  case cur_state is
    when s0 =>
      active <= '0';
      if (trigger = '1') then
        next_state <= s1;                      accept     S2
      else
        next_state <= s0;
      end if;
    when s1 =>
      active <= '1';
      next_state <= s2;
    when s2 =>
      active <= '1';
      if (accept = '1') then
        next_state <= s0;
      else
        next_state <= s2;
      end if;
  end case;

end process;
                                 ENG6090 RCS                           43
 Example: State Machine                                        X=0
library IEEE;
use IEEE.std_logic_1164.all;                      X=1
entity state_machine is
                                                        S0         S1
   port(reset, clk, x : in std_logic;
   z : out std_logic);
end entity state_machine;                                               X=0

architecture behavioral of state_machine is                  X=1
type statetype is (state0, state1);
signal state, next_state : statetype := state0;
begin
    comb_process: process (state, x) is
    begin
       --- process description here
   end process comb_process;

  clk_process: process is
  begin
     -- process description here
  end process clk_process;               ENG6090 RCS                    44
end architectural behavioral;
Example: Clock Process

   clk_process: process is
   begin
     wait until (clk’event and clk = ‘1’); -- wait until the rising edge
      if reset = ‘1’ then -- check for reset and initialize state
          state <= statetype’left;
     else state <= next_state;
     end if;
   end process clk_process;
   end behavioral;




                                ENG6090 RCS                                45
Example: Output and Next
State Functions
  comb_process: process (state, x) is
  begin
     case state is -- depending upon the current state
       when state0 => -- set output signals and next state
          if x = ‘0’ then
             next_state <= state1;
             z <= ‘1’;
         else
             next_state <= state0;
             z <= ‘0’;
       end if;
      when state1 =>
        if x = ‘1’ then
           next_state <= state0;
           z <= ‘0’;
       else
           next_state <= state1;
           z <= ‘1’;
      end if;
   end case;
  end process comb_process;
                                    ENG6090 RCS              46
Summary and Recommednations
   The nature of concurrent and sequential statements is very
    different:
    – Concurrent statements are modeled after hardware, and thus there
      is a clear, direct mapping between a concurrent statement and a
      hardware structure.
    – Sequential statements are intended to describe the abstract
      behavior of a system (e.g. ASMs) and some constructs cannot be
      easily realized by hardware (loops!)
    – Sequential statements are more flexible and versatile than
      concurrent statements
   Variables should be used with care. A signal is generally
    preferred. A statement like n:= n+1 can cause confusion
    for synthesis.
   Think of the if and case statements as routing structures
    rather than as sequential control constructs.
    – An if statement infers a priority routing structure, and a large
      number of elsif branches leads to a long cascading chain.
                                ENG6090 RCS                              47
ENG6090 RCS   48
Process Behavior
     All processes are executed once at start-up
     Thereafter dependencies between signal values and
      events on these signals determine process initiation
     One can view processes as components with an
      interface/function
     Note that signals behave differently from variables!

library IEEE;                                            begin
use IEEE.std_logic_1164.all;                             L1: var_s1 := x and y;
                                                         L2: var_s2 := var_s1 xor z;
entity sig_var is                                        L3: res1 <= var_s1 nand var_s2;
port (x, y, z: in std_logic;                             end process;
res1, res2: out std_logic);
end entity sig_var;                                      proc2: process (x, y, z) -- Process 2
                                                         begin
architecture behavior of sig_var is                      L1: sig_s1 <= x and y;
signal sig_s1, sig_s2: std_logic;                        L2: sig_s2 <= sig_s1 xor z;
begin                                                    L3: res2 <= sig_s1 nand sig_s2;
proc1: process (x, y, z) is -- Process 1                 end process;
                                           ENG6090 RCS                                           49
variable var_s1, var_s2: std_logic;
                                                         end architecture behavior;

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:15
posted:8/12/2012
language:English
pages:49