8- Communicating by sherif.abas

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The ATmega16 communicates through one of
the following ways:
   Serial Peripheral Interface (SPI)

   Universal Synchronous and Asynchronous serial
    Receiver and Transmitter (USART)

   Two-wire Serial Interface (TWI) also known as I2C
1.   Serial Peripheral Interface (SPI):

allows high-speed synchronous data transfer between the
ATmega16 and peripheral devices (or between several AVR
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
●The Master initiates the communication cycle when pulling low the
Slave Select SS pin.
● Writing a byte to the Master Data Register (Master SPDR) starts
the clock on the SCK line. After shifting one byte, the clock stops,
and the flag SPIF is set. If the SPI interrupt enable bit (SPIE) is set,
an interrupt is requested, and the Master will synchronize the Slave
by pulling high the SS line.
●The system is single buffered in the transmit direction and double
buffered in the receive direction (data bytes to be sent can be
written only after the entire shift cycle is completed, while a
received character must be read from the SPI Data Register before
the next character has been completely shifted in).
►When in Slave Mode:
 SS- the Slave Select pin is always input, When SS is forced
  to low, the SPI is activated, and MISO becomes an output
  if configured so by the user.
 When SS is high again, all pins are inputs, and the slave
  will not receive incoming data. and drops any partially
  received data in the Shift Register.
SPI Registers:

• SPI Control Register:
• SPI Data Register – SPDR:

• Writing to the register initiates data transmission.
• Reading the register causes the Shift Register Receive buffer to
be read.
• SPI Status Register – SPSR:

 Bit 7: SPI Interrupt Flag:
• is set when a serial transfer is complete by Master and Slave
• is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, the SPIF bit is cleared by
first reading the SPI Status Register with SPIF set, then accessing
the SPI Data Register (SPDR).
• Bit6: Write Collision Flag is set if the Data Register is written
during a data transfer.
• Bit0: Double Speed Bit in master mode setting this bit will
double the freq of the clock.
SPI Settings By CodeVision Wizard
2. Universal Synchronous and Asynchronous
serial Receiver and Transmitter (USART)
• Full Duplex Operation .
•Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation.
• Supports Serial Frames with 5, 6, 7, 8, or 9 Databits
and 1 or 2 Stop Bits.
• Odd or Even Parity Generation.
• Three Separate Interrupts on TX Complete, TX Data
Register Empty and RX Complete.
Used by Synchr.

 Share same
 I/O register
• Mode Selection:
Asynchronous / Synchronous Operation

• Receiver/Transmitter Enable:
enables USART Receiver and/or USART Transmitter

• Character Size:
5,6,7,8 or 9 bit

• Bit 8 (9   th   Bit) location:
Since transmit and receive registers has only 8 bits;
Bit 1/0 in UCSRB-Reg (RXB8/TXB8) serve as Receive/Transmit
Data Bit 8 and must be read/written before the low byte)

•Stop Bit Select:
1Stop Bits / 2Stop Bits

• Parity Mode:
Parity disabled / Even Parity / Odd Parity

• USART Baud Rate
USART initializion:
The USART has to be initialized before any communication can take
place. The initialization process normally consists of setting the baud
rate, setting frame format and enabling the Transmitter or the
Receiver depending on the usage. For interrupt driven USART
operation, the Global Interrupt Flag should be cleared (and interrupts
globally disabled) when doing the initialization.
► The USART Transmitter:
oThe USART Transmitter is enabled by setting the Transmit Enable
(TXEN) bit.
oA data transmission is initiated by loading the transmit buffer with
the data to be transmitted.
oIf 9-bit characters are used (UCSZ = 7), the ninth bit must be
written to the TXB8 bit in UCSRB before the Low byte of the character
is written to UDR.
oThe transmitter has two flags: USART Data Register Empty (UDRE)
and Transmit Complete (TXC). They can generate interrupts.
oDisabling of the Transmitter (setting the TXEN to zero) will not
become effective until ongoing and pending transmissions are
►The USART Receiver:
oThe USART Receiver is enabled by setting the Receive Enable (RXEN)
oThe Receiver starts data reception when it detects a valid start bit
until the first stop bit of a frame is received. The Receiver will ignore a
second stop bit.
oIf 9-bit characters are used the ninth bit must be read from the RXB8
bit in UCSRB before reading the low bits from the UDR.
oThe Receive Complete (RXC) Flag. When the Receive Complete
Interrupt Enable (RXCIE) in UCSRB is set, the Receive Complete
Interrupt will be executed as long as the RXC Flag is set.
oDisabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost.
oThe USART Receiver has three error flags: Frame Error FE (is set
when the stop bit was incorrect), Data OverRun DOR (indicates data
loss due to a Receiver buffer full condition) and Parity Error (PE).
oBy Asynchr. Reception The clock recovery logic synchronizes internal
clock to the incoming serial frames.
USART Registers:

USART Data Register (UDR)

• The Transmit Data Buffer Register and the Receive Data Buffer
Registers share the same I/O address referred to as USART Data
Register or UDR.
USART Control and Status Register A (UCSRA)
USART Control and Status Register B (UCSRB)
USART Control and Status Register C (UCSRC)

Clock Polarity (UCPOL)
      UCPOL           Output of             Input on
                    TxD Pin Change       RxD Pin Sample
        0     Rising XCK Edge        Falling XCK Edge

        1     Falling XCK Edge       Rising XCK Edge
3. TWI (Two-wire Serial Interface):
• Simple Yet Powerful and Flexible Communication Interface.
• Only two Bus Lines Needed.
• Device can Operate as Transmitter or Receiver.
• Up to 400 kHz Data Transfer Speed.
• Noise Suppression Circuitry Rejects Spikes on Bus Lines.
• Address Recognition Causes Wake-up When AVR is in Sleep
• TWI protocol allows the interconnection of up to 128
• Uses only two bi-directional bus lines, clock (SCL=PC0) and
data (SDA=PC1), with a pull-up resistor connected to each of
the TWI open drain bus lines allowing wired-AND function.
The output drivers contain a slew-rate limiter.
• A transmission consists of a START condition, one or more
data packets and a STOP condition. The bus is considered
busy until the next STOP. A new START condition can be
issued between a START and STOP condition (REPEATED
START condition).
• The level of the data line must be stable when the clock
line is high.
Comparison bet. Communication Systems:
1. Application:

         For prephirals       bet.2 uC’s     Multi uC Comm.
SPI                                       (no addressing)
USART  easier by Synchr.                  (address+data)
TWI    difficult: needs Ack                (7bit address= 128
       + address decoding                  device

2. Duplex:

          SPI               USART             TWI
                                      R/W bit
3. Synchronous/Asynchronous:

                       Synchr.      Asynchr.
      SPI                             
      USART                           
      TWI                             

4. Number of Lines:

       SPI              USART               TWI
        4                 2/3                 2
5. Baud Rate:

SPI                 fosc/2 -> fosc/128
USART-Synchr.       fosc/2.(1->4096)
USART-Asynchr.      fosc/16.(1->4096)
normal mode
USART-Asynchr.      fosc/8.(1->4096)
double speed mode
TWI                 fosc/(16+2.(10-255).4**1,4,16,64)
                    (upto 400 Kbit/s)
6. Flags and Interrupts:
  Serial Transfer Complete (F+I)
  Write Collision (F)

  Transmitter - Data Register Empty (F+I)
  Transmitter – Transmit Complete (F+I)
  Receiver – Receive Complete (F+I)
  Receiver – Frame Error (F)
  Receiver – Data Overrun (F)
  Receiver – Parity Error (F)

  After Start (F+I)
  After SLA+R/W (F+I)
  After Master looses Arbitration (F+I)
  After Slave being addressed (F+I)
  After Receiving Data Bits (F+I)
  After Stop (F+I)
  By Bus Error (F+I)
  Choose: Data Order, Clock Polarity, Clock Phase

      Parity: even/odd/no
      Data Bits: 5/6/7/8/9
      Stop Bits: 1/2
      Clock Polarity

  •   Multi Master arbitration
  •   Each Step can generate an Interrupt asking for a response

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