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Issues and Constraints in Deep Submicron SRAM Design

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Issues and Constraints in Deep Submicron SRAM Design Powered By Docstoc
					FinFET SRAM Design

        Zheng Guo
        11/09/2004
Increase SRAM Stability

                             Need to broaden operating margin
                              or suppress variations.
                                 Cut/boost node voltages
                                      Difficult to apply and lower
                                       performance.
                                 Increase β-ratio
                                      Difficult to only forward bias NMOS.
                             New devices?

 Yamaoka, Hitachi, 2004
    Double-gate MOSFET
   Two gates achieve greater channel control.
        Improved drive current from higher mobility and steeper sub-
         threshold swing.
   More Scalable than a single gate Ultra-thin body (UTB)
    SOI device.

                                              Gate
               Gate
                                     Source          Drain     TSi
    Source               Drain
         Body/Halo Doping                     Gate
  Thin-body double gate MOSFETs

           Gate length = Lg
                                                   Gate length = Lg
 Source




                                          Source
          Gate Fin Width = T
                            Si
                                                                      Gate2
                                                                      Vth Control
                                                   Gate1
               Drain




                                                            Drain
                       Fin Height   Switching                       Fin Height
                       HFIN = W/2   Gate                             HFIN = W


                                         Back-gated (BG) MOSFET
Double-gated (DG) MOSFET             •   Independent front and back gates
                                     •   One switching gate and Vth control
                                         gate
       Compact Device Model
                                                7E-04                                                                        7E-04
                                                              BG-PMOS                                                                        BG-NMOS
   Semi-empirical device model                 6E-04                                                                        6E-04



    based on a subset of BSIM3
                                                5E-04                                                                        5E-04




                                                                                                               Ids [A]
                                    Ids [A]
                                                4E-04                                                                        4E-04

   Captures the effect of supply               3E-04                                                                        3E-04


    change, threshold shift,                    2E-04                                                                        2E-04



    mobility enhancement
                                                1E-04                                                                        1E-04

                                                0E+00                                                                    0E+00

    Parameters can be used to                           -1     -0.8       -0.6          -0.4   -0.2   0                       0.00            0.20         0.40         0.60     0.80   1.00
                                                                                                                                                             Vds [V]
                                                                         Vds [V]
    create Spectre AHDL models                                                                                                 K VGS  VTH   VDS
                                                                                                                                             2
                                                                                                                                                                                 
                                                                                                          I DSAT                              1                               
    for DC simulation                                             Ec LVGS  VTH                                             VGS  VTH  EC L 
                                                                                                                                                   VA                           
                                                                                                                                                                                 
                                                   VDSAT 
                                                                  EC L  VGS  VTH                                       2 KVDS VGS  VTH  0.5VDS   VDS 
                                                                                                      I DLIN                                         1 
                                                                                                                                                             
                                                                                                                                 VDS  EC L               VA 
                                                                                                                                                              
                                                7E-04                                                                          7E-04
                                                             BG-PMOS Ids vs. Vgs, Vbg                                                        BG-NMOS Ids vs. Vgs, Vbg
                                                6E-04                                                                          6E-04

                                                5E-04                                                                          5E-04

                                                4E-04                                                                          4E-04
                                      Ids [A]




                                                                                                                   Ids [A]
                                                                          dVth = 350mV/V                                                     dVth = 300mV/V
                                                3E-04                                                                          3E-04
                                                                                    g


                                                2E-04                                                                          2E-04

                                                1E-04                                                                          1E-04

                                                0E+00                                                                         0E+00
                                                        -1        -0.8            -0.6         -0.4   -0.2                             0.2           0.4          0.6          0.8      1
                                                                                 Vds [V]                                                                      Vds [V]
6T SRAM Cell
                   All FETs double-gated.
                    1.20E+00


               
                    1.00E+00



                    8.00E-01



                    6.00E-01



                    4.00E-01



                    2.00E-01



                    0.00E+00
                          0.00E+00        2.00E-01     4.00E-01     6.00E-01    8.00E-01    1.00E+00    1.20E+00



                         1.20E+00


                  Access NFETs back-gated w/
                         1.00E+00



                   feedback to dynamically
                         8.00E-01



                   increase β-ratio by
                    VR
                         6.00E-01



                   weakening access NFETs.
                         4.00E-01




                  All other FETs double-gated.
                         2.00E-01




                         0.00E+00
                               0.00E+00     2.00E-01     4.00E-01    6.00E-01    8.00E-01    1.00E+00   1.20E+00
                                                                        VL
4T SRAM Cell

                             Data retention leakage current
                              usually need to be at least
                              1000xIleakage to compensate for
                              the widely fluctuating leakage
                              current.
                             Data retention leakage current
                              flows on both sides but only
 Yamaoka, Hitachi, 2004
                              needs to flow in one side for
                              dataretention.
4T SRAM Cell
                  All FETs double-gated.
                          1.20E+00



                          1.00E+00



                           8.00E-01



                           6.00E-01



                           4.00E-01



                           2.00E-01



                          0.00E+00
                    -2.00E-01 0.00E+00        2.00E-01     4.00E-01     6.00E-01        8.00E-01    1.00E+00    1.20E+00

                          -2.00E-01



                              1.20E+00




                  Access PFETs back-gated w/
                              1.00E+00




                   feedback to selectively increase
                              8.00E-01




                   compensation current and to
                              6.00E-01




                    VR
                   dynamically increase β-ratio.
                              4.00E-01



                              2.00E-01



                  All other FETs double-gated.
                               0.00E+00
                         -2.00E-01 0.00E+00     2.00E-01     4.00E-01        6.00E-01    8.00E-01    1.00E+00   1.20E+00


                             -2.00E-01
                                                                        VL
4T Write Issue
                                       1.20E+00



                                       1.00E+00



                                       8.00E-01


   When writing to a neighboring      6.00E-01



    cell (sharing common bit-lines),   4.00E-01



    ICOMP is reversed and will         2.00E-01



    discharge the “1” storage node!    0.00E+00
                                             0.00E+00   2.00E-11   4.00E-11   6.00E-11   8.00E-11   1.00E-10   1.20E-10



    Level of discharge depends on VT
                                       -2.00E-01



    of the access PMOS transistors.    1.20E+00



        Use high VT devices.          1.00E+00


                                       8.00E-01


                                       6.00E-01


                                       4.00E-01


                                       2.00E-01



                                       0.00E+00
                                             0.00E+00   2.00E-11   4.00E-11   6.00E-11   8.00E-11   1.00E-10   1.20E-10

                                       -2.00E-01
4T Write Issue
                                                                                                                   1.20E+00


1.20E+00
                                                                                                                   1.00E+00

1.00E+00
                                                                                                                   8.00E-01
8.00E-01

                                                                                                                   6.00E-01
6.00E-01




                                                                                                         VR
                                                                                                                   4.00E-01
4.00E-01


2.00E-01                                                                                                           2.00E-01


0.00E+00
                                                                                                                    0.00E+00
      0.00E+00 2.00E-11 4.00E-11 6.00E-11 8.00E-11 1.00E-10 1.20E-10 1.40E-10 1.60E-10 1.80E-10               -2.00E-01 0.00E+00   2.00E-01   4.00E-01        6.00E-01   8.00E-01   1.00E+00   1.20E+00
-2.00E-01
                                                                                                                  -2.00E-01
                                                                                                                                                         VL
1.20E+00


1.00E+00


8.00E-01                                                                                                             Moderate VT access
6.00E-01                                                                                                              devices
4.00E-01
                                                                                                                     110 surface conduction
2.00E-01


0.00E+00
      0.00E+00   2.00E-11   4.00E-11   6.00E-11   8.00E-11   1.00E-10   1.20E-10   1.40E-10   1.60E-10
-2.00E-01
  4T Write Issue
                                                                                                                         1.20E+00

 1.20E+00
                                                                                                                         1.00E+00
 1.00E+00

 8.00E-01                                                                                                                8.00E-01


 6.00E-01
                                                                                                                         6.00E-01




                                                                                                               VR
 4.00E-01
                                                                                                                         4.00E-01
 2.00E-01

0.00E+00                                                                                                                 2.00E-01
      0.00E+00    2.00E-11   4.00E-11    6.00E-11   8.00E-11    1.00E-10    1.20E-10    1.40E-10    1.60E-10
-2.00E-01
                                                                                                                          0.00E+00
                                                                                                                    -2.00E-01 0.00E+00   2.00E-01   4.00E-01        6.00E-01   8.00E-01   1.00E+00   1.20E+00
-4.00E-01
                                                                                                                        -2.00E-01
                                                                                                                                                               VL

1.20E+00


1.00E+00

8.00E-01
                                                                                                                           High VT access devices
6.00E-01


4.00E-01
                                                                                                                           110 surface conduction
2.00E-01
                                                                                                                           WL=-0.2V on Read/Write.
0.00E+00
      0.00E+00   2.00E-11    4.00E-11   6.00E-11    8.00E-11   1.00E-10    1.20E-10    1.40E-10    1.60E-10
-2.00E-01


-4.00E-01
Layouts
    6T Cell       4T Cell




  6.6um X 8um   5um X 8um

				
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