CMOS Device Model by yurtgc548


									         CMOS Device Model
• Objective
  – Hand calculations for analog design
  – Efficiently and accurately simulation
• CMOS transistor models
  – Large signal model
  – Small signal model
  – Simulation model
  – Noise model
            Large Signal Model
• Nonlinear equations for solving dc values of
  device currents given voltages
• Level 1: Shichman-Hodges (VT, K', g, l, f, and
• Level 2: with second-order effects (varying
  channel charge, short-channel, weak inversion,
  varying surface mobility, etc.)
• Level 3: Semi-empirical short-channel model
• Level 4: BSIM models. Based on automatically
  generated parameters from a process
  characterization. Good weak-strong inversion
Transconductance when VDS is small
Transconductance when VDS is small
Transconductance when VDS is small
Effect of changing VDS for a large VGS
Effect of changing VDS for a given VGS
Effect of changing VDS for a given VGS
  Effect of changing VDS for various VGS

Effect of changing VDS for various VGS
Effect of changing VDS for various VGS
       MOST Regions of Operation
• Cut-off, or non-conducting: VGS <VT
  – ID=0
• Conducting: VGS >=VT
  – Saturation: VDS > VGS – VT
                iD          (vGS - VT )2
  – Triode or linear or ohmic or non-saturation: VDS <=
    VGS – VT
                  μCoxW                  2
           iD                          VDS
                        ((vGS - V )VDS - 2 )
  With channel length modulation

     iD          (vGS - V ) ( 1  λVDS )


VT  VT 0  g ( 2|φ f |  |vBS| - 2|φ f | )

              μCoxW      W
                   K'
                L        L
Capacitors Of The Mosfet
CBD and CBS include both the diffusion-bulk
junction capacitance as well as the side wall
junction capacitance. They are highly nonlinear
in bias voltages.

C4 is the capacitance between the channel and
the bulk. It is highly nonlinear and depends on
the operation of the device. C4 is not
measurable from terminals.
Gate related capacitances
Small signal
Typically: VDB, VSB are in such a way that there is
a reversely biased pn junction.

Therefore:    gbd ≈ gbs ≈ 0
In saturation:

In non-saturation region
High Frequency Figures of Merit wT
• AC current source input to G
• AC short S, D, B to gnd
• Measure AC drain current output
• Calculate current gain
• Find frequency at which current gain = 1.
• Ignore rs and rd,  Cbs, Cbd, gds, gbs, gbd all have
  zero voltage drop and hence zero current
• Vgs = Iin /jw(Cgs+Cgb+Cgd) ≈ Iin /jwCgs
• Io = − (gm − jw Cgd)Vgs ≈ − gmVgs
• |Io/Iin| ≈ gm/wCgs
• At wT, current gain =1
• wT ≈ gm/(Cgs+Cgd)≈ gm/Cgs
• or
    High Frequency Figures of Merit wmax

•   AC current source input to G
•   AC short S, D, B to gnd
•   Measure AC power into the gate
•   Assume complex conjugate load
•   Compute max power delivered by the transistor
•   Find maximum power gain
•   Find frequency at which power gain = 1.
• wmax: frequency at which power gain
  becomes 1

                    BSIM models
• Non-uniform charge density
• Band bending due to non-uniform gate voltage
• Non-uniform threshold voltage
   – Non-uniform channel doping, x, y, z
   – Short channel effects
      • Charge sharing
      • Drain-induced barrier lowering (DIBL)
   – Narrow channel effects
   – Temperature dependence
• Mobility change due to temp, field (x, y)
• Source drain, gate, bulk resistances
      “Short Channel” Effects
• VTH decreases for small L
  – Large offset for diff pairs with small L
• Mobility reduction:
  – Velocity saturation
  – Vertical field (small tox=6.5nm)
  – Reduced gm: increases slower than root-ID
          Threshold Voltage VTH
• Strong function of L
  – Use long channel for VTH matching
  – But this increases cap and decreases speed

• Process variations
  – Run-to-run
  – How to characterize?
  – Slow/nominal/fast
  – Both worst-case & optimistic
    Effect of Velocity Saturation
• Velocity ≈ mobility * field
• Field reaches maximum Emax
  – (Vgs-Vt)/L reaches ESAT
• gm become saturated:
  – gm ≈ ½mnCoxW*ESAT
• But Cgs still 2/3 WL Cox
• wT ≈ gm/Cgs = ¾ mnESAT /L
• No longer ~ 1/L^2
          Threshold Reduction
• When channel is short, effect of Vd extends to S
• Cause barrier to drop, i.e. Vth to drop
• Greatly affects sub-threshold current: 26 mV Vth
  drop  current * e
• 100~200 mV Vth drop due to Vd not uncommon
   100s or 1000 times current increase

• Use lower density active near gate but higher
  density for contacts
                 Other effects
• Temperature variation
• Normal-Field Mobility Degradation
• Substrate current
  – Very nonlinear in Vd
• Drain to source leakage current at Vgs=0
  – Big concern for static power
• Gate leakage currents
  – Hot electron
  – Tunneling
  – Very nonlineary
• Transit Time Effects
     Consequences for Design
• SPICE (HSPICE or Spectre)
  – BSIM3, BSIM4 models
  – Accurate but inappropriate for hand analysis
  – Verification (& optimization)
• Design:
  – Small signal parameter design space:
     • gm, CL      (speed, noise)
     • gm/ID, ID   (power, output range, speed)
     • Av0= gmro   (gain)
  – Device geometries from SPICE (table, graph);
  – may require iteration (e.g. CGS)
Intrinsic voltage gain of MOSFET
 Sweep V1
 Measure vgs

 Intrinsic voltage gain = gm/go = Dvds/Dvgs for constant Id
                Electronic Noise
• Noise phenomena
• Device noise models
• Representation of noise (2-ports):
  –   Motivation
  –   Output spectral density
  –   Input equivalent spectral density
  –   Noise figure
  –   Sampling noise (“kT/C noise”)
• SNR versus Bits
• Noise versus Power Dissipation
  – Dynamic range
  – Minimum detectable signal
     Noise in Devices and Circuits
•Noise is any unwanted excitation of a circuit, any
input that is not an information-bearing signal.
• External noise: Unintended coupling with other
parts of the physical world; in principle, can be
virtually eliminated by careful design.
• Intrinsic noise: Unpredictable microscopic events
inherent in the device/circuit; can be reduced, but
never eliminated.
•Noise is especially important to consider when
designing low-power systems because the signal
levels (typically voltages or currents) are small.
      Noise vs random process
• random process variations
  – Variations from one device to another
  – For any device, it is fixed after fabrication
• Noise
  – Unpredictable variations during operation
  – Unknown after fabrication
  – Remains unknown after measurement during
  – May change with environment
Time domain description of noise
What is signal and what
is noise?
    Signal and noise power:
        x(t )  s(t )  n(t )
    1 T 2
Ps   s (t ) dt, S (rms)  Srms  Ps
    T 0
    1 T 2
Pn   n (t ) dt, N (rms)  N rms  Pn
    T 0
      Physical interpretation
If we apply a signal (or noise) as a voltage
source across a one Ohm resistor, the power
delivered by the source is equal to the signal

Signal power can be viewer as a measure of
normalized power.

      Signal to noise ratio
                   Ps               S rms
  SNR  10 log 10 ( )  20 log 10 (       )
                   Pn               N rms
SNR = 0 dB when signal power = noise power

Absolute noise level in dB:
w.r.t. 1 mW of signal power
         Pn in dB m  10 log
                     30 dB  10 log( Pn )
               SNR in bits
• A sine wave with magnitude 1 has power
  = 1/2.
• Quantize it into N=2n equal levels between
  -1 and 1 (with step size = 2/2n)
• Quantization error uniformly distributed
  between +–1/2n
• Noise (quantization error) power
     =1/3 (1/2n)2
• Signal to noise ratio
     = 1/2 ÷ 1/3 (1/2n)2 =1.5(1/2n)2
     = 1.76 + 6.02n dB or n bits

C=0: n1 and n2 uncorrelated
 C=1: perfectly correlated

For independent noises
   Frequency domain description of
   Given n(t) stationary, its autocorrelation is:
                               1 T
               Rn ( )  lim
                        T   2T
                                 T n(t )n(t   ) dt
   The power spectral density of n(t) is:
                  PSDn ( f )  S n ( f )  F ( Rn ( ))
                       Pn          PSDn ( f ) df

For real signals, PSD is even.  can use single sided
spectrum: 2x positive side
                      Pn           PSDn ( f ) df
                                     ↑ single sided PSD
Parseval’s Theorem:
         If              x(t )  X ( f )
                          2                      2
                     x(t ) dt  
                                            X ( f ) df

If x(t) stationary,
                           Rx ( )  PSDx ( f )
                   T        2                  
        T    
                        x(t ) dt  Rx (0)  
                                                     PSDx ( f ) df
Interpretation of PSD

                 Pxf1 = PSDx(f1)

            Types of “Noise”
• “man made”
  – Interference
  – Supply noise
  – Use shielding, careful layout, isolation, …
• “intrinsic” noise
  – Associated with current conduction
  – “fundamental” –thermal noise
  – “manufacturing process related”
  – flicker noise
                Thermal Noise
• Due to thermal excitation of charge carriers in a
  conductor. It has a white spectral density and is
  proportional to absolute temperature, not
  dependent on bias current.

• Random fluctuations of v(t) or i(t)
• Independent of current flow
• Characterization:
   – Zero mean, Gaussian pdf
   – Power spectral density constant or “white” up to about
   Thermal noise dominant in

R = 1kΩ, B = 1MHz, 4µV rms or 4nA rms
Equivalently, we can model a real resistor with an
ideal resistor in parallel with a current noise source.
What rms value should the current source have?

Show that when two resistors are connected in
series, we can model them as ideal series resistors
in series with a single noise voltage source. What’s
the rms value of the voltage source?

Show that two parallel resistors can be modeled as
two ideal parallel resistors in parallel with a single
noise current source. What’s the rms value of the
current source?
              Noise in Diodes
Shot noise dominant
– DC current is not continuous and smooth but
   instead is a result of pulses of current caused by
   the individual flow of carriers.
It depends on bias, can be modeled as a
white noise source and typically larger than
   thermal noise.
   − Zero mean
   – Gaussian pdf
   – Power spectral density flat
   – Proportional to current
   – Dependent on temperature
ID= 1mA, B = 1MHz, 17nA rms
MOS Noise Model
Flicker noise
 –Kf,NMOS 6 times larger than Kf,PMOS
 –Strongly process dependent
 −when referred to as drain current noise, it
  is inversely proportional to L2
BJT Noise
             Sampling Noise
• Commonly called “kT/C” noise
• Applications: ADC, SC circuits, …


     Filtering of noise
 x(t)                        y(t)

|H(f )|2 = H(s)|s=j2pf H(s)|s=-j2pf
            Noise Calculations
1) Get small-signal model
2) Set all inputs = 0 (linear superposition)
3) Pick output vo or io
4) For each noise source vx, or ix
   Calculate Hx(s) = vo(s) / vx(s) (or … io, ix)
5) Total noise at output is

6) Input Referred Noise: Fictitious noise source at
                  2         2               2
               v in ,eff    on,T   / A(s)
Example: CS Amplifier
VDD              Von=(inRL +inMOS)/goT

  RL             goT = 1/RL + sCL

  M1    CL
                 nRL    4 k BT
             nMOS       4k BT g m
Some integrals
     In the previous example, if the transistor is
     in triode, how would the solution change?

     If we include the flicker noise source, how
     would that affect the computation? What do
     you suggest we should modify?
 In the example, if RL is replaced by a PMOS
 transistor in saturation, how would the
 solution change? Assume appropriate bias

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