In the basic two stage opamp

							                                   Department of Electronic
                           97.588 Signal Processing Electronics
                                      Final Examination
December 6, 1999 5:30PM - 7:00PM                                        R. Mason
Answer all questions on sheets provided
___________________________________________________________________________

1.    (5 points)   Multiple Choice - Choose Best Answer

(a)   Which of the following is NOT an opamp specification?
            (i)    IX
            (ii)   CMRR
            (iii) ROUT
            (iv) VOS
(b)   Why do we use clocked comparators?
            (i)    reduce charge injection
            (ii)   increase voltage gain
            (iii) reduce offset voltage
            (iv) increase input impedance
(c)   What is the typical gain of a standard folded cascode CMOS opamp?
            (i)    10 dB
            (ii)   25 dB
            (iii) 50 dB
            (iv) 100 dB
(d)   A major source of error in CMOS sample and hold circuits is:
            (i)    loop gain
            (ii)   charge injection
            (iii) input offset voltage
            (iv) sample period
(e)   An ideal 7 bit A/D with a full scale sinusoid input would have an SNR of:
            (i)    43.9 dB
            (ii)   42.14 dB
            (iii) 0 dB
            (iv) 32.14 dB

2.    (15 points) Short Answer
(a)   What are typical values of RIN, open loop unity gain frequency, settling time, and CMRR
      for the basic two stage CMOS opamp?




(b)   In the basic two stage opamp, what effect does the miller capacitor Cc have on the
      frequency response? What happens if we decrease the value of Cc ?
(c)   What is lead compensation? Why would we use a transistor in triode region instead of a
      resistor for lead compensation?




(d)   Why would you use a wide swing cascode current mirror?




(e)   In the folded cascode opamp, why do we use folded structure? What is drawback of folded
      cascode?




(f)   What is the purpose of common mode feedback circuits in fully differential opamps?




(g)   How can you reduce charge injection effects in clocked comparators?




(h)   Explain the meaning of sampling jitter in a sample and hold circuit?
(i)   How can you increase the output impedance of a standard cascode current mirror?




(j)   Why can't we just increase the size of the hold capacitor in a CMOS sample and hold
      circuit to reduce charge injection?




(k)   For an ideal A/D converter, what are the range of input values that will produce the same
      digital output?




(l)   Why do we use 2's complement numbers for signed converters (i.e. both positive and
      negative values)




(m)   In a sample and hold circuit charge injection due to the channel charge causes distortion.
      Why?




(n)   What are the advantages of an R-2R ladder D/As compared to a binary weighted resistor
      network D/As?




(o)   Why do we use thermometer codes?
3.    (5 points)   Explain the purpose of each component in the circuit below.




4.     (5 points)  The sample and hold circuit below has a number of desirable properties in
terms of input impedance, distortion, offset voltage, slew rate and isolation. Explain the purpose
of each component and if and how it affects the above properties.
5.    (5 points)What type of circuit is this below? Explain how voltage offset and clock
feedthrough errors are reduced in this circuit.




6.    (5 points)   What sampling time uncertainty can be tolerated for a 16-bit A/D converter
operating on an input signal from 0 - 20KHz?