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Defect Reduction Technology Program - Download as PowerPoint by SEBuk0


									         ITRS - YE ITWG

Conference in San Francisco (USA)
          July 14, 2009

   L. Pfitzner,

                                                     San Francisco July 14, 2010   1
Scope of Yield Enhancement
• Aspects                                                                  45 nm high-k metal gate
                                                                           transistor. Presented by
    – Manufacturing of integrated                                          Mark Bohr (Intel) 02/2009

      semiconductor devices: numerous
      processing steps building the 3D
      structure of the chip (e.g. 9 Cu and low –
      k interconnect layers for 32 nm)                                     45 nm ramp production was
                                                                           the fastest
    – Yield: percentage of operating chips at                              Presented by Mark Bohr
      the end of the manufacturing process                                 (Intel) 02/2009

• Components
    – Determination and control of
    – Inspection of structures and critical
    – Model to predict and calculate yield
      based on historic contamination levels
      (particulate and metals) and defects
                                                     Gordon Moore: “There is no fundamental
    – Determination of kill ratios: Correlation
                                                   obstacle to achieving device yields of 100%.”
      between defects and yield                              (Electronics, 38 (8), 1965)

                                                                               San Francisco July 14, 2010   2
Objectives of Yield Enhancement
• collect defect data
 – tools for inspection and root
   cause analysis
 – automated defect              process        process                   process
   classification and filtering module 1        module 2                  module k
 – inspection strategy                                                                k
                                  wafer             wafer                     wafer
• yield management
 – software
 – objective: to correlate data
   and find excursions                                       defect
 – predict yield
                                           inspection and collection of data
• defect data excursions                                    defect
 – define specs                                             classiffication
 – procedure for clarification         review, characterization, metrology

                                                                                 San Francisco July 14, 2010   3
Defects and Failure Mechanisms
•   processes: litho, etch thin film
    implantation, planarization,                    overlay
                                                                                 ESD                Interconnects
    cleaning,…                                                                   Damage
•   faults and problems: defects                                                                         Metal 2
    as e.g. particles, flatness,
    layer properties, patterns,                                Via                particle        open
                                                           Metal 1
•   challenges                                   particle                                    layer thickness
      – yield and defect map in 2 D
      – root cause analysis                              p+        n                         n+      p           p
        requires 3 D                                                                              COP
      – model, predict, and forecast                          n-well                                 contamination
        yield  YM&DB                                                            interfaces: roughness, state
      – requires fast and non-                                                   density, charges
        destructive inspection
        (defect density) and
        metrology (root cause
        analysis) for 2D and 3D
        structures  DDC                         Si crystal: stacking faults, contamination, stress,
      – requires preventive defect               COP (crystal originating particles), epi defects
        and contamination control
         WECC
                           (YM&DB: defect budget and yield modelling - DDC:

                                                                                                           San Francisco July 14, 2010   4
Organization of the Chapter 2010
 •   Chair: Lothar Pfitzner (Fraunhofer IISB)
     Co-Chair: Dilip Patel (ISMI)

 •   Difficult Challenges
              • Table YE 2
 •   Technology Requirements and Potential Solutions
       - Yield Learning (YL – not active in 2010)
              • Chair: N.N.; Contributors to be defined by Samsung, AMAT
       - Yield Model and Defect Budget (YMDB – not active in 2010)
              • Chair: Sumio Kuwabara (Renesas) - Japan
              • Table YE 3, (2 deleted tables – defect budgets)
       - Defect Detection and Characterization (DDC)
              • Chair: N.N. (A. Nutsch and D. Patel) – Europe and US
              • Table YE 4, YE 5, YE 6
       - Wafer Environment Contamination Control (WECC)
              • Chair: Kevin Pate (Intel) – USA, Andreas Neuber (AMAT) -
              • Table YE 7

                                                                     San Francisco July 14, 2010   5
2010 YE ITWG Contributors
Europe                                                       Korea (not confirmed)                       United States
         Lothar Pfitzner ( chair, Fraunhofer IISB )
         Andreas Neuber (c-chair, AMAT )                              Sang Kyun Park ( Magna Chip )
                                                                                                                Dilip Patel ( co-chair, ISMI )
         Dieter Rathei ( DDC, DR Yield )                              Jinsung Kim ( Samsung )
                                                                                                                Barry Gotlinsky ( WECC, Pall )
         Francois Finck ( DDC, ST )                                   Lim Jaewoong ( Samsung )                  Biswanath Roy ( WECC, Pall )
         Barry Kennedy ( DDC, Intel )                                 Incheol Baek ( Dongbu HiTek )             Bob Latimer ( WECC, Hach )
         Andreas Nutsch ( DDC, Fraunhofer IISB )                                                                Chris Muller ( WECC, Purafil, Inc. )
         Ines Thurner ( DDC, Smart Industry Partners )                                                          Dan Fuchs ( WECC, BOCE )
         Jan Cavelaars ( DDC, NXP )                                                                             Dan Wilcox ( WECC, Replipoint Technologies )
         Mathias Haeuser (DDC, Infineon)
         Delphine Gerin ( WECC, ST Crolles )
                                                             Taiwan                                             David Blackford ( WECC, Fluid Measurement
                                                                      Victor Liang ( , TSMC )                         Technologies )
         Astrid Gettel ( WECC, GLOBALFOUNDRIES )                                                                David Roberts ( WECC, Nantero )
         Christoph Hocke ( WECC, Infineon Technologies )              YCHuang Huang ( , TSMC )
                                                                                                                Drew Sinha ( WECC, Siltronic )
         Michael Otto ( WECC, Fraunhofer IISB )                       Ray Yang ( , UMC )                        Dwight Beal ( WECC, PMS )
         Matthias Pfutterer ( WECC, M+W Group )                       Mao-Hsiang Yen ( , Winbond )              James McAndrew ( WECC, Air Liquide )
         Hubert Winzig ( WECC, Infineon )                             Cherng Guo ( , MXIX )                     Jeff Chapman ( WECC, IBM )
         Francesca Illuzzi ( WECC, Numonyx )                                                                    Jeff Hanson ( WECC, Texas Instruments )
         Hans Jansen ( WECC, ASML )                                                                             John DeGenova ( WECC, Texas Instruments )
         Jost Kames ( WECC, artemis control AG )             Malaysia                                           John Kurowski ( WECC, IBM )
         Arnaud Favre ( WECC, Adixen )                                Guillaume Gallet ( WECC, Camfil)          Keith Kerwin ( WECC, TI )
                                                                                                                Kevin Pate ( co-chair, Intel )
Japan                                                                                                           Larry Rabellino ( WECC, SAES )
         Sumio Kuwabara ( YMDB, Renesas )                                                                       Marc Camenzind ( WECC, Balazs-AirLiquide )
         Hiroshi Nagaishi ( DDC, Renesas )                                                                      Rich Riley ( WECC, Intel )
         Masashi Hamanaka ( DDC, Panasonic )                                                                    Rick Godec ( WECC, Ionics Instruments )
         Takahiro Tsuchiya ( DDC, Fujitsu Semiconductor )
         Yoshitaka Tatsumoto ( DDC, Lasertec )
         Masahiko Ikeno ( DDC, Hitachi High-Technologies )
                                                                  Thank you                                     Sarah Schoen ( WECC, Balazs-AirLiquide )
                                                                                                                Scott Anderson ( WECC, Balazs-AirLiquide )
                                                                                                                Slava Libman ( WECC, M+W Group )
         Mutsuhiro Amari ( WECC, Entegris )                                                                     Suhas Ketkar ( WECC, APCI )
         Takashi Futatsuki ( WECC, Organo )
         Teruyuki Hayashi ( WECC, TEL )
         Katsunobu Kitami ( WECC, Kurita )
                                                                  very much!                                    Terry Stange ( WECC, Hach Ultra Analytics )
                                                                                                                Tony Schleisman ( WECC, Air Liquide )
                                                                                                                Val Stradz ( WECC, Intel )
         Kaoru Kondoh ( WECC, Rion )                                                                            Wai-Ming Choi ( WECC, Entegris )
         Yasuhiko Matsumoto ( WECC, Rohm )                                                                      William Moore ( WECC, IBM )
         Fumio Mizuno ( WECC, MEISEI University )                                                               Milton Goldwin ( DDC, ISMI )
         Kazuo Nishihagi ( WECC, HORIBA )
         Koichiro Saga ( WECC, SONY )
         Yoshimi Shiramizu ( co-chair, Renesas )
         Isamu Sugiyama ( WECC, NOMURA )
         Ken Tsugane ( WECC, HITACHI )
         Hidehiro Masuko ( WECC, ShinEtsu )

                                                                                                                                      San Francisco July 14, 2010   6
2010 Key Challenges
The Yield Enhancement community is challenged by the following topics:

• Near Term (>16 nm)
    – Detection and identification of Small Yield Limiting Defects from Nuisance -
      Detection of multiple killer defects and their simultaneous differentiation at high capture
      rates, low cost of ownership and high throughput. It is a challenge to find small but yield
      relevant defects under a vast amount of nuisance and false defects.
    – Non-Visual Defects and Process Variations – Increasing yield loss due to non-visual
      defects and process variations requires new approaches in methodologies, diagnostics
      and control. This includes the correlation of systematic yield loss and layout attributes.
      The irregularity of features in logic areas makes them very sensitive to systematic yield
      loss mechanisms such as patterning process variations across the lithographic process
    – 3D Inspection – For inspection tools the capability to inspect high aspect ratios but also
      to detect non-visuals such as voids, embedded defects, and sub-surface defects is
      crucial. The need for high-speed and cost-effective 3D inspection tools becomes crucial
      as the importance of 3D defect types increases.
    – Process Stability vs. Absolute Contamination Level – Including the Correlation to
      Yield Test structures, methods and data are needed for correlating defects caused by
      wafer environment and handling with yield. This requires determination of control limits
      for gases, chemicals, air, precursors, ultrapure water and substrate surface cleanliness.

                                                                                 San Francisco July 14, 2010   7
2010 Key Challenges
The Yield Enhancement community is challenged by the following topics:

•   Long Term (<16 nm)
      – Next Generation Inspection - As bright field detection in the far-field loses its ability
         to discriminate defects of interest, it has become necessary to explore new
         alternative technologies that can meet inspection requirements beyond 16 nm node.
         Several techniques should be given consideration as potential candidates for
         inspection: high speed scanning probe microscopy, near-field scanning optical
         microscopy, interferometry, scanning capacitance microscopy and e-beam. This
         pathfinding exercise needs to assess each technique’s ultimate resolution,
         throughput and potential interactions with samples (contamination, or degree of
         mechanical damage) as key success criteria.
      – Inline Defect Characterization and Analysis – Alternatives to Energy Dispersive
         X-ray Spectroscopy systems are required for high throughput in-line characterization
         and analysis for defects smaller than feature sizes. The data volume to be analyzed
         is drastically increasing, therefore demanding for new methods for data
         interpretation and to ensure quality.
      – Development of model-based design-manufacturing interface — Due to Optical
         Proximity Correction (OPC) and the high complexity of integration, the models must
         comprehend greater parametric sensitivities, ultra-thin film integrity, impact of circuit
         design, greater transistor packing, etc.

                                                                                    San Francisco July 14, 2010   8
Update 2010
 • Overall
    – confirmation of key challenges
    – deleted 450 mm as a new challenge
    – ISMI  to organize a new defect budget survey

 • DDC
    – adjust tables to ORCT input
    – update colours and numbers

 • DB & YL
    – outline for defect budget survey presented
    – discuss non–visible defects
    – Tables were deleted (not up to date)

                                                      San Francisco July 14, 2010   11
Update 2010
      Focus items (Ultrapure Water, Chemicals, Gas, Airborne/Surface
      Molecular Contamination and Cleanroom)

    – Particles: Measurement, composition, critical size, identify yield
      correlation, deposition models
    – Organics: Measurement, speciation, identify yield correlation,
      deposition models
    – Ionic, metallic and other molecular contamination: Deposition
      risk assessment methodology and model
    – Gases and CVD/ALD precursor contamination control
      requirements: measurement, control and impact assessment
    – Airborne and Surface Molecular Contamination: integrated
      control concept (carrier and mini-environment), metrology
      requirements, deposition models and impact assessments

                                                               San Francisco July 14, 2010   12
Activities 2010

 • Setup of ITRS Forums  in operation and used for

 • Defect Budget Survey (ongoing)
     – outline for defect budget survey (see )
     – Contributors defined in Japan, Europe, and US

                                                       San Francisco July 14, 2010   13
YE involvement of ANNA
 Input generation by ANNA (European Integrated
 Activity of Excellence and Networking for Nano and
 Micro- Electronics Analysis)
    – ANNA integrates analytical infrastructures (
        • virtual distributed joint laboratory (8 laboratories accredited
          according ISO 17025)
        • development of analytical techniques for semiconductor
        • driven by quality requirements such as comparability of techniques
          and methods but also by the challenge of pushing metrology and
          analytical techniques to the limits
        • involvement of industry, research organisations and academia
    – Inputs for ITRS:
        • Contributions for Standardization (ISO and DIN)
        • Metrology Challenges
        • Input to be delivered by IDM and wafer manufacturers

                                                                 San Francisco July 14, 2010   14
ANNA Contributions for Standardization
 • The production of relevant reference material and
    – References for trace analysis were produced and characterized

    – Ultra-short pulsed laser deposition (PLD) of Ni was used in reference
      free SR-TXRF analysis

    – B, As, Si implanted samples were produced at depths and
      concentrations for ultra shallow junctions

    – To investigate nanocrystals HfO2 and HfSiO2 films were made for
      measurements of thickness and stoichiometry

    – For strain in device processing, epitaxial wafers were used to produce
      standard samples for CBED analysis

    – Standard samples for nanocrystals characterization were developed

                                                                  San Francisco July 14, 2010   15
ANNA – YE/Metrology Challenges
• ANNA prepares and/or encourages standards for

   – Highly sensitive detection of inorganic contamination from Li to U.

   – Comprehension of organic contamination of wafer surfaces

   – Metrology for depth distribution of Ultra Shallow Junctions

   – Nanofilms Characterization

   – Crystal defects and strain in device processing

   – Nanocrystal Characterization:

                                                               San Francisco July 14, 2010   17
ITRS-SEMI Alignment on Ultrapure Water Spec
• UPW ITRS group identified limitations of use of
  ITRS tables for design UPW facilities – ITRS
  enables future technologies
• Collaboration between UPW ITRS group and SEMI
  resulted in development of new UPW quality guide
  (SEMI F063)
   – F063 is a guide providing advanced Semiconductor Fabs with
     information required for setting internal specifications
   – F063 is based on ITRS risk assessment
   – F063 considers UPW treatment technology and metrology
   – F063 takes into account economical viability
   – The agreement is that F063 be updated every two year,
     maintaining ITRS pace
   – The SEMI TF is attempting to align the F063 with ASTM

                                                        San Francisco July 14, 2010   19
Summary July 2010
 Development / Improvement of the Yield Enhancement

    – Addition of new key challenges
        • integrated AMC concept (together with Factory Integration),
        • next generation inspection
    – ISMI / SEMATECH outlined a defect budget survey:
        • request to get support from IDMs (Asia, US, Europe) and TWG as
          FEP, Interconnect, Litho,….
        • presentation survey outline available
    – European IDMs committed to work on IDM contribution to the
      survey and chairing DDC - Defect Detection and

                                                                 San Francisco July 14, 2010   20

 Development/ Improvement of the
 Yield Enhancement chapter

    – Reflection of current status and future requirements needs
      subsequent adjustment of outline and content of the chapter

    – Request to IDMs, ESIA, JEITA, KSIA, SIA, TSIA, ISMI,
      academia contributing to ITRS:
        • assure that sufficient contributors and resources are
        • surveys required for future updates e.g. DB&YM

                                                             San Francisco July 14, 2010   21

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