Thesis Presentation by s2939Sm

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									Design of Sub-mW RF CMOS
Low-Noise Amplifiers



Derek Ho
Dept. of Electrical and Computer Engineering
University of British Columbia

March 30, 2007
Outline
 Motivation and Objectives
 Device Characteristics
 Design Methodology
 90nm 2.4GHz LNA Design and Results
 Conclusion and Future Work




                                       2
Introduction
   What is an LNA?
    A circuit used to provide gain where preserving
    the signal-to-noise ratio is important

   Where can I find one?
    In wireless/wireline receivers and sensor
    interfaces

   Why ultra-low-power?
    Want a long battery life for portable/remote
    applications and implants



                                                      3
LNA Requirements
                                                     Receive Chain
                                   1   2   3   4



               VDD

              Ld        Ctune
                           RFout
         VB        M2
        Lg
 RFin              M1
        Cm

              Ls




              Noise figure of receiver (F = noise figure, G = gain):


                      Ideally low
              (for data rate and range)
                                                                       4
LNA Requirements
       Output
                         Ideal

                                 Better Linearity


                           Worse Linearity




                                             Input

   An LNA with good linearity can handle a larger
   input signal without deviating from linear operation.



                                                           5
LNA Design Challenges
                        Tightly Coupled
                         Performance
                           Tradeoff
          Lack of
        Systematic                         Complex Simulation
       Analog Design                       (Noise/Nonlinearity)
        Technique


  Stringent Power                                   Low-Q On-chip
      and Area                                        Inductors
   Requirement

                        LNA Design
                                                 Complex
    Shrinking Supply                             MOSFET
        Voltage                                   Models

                        MOSFET Low
                       Output Resistance

                                                                    6
Research Objectives
Devise a simple methodology that leads to
 power-efficient LNA designs
- Form a graphical toolkit to help reduce design time and improve design quality
- Explore LNA power-performance tradeoffs
- Find a low-voltage low-power circuit topology
- Demonstrate a high performance design in a deep submicron technology




                                                                               7
Outline
 Motivation and Objectives
 Device Characteristics
 Design Methodology
 90nm 2.4GHz LNA Design and Results
 Conclusion and Future Work




                                       8
Gain and Transconductance
                                   Advantage of graphical approach: Quicker, more accurate
       “gain / frequency response vs. bias”                                                                                                                                “gain vs. bias”
                         250                                                                                                                   50
                                                                                                                                                        20/0.1
                                    20/0.1                                                  (20/0.1), (40/0.1)




                                                                                                                                                                               moderate inversion
                                                             moderate inversion
                                                                                                                                               45
                                                                                                                                                        40/0.1




                                                                                                                                                                                                                    strong inversion
                                    40/0.1




                                                                                                  strong inversion
                         200                                                                                                                   40       40/0.2
                                    40/0.2




                                                                                                                                     m [mS]
   Transit Freq. (GHz)




                                                                                                                                               35
f [GHz]


                                    subthreshold




                                                                                                                                                          subthreshold
                         150                                                                                                                   30




                                                                                                                                    ggm [mS]
                                                                                                                                               25

                         100                                                                                                                   20
      T




                                                                                                                                               15

                         50                                                                                                                    10

                                                                                                                                               5
                                                                                                                     (40/0.2)
                          0                                                                                                                    0
                               0                   0.2         0.4                          0.6                 0.8             1                   0                0.2         0.4                          0.6                      0.8   1
                                                                                  VGS [V]                                                                                                           VGS [V]
                                                             VGS [V]                                                                                                              VGS [V]

                                                        Both fT and gm are strong functions of VGS
                                                        fT a strong function of L, but largely independent of W
                                                        MOSFET has poor subthreshold performance

                                                                                                                                                                                                                                                 9
Transconductance Efficiency gm/ID
                                  35
                                                                                                                              20/0.1




                                                                moderate inversion
                                  30                                                                                          40/0.1




                                                                                                     strong inversion
                                                                                                                              40/0.2



                  gmgm/ID [1/V]
                                  25

                    /ID [1/V]

                                           subthreshold
                                  20

                                  15

                                  10

                                  5

                                  0
                                       0                  0.2      0.4                         0.6                      0.8            1
                                                                                     VGS (V)
                                                                 VGS [V]

   First proposed in 1996 for op-amp (low-frequency) design [1]
   Represents “gain achieved” per unit “power consumed”
   Decreases towards strong inversion
   Insensitive to W and L
     can first design VGS (bias) then design W (size)

                                                                                                                                           10
                                             moderate
                                             inversion
Linearity
                                                     strong inversion




                              subthreshold

                                                    VGS [V]
                    VIP3 of a 40nm nFET vs. VGS (VTH = 0.23V) [22]



   VIP3 (measure of linearity, the greater the better) is the highest at
    moderate inversion (around 0.25V for the 45nm FET).



                                                                            11
Outline
 Motivation and Objectives
 Device Characteristics
 Design Methodology
 90nm 2.4GHz LNA Design and Results
 Conclusion and Future Work




                                       12
Circuit Topology
      Common-Source                                     Cascode
                                                               VDD
                   VDD
                                                              Ld        Ctune
                  Ld        Ctune
                                                                          RFout
                              RFout                      VB        M2
             Lg
  RFin                 M1                                Lg
            Cm                                RFin                 M1
                                                        Cm
                  Ls                                          Ls



Problems with common-source                           Cascode Design:
- Low device output resistance  low gain             Lg, Ls, Ld, Cm, Ctune,
- Poor input/output isolation  Instability          VB, VGS1, W1/L1, W2/L2


                                                                                  13
Transistor Sizing for Noise
                      10
                                                        Cascode NF
                       9
                                                        CS NF
                       8

                       7
                                    Cascode
            NF [dB]
                       6
          NFLNA[dB]

                                    Common-Source
                       5

                       4
                       3

                       2

                       1

                       0
                           0   20   40     60      80   100      120
                                          W [μm]
                                         W [μm]
        NF of LNA improves with larger W
        However, power proportional to W
         Noise-power tradeoff
                                                                       14
Design Procedure
Step 1: Choose the bias VGS                               Design Sweet Spot

Selection criteria:                                       50

                                                          45
                                                                   20/0.1
                                                                   40/0.1
                                                          40       40/0.2


1)   Tradeoff gm (gain) and gm/ID (power)                 35

                                                          30




                                               gm [mS]
                                                          25



2)   For noise, want low VGS for a large                  20

                                                          15

                                                          10                                              gm
     W but avoid subthreshold operation                   5

                                                          0
                                                               0            0.2   0.4             0.6     0.8            1
                                                                                        VGS [V]


3)   For linearity, exploit high VIP3                     35

                                                          30
                                                                                                                20/0.1
                                                                                                                40/0.1
                                                                                                                40/0.2
                                                          25




                                            gm/ID [1/V]
                                                          20
                                                                                                        gm/ID
 Bias the device in moderate inversion
                                                          15

                                                          10

                                                           5

                                                           0
                                                               0            0.2   0.4             0.6     0.8            1
                                                                                        VGS (V)




                                                                                                                15
Design Procedure
Step 2: Calculate ID
   ID = (Power) / (Supply voltage)

Step 3: Transistor Sizing (Find W)
                      (VGS  VTH ) 2
   I D  Wv sat Cox                     (1  VDS )
                    (VGS  VTH )  Ec L

Step 4: Find gm
   gm=d(ID)/d(VGS), or by simulation


                                                      16
Design Procedure
Step 5: Determine gate-source cap Cgs
   Decide whether adding Cm is beneficial Cm decreases
   fT but alleviate the need to build large inductors

                                                     VDD

                                                    Ld        Ctune
                                                                 RFout
                                               VB        M2
                                              Lg
                                       RFin              M1
                                              Cm

                                                    Ls
                                Cgs = Cm || Cgs1

                                                                         17
Design Procedure
Step 6: Impedance matching
   Design Lg, Ls, & Cm to create a 50Ω input impedance.
                                                            Small-signal model
                                                              Zin
               1                       g L
      Z in          j ( Ls  L g )  m s                         Lg                  +
             jC gs                     C gs           Rs                Cm    Cgs1     Vgs
                                                                                        -
                                                                                                   gmVgs

                                                      υRF                                Ls
                      g m Ls
        e{Z in }            Rs  50
                       C gs                                                    VDD

                                                                              Ld        Ctune
                       1
        m{Z in }            ( Ls  L g )  0                                           RFout
                      C gs                                          VB
                                                                    Lg
                                                                                   M2

                                                           RFin                    M1
                                                                     Cm

                                                                              Ls
                                               Designing
                                                                                                           18
Design Procedure
Step 7: Design the load Ld and Ctune
   Ld, Ctune and the parasitic caps at the output
   should resonate at the frequency of
   operation                                 Designing
                                                              VDD
   Ld is often chosen as large as it can                     Ld        Ctune
   practically be implemented to increase gain                            RFout
                                                        VB        M2
                                                       Lg
                                                RFin              M1
                                                       Cm

                                                             Ls




                                                                         19
Outline
 Motivation and Objectives
 Device Characteristics
 Design Methodology
 90nm 2.4GHz LNA Design and Results
 Conclusion and Future Work




                                       20
A 90nm 2.4GHz LNA
                              VDD

                             Ld        Ctune
                                          RFout
                        VB        M2
                       Lg
                RFin              M1
                       Cm

                             Ls



   Cascode with on-chip inductors
   1V supply  can share with digital
   We now proceed to LNA (circuit-level) design…


                                                    21
Gain
                                           “gain vs. bias”                                         “gain vs. size”
              25                                                                         25
                         Subthreshold Region




              24                                                                         24

              23                                                                         23
  AvA [dB]




                                                                              AvA[dB]
                                                                                  [dB]
       [dB]




              22                                                                         22




                                                                                   v
        v




              21                                                                         21

              20                                                                         20

              19
                                                           Power                         19                         Power
              18                                                                         18
                   0.3                         0.4       0.5     0.6   0.7                    10   15   20     25     30   35   40
                                                       VGS [V]                                               W [μm]
                                                     VGS [V]                                             W [μm]

              Gain insensitive to VGS                                        Gain does not scale well with W




                                                                                                                                     22
                                                                  NF vs. f (sweeping VGS)
                                                                   10


  Noise                                                                9
                                                                       8




                                                                                                            3V
                                                                       7




                                                                                                          0.
                                                             NF [dB]




                                                                                                          S=
                                                                       6




                                                                                                         G
                                                                                                     V
                                                                       5
                         Noise Summary                                 4
                                                                                       Power              =0
                                                                                                            .4 V
                                                                                                     V GS 0.5V
                                                                       3              Increase       V GS
                                                                                                         =
                                                                                                             V
                                                                                                        =0.6
                                                                                                   V GS .7V
                                                                       2                                 0
                                                                                                   V GS=
             Top 5 Noise Contributors:                                 1
                    1 (9.2%)                                                1   1.5    2     2.5     3             3.5
                    2 (8.6%)                4                                          f [GHz]
                    3 (8.2%)        Ctune           Ld
                    4 (7.3%)
                                                         VGS 0.4-0.7V: -0.6dB at 6.4x power
40% of total
           noise 5 (5.5%)                       3
(76% of which                                                           NF vs. f (sweeping W)
                                                                       10
comes from the R’s            Lg                                        9

in the inductors)                                                       8
                                            1




                                                                                                           m
                                                                                                         0μ
                                                                        7
                                   5                                                   Power




                                                                                                    =1
          (52%)




                                                             NF [dB]
                  Rsrc




                                                                                                   W
                                                                        6

                                       2                                5
                                                                                      Increase         0μ
                                                                                                         m
                                                                                                    =2
                                                                                                   W μm
                                                                        4                             30
                                                                                                   W=
                                                                                                       0μm
                                                                        3                          W=4

     Meaning: Need to make inductors                                    2

                                                                        1
     with low series resistance!                                            1   1.5    2     2.5     3             3.5
                                                                                       f [GHz]

                                                         W 10-40μW: -3.4dB at 4.2x power
                                                                                                                         23
Linearity
                               “LNA linearity vs. bias”
                         8
                                                        Power
                         6
            IIP3 [dBm]



                         4
          IIP3 [dBm]


                                                           Adjusted W
                         2


                         0
                                             Constant W
                         -2


                         -4
                              0.4   0.45   0.5   0.55     0.6   0.65    0.7

                                              VGS
                                             VGS[V]
                                                  [V]                         40nm



Linkage between LNA performance
and device characteristic

                                                                                     24
Simulation Results
                               2.4 GHz
                                                                            TABLE 2
   Gain: 22.7dB                                                     Summary of LNA Performance
                25                                  5                  Gain (dB)     22.7

                20                                  4.5                NF (dB)        2.8
                                                                       S11 (dB)      −14.7




                                                          NF [dB]
      Av [dB]




                15                                  4
                                                                       IIP3 (dBm)    5.14
                10                                  3.5
                                                                       P1dB (dBm)    −10
                5                                   3                  PDC (μW)       943        Power: 943μW
                0                                   2.5
                                                                       fc (GHz)       2.4
                     1.5   2      2.5     3   3.5
                                                                       Gate L (μm)   0.09
                                f [GHz]
Noise: 2.8dB




                                                                                                           25
Component Values

                   VDD                VDD (V)        1
                                      Lg = Ld (nH)   5
                  Ld        Ctune     Ls (nH)        2
                              RFout   Cm (fF)        480
             VB        M2
                                      Ctune (fF)     720
             Lg
      RFin             M1             W1/L1 (μm)     25/0.1
             Cm
                                      W2/L2 (μm)     25/0.1
                  Ls                  Vin,DC (V)     0.4
                                      VB (V)         0.9


All components can be conveniently implemented on-chip!
                                                              26
Performance Comparison
                                                                                < 1mW
                                                                                > 1mW
                30
                         Best
                25                                   This Thesis
                                       > 1mW
                20
    Gain (dB)




                                                        [15], ‘05
                15                                                   [9], ‘06       [8], ‘05
                                [14], ‘06   [10], ‘05
                                                   [13], ‘05            [12], ‘06
                10
                                                                    [11], ‘04       < 1mW
                5
                                                                                    Worse
                0
                     0             1           2               3                4              5
                                            Noise Figure (dB)
                    This work (simulated) vs. others (measured)
                    This work focuses on design methodology
                    Highest gain amongst all LNAs
                    Good noise figure amongst sub-mW LNAs
                                                                                                   27
Outline
 Motivation and Objectives
 Device Characteristics
 Design Methodology
 90nm 2.4GHz LNA Design and Results
 Conclusion and Future Work




                                       28
Conclusion
   A design methodology was devised for sub-mW RF
    CMOS LNAs having the following benefits:
    1) simple to apply
    2) can serve as a starting point for local optimization
    3) based on the fundamental device properties
   The gm/ID approached previously used for low-frequency
    op-amp design was adopted for radio-frequency design
   A 2.4GHz 943μW LNA was designed with only manual
    design optimization



                                                          29
Future Work
Enhancements to the proposed methodology:
 Incorporate a quantitative noise analysis into the gm/ID
   design framework
 Account for process variation and DFM concepts
 Silicon verification
Interesting/high-impact research areas:
 Noise optimization technique for the ultra-low-power
   design space
 Further exploitation of high FET linearity in moderate
   inversion


                                                             30
Related Publications
 1.   D. Ho and S. Mirabbasi, “Design considerations for
      Sub-mW CMOS RF low-noise amplifiers,” to appear
      in IEEE Canadian Conference on Electrical and
      Computer Engineering, 2007.
 2.   D. Ho and S. Mirabbasi, “Low-voltage low-power
      low-noise amplifier for wireless sensor networks,”
      IEEE Canadian Conference on Electrical and
      Computer Engineering, 2006.




                                                      31
References
[1]    F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based methodology for the design of CMOS analog
       circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE J. Solid-State
       Circuits, vol. 31, no. 9, Sep. 1996.
[2]    T.-K. Nguyen, S.-K. Han, and S.-G. Lee, “Ultra-low-power 2.4GHz image-rejection low-noise amplifier,”
       Electronics Letters, vol. 41, no. 15, July 2005.
[3]    D. B. G. Perumana, S. Chakraborty, C.-H. Lee, and J. Laskar, “A fully monolithic 260-μW, 1-GHz subthreshold
       low noise amplifier,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 6, Jun 2005.
[22]   Ming Cai, “Design studies of nanometer-gate low-noise amplifier near the limits of CMOS scaling,” Doctor of
       Philosophy Thesis, University of California, San Diego, San Diego, CA, 2006.
[28]   S. B. T. Wang, A. M. Niknejad, and R. W. Brodersen, “Design of a sub-mW 960-MHz UWB CMOS LNA,” IEEE
       J. Solid-State Circuits, vol. 41, no. 11, Nov. 2006.
[29]   D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P.
       Wambacq, S. Donnay, and S. Decoutere, “Low-power 5 GHz LNA and VCO in 90nm RF CMOS,” IEEE Sym.
       on VLSI Circuits, June 2004.
[30]   S. Asgaran, M. J. Deen, and C.-H. Chen, “A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance
       used for input matching,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 4, Apr. 2006.
[31]   L.-H. Lu, H.-H. Hsieh, and Y.-S. Wang, “A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier,” IEEE
       Microwave and Wireless Components Letters, vol. 15, no. 10, Oct. 2005.
[32]   T.-S. Kim and B.-S. Kim, “Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD
       sinker,” IEEE Microwave and Wireless Component Letters, vol. 16, no. 4, Apr. 2006.
[33]   M. Shouxian, M. Jian-Guo, Y. K. Seng, and D. M. Anh, “A modified architecture used for input matching in
       CMOS low-noise amplifiers,” IEEE Trans. on Circuits and Systems II, vol. 52, no. 11, Nov. 2005.




                                                                                                                32
Thank you!




             33
Appendices




             34
I-V Characteristics (90nm nFET)
                                                                            6
          30                                                                                                         VGS = 0.7V
                   20/0.1
                                                                            5
          25       40/0.1
                   40/0.2                                                                     1mW
                                                                            4
          20                                                                                                         VGS = 0.6V




                                                                  ID [mA]
ID [mA]




                                                                            3
          15
                                                                                       0.5mW
                                                                                                                      VGS = 0.5V
          10                                                                2


          5                                                                 1       0.1mW                             VGS = 0.4V
                                                                                                                      VGS = 0.3V
          0                                                                 0
               0            0.2   0.4             0.6   0.8   1                 0           0.2     0.4        0.6   0.8          1
                                        VGS (V)
                                                                                                          VDS [V]




              ID scales with W, ID does not scale with 1/L
              Bias selection with constant power contours


                                                                                                                                   35
Characteristic Current Densities




      S.P. Voinigescu, T.O. Dickson, T. Chalvatzis1, A. Hazneci, E. Laskin, R.
      Beerkens, and I. Khalid, “Algorithmic Design Methodologies and Design
      Porting of Wireline Transceiver IC Building Blocks Between Technology
      Nodes,” CICC, San Diego, Sept.19, 2005.
                                                                                 36
Drain Current Modeling
                         90nm FET


                             Square Law


                           DSM

                           Actual




                                    37
Linearity – IP3
Intermodulation Distortion




By Quasi Periodic Steady State (QPSS) Analysis
                                                 38
Dynamic Range – P1dB
1dB compression point by Periodic Steady State (PSS) Analysis




                                                                39

								
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