FINAL EXAM TOPICS: - Download as DOC

							UTA EE2303 SPRING 2010 EXAMII TOPICS:

Style of Exam is similar to EXAM I. You need to be able to make
derivations, interpret graphs and extract information, be able to generate
load lines and use them to calculate Q points, extract small signal models in
and derive equations for gain, and input impedance. Chapters 4 and 5

A. BJT npn DC and small signal ac analysis

Chapter 4 (excluding current mirror and NOR gate). Cut-off, Forward active,
and saturation regions. Determination of DC load-line and Q point in Four
resistor biasing circuit. Role of RE: its effect on IB , IC , and gain and bias
stability.

Small signal ac model of BJT, common emitter and emitter follower
amplifiers, ac and dc load lines, gain, input and output resistance.

Section 4.9 (Logic switch/inverter transfer characteristic): You should be
able to use graphical method to obtain transfer characteristics of a BJT
inverter. How does RE change Transfer function?

We spent a lot of time on Amplifier analysis and design. You should be
able to do 4 resistor biasing, BJT amplifiers. You should be able to extract
DC and ac analysis circuits when coupling and bypass capacitors are
present.

B. FET: only n-channel enhancement FET (Chapter 5)

Formulas for iD vs. vDS for Cut-off, Triode and Saturation regions of
operations will be given. However you must know operates. Know the
inequalities that determine the 3 regions of operation.

Be able to extract K, Vto, and λ given iD vs. vDS curves (e. g. Fig 5.6 and
5.11)

Be able to write load line equations and graphically determine operating (Q)
point of the FET (e.g. Fig 5.14 and section 5.2)

Be able to analyze a 4 resistor bias circuit to obtain VGSQ, VDSQ, IDQ, both in
saturation region and in Triode region.
When solving for FET biasing, you must pay attention to your assumption
regarding which region of operation you pick THEN verify that your result
satisfy the appropriate inequalities. (e.g. for an enhancement mode n-type
FET if you assumed saturation your results obtained for vGS must be >Vto
and at the same time vDs value must be greater than vGS-Vto). Also when you
solve quadratic equations you must discard the wrong root: here is what you
do for n-channel FETs: For saturation: discard the vGS value that is less than
Vto. For triode region, discard the vDS value that is larger than vGS-Vto.

FET small signal ac analysis of common source and source- follower
amplifier: Drawing small signal model, calculation ogf gain, input
resistance, output resistance.

Useful links:

BJT
bjtFixedBiasing.pdf     bjtFourResisor.pdf

bjtGraphicMethod.pdf     AND its Solution BJTgraphicSolution.pdf

http://www.electronics-tutorials.ws/transistor/tran_2.html

FET
Triode and Saturation Regions Operation-Region-FET
http://www.electronics-tutorials.ws/transistor/tran_4.html

Summary of BJT and FET http://www.electronics-
tutorials.ws/transistor/tran_8.html

More example solutions will be posted