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PROFORMA FOR SUBMITTING R&D PROJECT PROPOSAL
FOR SEEKING FINANCIAL SUPPORT
SUMMARY SHEET
1. Title of Project : Si:Ge BJT – all encompassing and comprehensive advanced version of
HICUM which includes variable latching property of BJT as well as the Universal Hybrid-pi
model.
2. Organisation
a) Name: Indian Institute of Technology, Patna.
b) Address : Patliputra Colony, Patna 800013
c) Legal status (indicate if Government Department, Statutory, Corporate Body, Registered
Society, Private Company with recognised R&D unit etc.): Statutory Body by an Act of
Parliament.
3. Chief Investigator
a) Name; Dr. Kailash Chandra Ray.
b) Designation: Assistant Professor.
c) Department: Electrical Engineering Department.
d) Address: IIT,Patna.
4. Nature of Project (Check one)
a) Research, Development & Engineering (R,D & E) leading to production capability
b) Application oriented Research, Design and Development (R,D&D) having production
potential
c) √Basic R&D
5. Objective of the Project: To develop an all encompassing and comprehensive simulation
updated software HICUM for commercial simulators for Circuits and Systems using Si:Ge
BJT.
6. Brief outline of the project with specific technology fall-outs:
Part 1. Study variable latching phenomena in UHF Si BJT+Microwave Si:Ge BJT and
develop a theoretical model which can adequately explain the variable latching phenomena.
Si BJT under constant current drive, under Current Mirror Configuration, under Symmetrical
Widlar Configuration and under Widlar configuratrion (Appendix III) show a sustaining
voltage which is in ascending order starting from BVCES and going as high as BVCBO .
Part 2. Measure the gains of differential amplifiers using Current Mirror, Symmetrical
Widlar and Widlar Current Source as the dynamic load(Appendix IV). Measure the gains by
Frequency Domain Analysis using super attenuator (Appendix VI) to scale down the
available sine wave input and by Oscillation based technique (Appendix V) to make sure that
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our measurement of the super-gain is accurate. Then justify the gains using Universal Hybrid-
pi model. This measurement will authenticate our Universal Hybrid-pi model.
Part 3. Incorporate the basic findings in Part 1 and Part 2 in a compact model for simulation
software and use the software to predict the gain of a practical Op Amp μA741 and see how
the simulated result is verified by the experimentally measured results of the open lop gain of
the given Op Amp.
Part 4. Repeat Part 3 for a series of BJT Op Amps and validate the compact model as
developed in our project.
Part 5. Once our compact model is validated we have to combine the features of our Model
with those of the latest version of HICUM and repeat Part 4 to establish that this advanced
model is superior to the existing models of HICUM.
Part 6. Present our model , the advanced version of HICUM, as the standard model to
Compact Model Council for acceptance and simultaneously apply for an international patent
of the same.
7. Expected outcome in physical terms (as applicable)
a) Specifications of subsystem/system (as applicable): It will be a fuller and all encompassing
model of Si BJT superior to the models presently existing.
b) Nature of documents for technology transfer: An all encompassing and comprehensive
model of Si:Ge.
c) Manpower trained
i) Level of training:
ii) Nos. (industry/outside R&D/Internal): There are 25 plus SiGe Industrial Fabrication
Facilities all over the world which will incorporate this comprehensive model in their
commercial simulators. The prominent names today in Si:Ge HBT industrial
production are IBM, Jazz Semiconductors, Hitachi, Infineon, IHP, ST
Microelectreonics, Texas Instrumentss and Phillips.
8. Agency with which link up is (Details may be given as applicable) established/proposed
9. Duration of Project-1 Year
10. Year-wise break-up of physical achievements with specific intermediate milestones (in terms
of aims and objectives):2 months-Part 1, 2 months-Part 2, 2 months –Part 3, 2 months-Part 4,
2 months – Part 5, 2 months –Pat 6.
11. Likely End User(s):All the R&D facilities engaged in research in Analog Circuit and Systems
plus the users of commercial simulators namely IBM, Jazz Semiconductors, Hitachi,
Infineon, IHP, ST Microelectreonics, Texas Instrumentss and Phillips.
12. Name of other organisations jointly participating in the project (including organisation
abroad)None.
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3
13. Total Budget outlay
(Rs.in lakhs)
Years
Head 1st 2nd 3rd Total
Capital Equipment Rs. 50 lakhs
FE Comp.
Consumable stores Rs. 10 lakhs
FE Comp.
Duty on import (if any) Rs.
Manpower Rs. 6 lakhs
Travel & Training Rs. 10 lakhs
FE Comp.
Contingencies Rs. 10 lakhs
Overheads, if any Rs. 10 lakhs
Grand Total (FE Comp.)
` Grand Total : Rs.96 lakhs
FE Component : Rs.
14. a) Contribution of Project Implementing/ Rs.
& other Organisation in Total Budget Outlay
b) DIT Contribution Rs.96 lakhs
Signature of Chief Investigator Signature of
Designation Head of the Institution/Organisation
Date Designation
Date
Additional Information Required
4
1. Wherever applicable, Under S.No.13, share of the industry, collaborating agency, any other
assistance and DIT's support required in the total cost of the Project may be provided under
various budget heads.
2. Brief history of the electronics company including products being made, capacities, related
collaborators, achievements, capabilities etc. may be provided (including recent annual
reports and company brochure)
3. Please indicate recent major achievements of in-house R&D Unit of the electronics company
in development of new products/processes, technology export, patent taken etc. and whether
in-house R&D unit of the firm is recognised by DSIR.
4. Any other information in support of the proposal.
5
DETAILS OF THE PROPOSAL
PART 1 : BACKGROUND INFORMATION
1. Title of Project: Si:Ge BJT – all encompassing and comprehensive advanced version of
HICUM which includes variable latching property of BJT and the Universal Hybrid –pi
Model.
2. (i) Chief Investigator: Dr. Kailash Chandra Ray;
(ii)Co-Investigator :Dr Bijay Kumar Sharma.
3. Other Investigators of the Project with their designations: none-None
4. Brief Bio-data of Chief Investigator and other Investigators (including publications/patents)
(Please attach separate sheets): Bio-data of co-investogator is attached as Appendix I at the
end.
5. Competence of Investigator in Project Area (Including Industry interaction/Technology
transfer): Co-investigator has been working in this area for last 20 years as is evident from
his CV. He is a master in the field.
6. Other Commitments of the Chief Investigator and Co-Investigators (including lectures,
research projects
responsibilities etc.) Indicate the percentage of time the Chief Investigator and Co-
Investigator would devote to the project.: Co-investigator will devote his full time.
7. Details on each of the ongoing/completed projects with the Chief Investigator/Co-
Investigator/R&D Team
i) Project Title
ii) Funding Agency (or Internal funding)
iii) Brief Project Summary
iv) Technical Status vis-a-vis objectives
v) Financial Status (Total Project outlay, expenditure to date)
vi) Duration and year of initiation
vii) Expected date of completion
8. Brief summary of other project proposals (submitted by any of the Investigators) awaiting
consideration of DIT and other funding agencies like DST, DRDO, DSIR, MHRD, ICICI,
IDBI etc.
9. Infrastructure and other facilities available at the institute for undertaking this project.
a) List of major equipment alongwith model numbers, specifications etc.
6
b) Existing manpower and other personnel with names available for the project on full-time
basis.
10. Expensive Equipment /facilities available elsewhere which could be made use of for the
project.
11. Details of collaborating agencies (As this would vary from project to project, necessary
details may be given as appropriate)
12. Additional information, if any.
7
PART II : TECHNICAL INFORMATION
1. Aim and Scope of the project (in terms of specific physical achievement): The Design of
Op.Amps presently fully depends on Simulation and trial and error. The development and
incorporation of the Universal Hybrid-pi model will give a theoretical footing to the design of
Op Amps. Further more the micro-wave Si:Ge have undergone structural changes which
compel the operating voltage to be low. By use of this model which incorporates variable
latching property we can better exploit the potential of the devices. The CB Junction
breakdown voltage after the structural changes has come down to 7 V. But in CE
configuration the permissible range will be only 4V. By use of this model and by proper
circuit design we may operate at 7V. The typical dc parameters of SiGe are:
BVEBO=3.3V,BVCBO=5.5V,BVEBO=1.8V and dc current gain=450[“ A 210GHz fT SiGe HBT
with a non-selfaligned structure”, Jeng et al, IEEE ED letters , Vol22, No.11, Nov,2011]
2. Detailed description of the Project: Today SiGe technology has become the driving
technology behind the Information Revolution. SiGe is enabling light weight, personal
communication devices like digital wireless handsets and other entertainment and
information technology devices such as digital set-top boxes, Direct Broadcast Satellites,
Automobile Collision Avoidance Systems and Personal Digital Assistants. SiGe extends the
life of wireless phone batteries. It enables smaller and more durable communication devices.
SiGe technology is being used for developing mobile-computing systems which converge the
capabilities of cellular phones, global positioning systems and internet on one platform.
These SiGe based multifunction low-cost, mobile client devices are the building blocks of
future computing. These devices will communicate over voice and data networks. SiGe real
strength lies in its ability to integrate analog, RF and digital on a single chip using existing
CMOS fabs. This kind of compatibility is not found with GaAs technology. Apart from this
compatibility resulting in versatility, it is enabling new architecture such as direct frequency
conversion and software radio.
3. Need, forecast and urgency for the technology proposed to be developed with justification
such as importance of know-how, import substitution role, pay off w.r.t. purchase of know-
how or development of technology competitiveness, technology exports, international
alliances possibilities etc. It will fetch royalty to the country.
4. Specific manner in which know-how generated here is envisaged to be translated into
production, details regarding
a) the end product (with specifications to be attained etc.) It will be incorporated into the
advanced version of HICUM endorsed by Compact Model Council and which will be
used by all commercial simulators.
b) availability of pilot production facility in the organization- not required
5. a) Name of production agencies willing to productionise/use and market surveys if any
made by them regarding demand for the product :
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HICUM Group comprises HICUM Group at CEDIC, University of Technology Dresden, Germany, and the
University of California at San Diego, USA.
E-Mail
A. Mukherjee: mukherje iee.et.tu-dresden.de
M. Schröter: mschroter ieee.org
Phone
M. Mukherjee: +49 351 46331961
M. Schröter: +49 351 46337686
Fax
+49 351 46337260
12. Alternative production/user agencies. All the fabrication labs namely IBM, Jazz
Semiconductors, Hitachi, Infineon, IHP, ST Microelectreonics, Texas Instrumentss and
Phillips.
b)
6. Period required for completing the project : One Year.
7. Details of work already done by present investigators/
R&D team in this or other areas
a) Successfully completed on schedule. MODROB project at NIT,Patna, was successfully
completed in time.
b) Currently in progress
c) Abandoned
d) Industry interaction/know-how transferred
8. Summary of similar work being done elsewhere in the country: I am not aware of a similar
work in India.
9. Information regarding specific intermediate milestones (year-wise) :2 months-Part 1, 2
months-Part 2, 2 months –Part 3, 2 months-Part 4, 2 months – Part 5, 2 months –Pat 6.
10. a) Specific problems, hold-ups and difficulties foreseen in the implementation of the project.
b) If the answer is not Nil to 10(a), how does Chief Investigator propose to overcome them?
11. Detailed PERT/BAR Chart (Separate Sheet)Appendix II
12. Details of possible alternative arrangements if the Chief Investigator leaves institution or is
unable for any other reason to continue on this project. The co-investigator will complete the
project.
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13. Name of other organisations in India or Abroad jointly participating in this effort, extent of
their involvement, specific division of responsibility, accountability etc. None are
collaborating
14. List the personnel already working in the organisation who would be transferred to work full
time on this project. Co—investigator will carry out all the work.
15. Name of experts whom the Chief Investigator would invite to join the project team as full
time/part time member. Co-investigator is the expert.
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PART III - FINANCIAL DETAILS
Table - 1 Yearly Break-up
Budget requirements for the Year 2011-12……..(Please provide separate breakup for each year
of the project duration)
S.No. Head Local Foreign Duty Total Part Amt.
expe- Exchange of 6
payable
nses (FE) to be by
DIT
borne by participating/
other organisation
1. 2. 3. 4. 5. 6. * 7. 8.
1. Capital(Semiconductor Parametric Analyzer,DSO,Spectrum Analyzer, buffers and HICUM
and MEXTRAM software) : 50lakhs.
Equipment
2. Consumable(Bread board, hook-up wire, connecting wire, UHF and microwave transistor
pairs): 10 lakhs
stores
3. Manpower: Co-investigator fellowship Rs50,000 per month, 6 lakhs per annum.
4. Travel/
Training 10 lakhs
5. Contin-
gencies other
expenditure
debitable to
this project 10 lakhs
6. Overhead, if any 10lakhs
Total: Rs. 96 lakhs Others: Rs.
DIT.Rs.
*Total cost of the project and contribution to be made by the organisation/other organisation
should be shown separately.
Table II : Subsystem wise Break-up
S.No. Item description Local FE Duty Freight
Total
(including test equi-
pment, components,
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materials etc.)
1 2 3 4 5 6 7
______________________________________________________________________________
______________
Table-III Manpower Details
S.No. Designatio Monthl Ist Year 2nd Year Total
n of post y salary
No.of Total No.of Total
Posts Expenditur posts Expenditur
e e
1 2 3 4 5 6
Research Fellow-Rs50,000 per month, one post, total exp. per year Rs 6 lakhs
1. Scientific/Technical: none
2. Grade lower than (1): none
3. Skilled workers: none
4. Unskilled workersNone
Total:Rs. 6 lakhs.
Part IV
Endorsement by the Head of the Institution
1. I have read the terms & conditions (including special terms & conditions for co-financing)
governing the grant-in-aid and I agree to abide by them.
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2. I certify that I have no objection to the submission of this research proposal for consideration
by the Ministry of Information Technology
3. In case the project is approved, I undertake to make available facilities to carry it out, to
arrange for the submission of periodic progress reports and other information that may be
required by the Ministry of Information Technology and In general to ensure that the
conditions attached to the award of such grant are fulfilled by my institution/organisation.
4. I certify that in case present chief investigator is not available for any reason to continue work
on this project, the following persons will be available to carry it throughout to completion:
Sl.No. Name Designation
1.
2.
5. I certify that the facilities mentioned in the body of this report are available at my institution.
6. I certify that I shall ensure that accounts will be ept of the funds received and spent and made
available on demand, as specified and required by the Ministry of Information Technology.
7. I certify that I am the competent authority, the virtue of the administrative and financial
powers vested in me by to undertake the above stated commitments on behalf of my
institution.
Signature of the
Head of the Institution
Designation
Date:
R& D Projects Funding
Terms and Conditions Governing Grant-in-aid
i ) The grant is for the specific project as approved by DIT and shall be subject to the following
conditions:
(a) The grant amount shall be spent for the project within the specified time,
(b) Any portion of the grant which is not ultimately required for
expenditure for the approved purposes shall be duly surrendered to DIT.
ii) The grantee institution shall maintain an audited record in the form of a register in the
prescribed proforma for permanent, semi-permanent assets acquired solely or mainly out of DIT
grant;
iii) The assets referred to in (ii) above will be property of DIT and should not, without prior
sanction of DIT, be disposed off or encumbered or utilised for the purposes other than those for
which the grant has been sanctioned. An undertaking shall be given by the grantee institution that
they agree to be governed by these conditions; iv) At the conclusion of the project, DIT will be
13
free to sell or otherwise dispose of the assets which are the property of DIT and grantee
institution shall render to DIT the necessary support for facilitating the sale of these assets;
v) The grantee institution shall send to the Department of Information Technology at the end of
each financial year as well as at the time of seeking further instalments of the grant a list of assets
referred to in (ii) above;
vi) Should at any time grantee institution cease to exist, such assets etc., shall revert to DIT;
vii) The grantee institution shall render progress-cum-achievement reports at interval of not
exceeding six months on the progress made on all aspects of the project including expenditure
incurred on various approved items during the period.
viii) The grantee institution shall render an audited statement of accounts to DIT.
ix) The audited statement of accounts relating to grants given during financial year together with
the comments of the auditor regarding the observance of the conditions governing the grant
should be forwarded to the Department of Information Technology within six months following
the end of the relevant financial year;
x) The utilisation of grant for the intended purposes will be looked into by the Auditor of grantee
institution according to the directives issued by the Government of India at the instance of the
Comptroller and Auditor General and the specific mention about it will be made in the audit
report;
xi) DIT or its nominee/s will have the right of access to the books and accounts of the grantee
institution for which a reasonable prior notice would be given;
xii) The grantee institution should maintain separate audited account for the project. If it is found
expedient to keep a part or whole of the grant in a bank account earning interest, the interest, thus
earned should be reported to this Department. The interest so earned will be treated as a credit to
the grantee to be adjusted towards future instalment of the grant;
xiii) Sale proceeds of components, prototype, pilot project etc. fabricated as a result of the
development of the project arising directly from funds granted by Department of Information
Technology. shall be regretted to DIT;
xiv) The know-how generated by the project, shall be property of DIT. Any receipt by way of
sale of know-how transfer, royalties training etc., shall accure to DIT. DIT may, in its discretion,
allow or direct a portion of such receipts to be retained by the grantee organisation.
xv) DIT will have the right to call for drawings, specifications and other data necessary to enable
the transfer of know-how to other parties and the grantee shall supply all the needed data at the
request of DIT;
xvi) Application by grantee institution for any other financial assistance or receipt of grant/loan
from any other Agency/Ministry/Department for this project should have the prior approval of
Department of Information Technology.
xvii) The Grantee institution is not allowed to entrust the implementation of this project for
which grant-in-aid is received to another institution and to divert the grant-in-aid received from
Ministry of Information Technology as assistance to the later institution.
xviii) DIT shall appoint a Project Review and Steering Group (PRSG) comprising of
representatives from DIT and other experts. PRSG will periodically monitor the project in all
respects including technical and financial.
xix) The Grantee institution will first make all efforts to protect intellectual property generated
out of the project. The grantee institution will examine IPR protection issues in consultation with
14
IPR Cell, DIT to file patents, register the copyrights etc. before making it public by publishing in
the technical journals and books, presenting findings in Conferences etc.
xx) The Intellectual property and the rights associated with it shall be assigned to DIT. In cases
where the fundings have been done jointly with other organisations, the IP rights would be
appropriately shared.
xxi) In case of any dispute on any matter, related to the project during the course of its
implementation, the decision of Secretary, DIT, shall be final and binding on the institute.
A certificate of acceptance of terms and conditions as above needs to be given by the chief
investigator/ endorsed by the head of the institute while submitting the project proposal.
APPENDIX I
Curriculum Vitae.
Name: Bijay Kumar Sharma.
Date of Birth: 1st July 1946.
Permanent Address: Maniari Bhawan, M.P.Sinha, Kadam Kuan, Patna 800003.
Correspondence Address: Library, Indian Institute of Technology, Patliputra Colony,Patna
800013.
Telephone Number: Residence:+91-612-2672723, Mobile No.+91-9334202848;
Fax Number:+91-612-2277384
E-mail address: bijay_maniari@rediffmail.com;bijay_maniari@hotmail.com
Website: www.ecenitp.com
Educational Qualification:
Exam passed Board / University Year of % of Subjects taken
passing Marks
Secondry Cambridge Univ Dec 1961 63 P+C+M+B
Intermediate ***
Bachelors IIT, Kharagpur June 67 79.2 Electronics & Communication
Masters Stanford University August 70 4/4 Communicatin
Hybrid Microelectronics
Ph.D Univ.of Maryland August 72 3.84/4 Bio-Electronics
D.Sc. BRA Univ,Muz Feb 2010 Celestial Mechanics
Past and present employment:
Employer Designation Duration
Undecided
National Institute of Technology,Patna Professor & HOD 31st May 2011 to 30th
June 2011
National Institute of Technology,Patna Associate & HOD December 2005 to May
2011
National Institute of Technology,Patna Lecturer January 2004 to
November 2005
Bihar College of Engineering,Patna Lecturer December 1997 to
Dec.2003
Institute of Engg & Tech,Lucknow Assistant Prof & March 1985 to July 1986
HOD
15
Birla Instritute of Technology & Assistant Prof Sept1984 to February
Science,Pilani 1985
Indian Institute of Technology, Kharagpur Lecturer June1980 to August 1984
CSIR Pool Officer Sept 1972 to June 1973
Central Electronics Engineering Research Juniour Research Sept 1967 to Aug1969
Institute, Pilani Fellow
List of Publications in peer reviewed Journal.
S.No. Title of papers Authors Journal From to
1 of the
“The Architectural Design rules Self Earth, Moon and 15 37
Solar Systems based on the New Planets, Vol.108,Issue
Perspective.” 1(2011)
2 “Simulation Software for the spiral Self et Advances in Space 460 46
trajectory of our Moon” al Research 6
2009, February, Vol
43,
3 The prediction of Universal Hybrid-π Self JIETE, Jan-Feb, 1989, 1 7
model leads to a new effect- Variable Vol.35,No.1
Latching Phenomena in CE BJT
4 The Hybrid-π model: some Self et JIETE, March-April, 97 10
discrepancies and the suggested al 1990, Vol.36, 4
Hybrid-π model
5 Development of a low cost attachment to Self et IETE Tch Rev. Vol 1, No. 179 18
produce Braille copies of Diagrams: a graphic al 12, 1984 1
aid to sightless people
Journals(Specify in Nos. and Submit Photocopies with Cover Page and Content
area):
Journal Number of co- author(s) Number
International Level Publications 2
National Level Publications 3
Seminars/Workshop Proceedings 25
Other Publication (if any)D.ScThe. 1
Teaching:
Level of Area of From To Length in
Teaching Teaching Years
PG Microelectronics July 1980 September 1984 4yrs. 3months
UG Electronic Core Jan 1970 Till date 20yrs
Others *******
16
Awards/ Recognition/ Extension Service/ Examiner ship / Patents, Etc.
(Attach a Separate Sheet, mentioning the Details):
Prizes First Prize for optional Quantum Mechanics in Fifth Year B.Tech. At
IIT, Kharagpur.
Scholarship Merit Scholarship & Tuition Waiver in 2nd year ,4th year & 5th year of
five year BTech Integrated courses at IIT, Kharagpur.
Teaching Assistantship Spring Quarter in MS at Stanford
Research Assistantship Winter Quarter in MS at Stanford.
Two years in PhD at Univ of Maryland.
Junior Research Two years in Solid State Divison of Central Electronics Engineering
Fellowship Research Institute, Pilani.
Sports & Extracurricular Consistently held positions in Cycle Race.
Activities
Fellow and Memberships of Professionals/Learned bodies/Societies.
Institution of Electronics & Telecomm. Engg Fellow Member
(IETE) F-047747
Indian Society of Technical Education Life member
(ISTE) LM 44873
Institution of Electrical & Electronics Engg Member
(IEEE) 80609869
Administrative Experience:
Capacity From To Length in
Years
Head Of the Department Jan 2006 30.6.11 5 years
Placement + Training Jan 2005 Sept 2010 5 years
Following study materials have been uploaded at http://cnx.org
1.Solid State Physics and Devices_the Harbinger of Third Wave of
Civilization.
Chapter 1. Modern Physics-Foundation of Solid State Physics & Devices.
Chapter 6. Integrated Circuit – Design and Fabrication.
Chapter 7. CMOS Digital VLSI Design.
17
2. Lecture Notes on Analog Electronics_this covers the full semester
course.
3. Digital System Design using VHDL.
Research experience.
Modernization and Obsolescence removal of Computer Lab in ECE Department under AICTE
8017/RDII/MOD/DEG(222)/98-99
i. With Rs 5 lakh grant we bought 3 pcs and 1 server and Laser Jet Printer. We set up
Orcad Simulation Software and carried our research as shown in my Publications.
R & D work as Research Assistant under Prof. R.W.Newcomb at Stanford University and University of
Maryland, College Park,USA.
i. Development of thin film 3-phase micromotor.
R & D work as Junior Research Fellow at CEERI, Pilani.
i. Development of indigenous Tolansky Interferometer for measuring few hundred
Angstrom thin films by step method and using Sodium Vapour Lamp.
ii. Development of NiCr thin film resistance 200 ohm per square sheet resistivity and
temperature coefficient of resistance of 150 p.p.m. ;
Research Plan:
i. Setting up of Radio Telescope and making this a part of Indian Deep Space
Communication Network and developing a full academic curriculum on the same.
Through Deep Space Communication Networks, the space crafts on long missions
are controlled, guided and maneuvered. With completion of Chandrayan Mission I
and Chandraya Mission II in preparation, deep space communication assumes
enormous significance but no formal education is being imparted in the field
anywhere in India. Even Indian Institute of Space Technology & Sciences,
Tiruvanthpuram, does not have a formal programme on Deep Space
Communication. This course work at ECE UG and at ECE PG will fill up a very
important gap in Indian Technical Education.
ii. I will also develop a strong UG and PG programme centered around
“VLSI design and Microelectronics” specialization. This programme will
emphasize on the following lab programmes:
a. Solid State Physics and Device Lab.
b. Material and Device Testing and Characterization Lab.
c. Digital System Design Lab using Verilog/VHDL. On
Xilinx platform.
d. Analog & Mixed Signal Design (AMS) using microwind
package.
e. Process Simulation Lab using SUPREME3-1D process
simulator for Silicon
18
And using SUPREM IV.GS-2D process simulator for Si
and GaAs.
f. Device modeling and simulator using
MEDICI/PISCES/SEDAN III
APPENDIX II
Programme Evaluation and Review Technique(PERT) CHART
The activities are:
A = over two months period a set of UHF and microwave N-type matched pairs’ sustaining
voltage and output impedance in Current Mirror Configuration, in Symmetric Widlar
Configuration and Widlar Configuration will be measured and the two will be correlated in close
form equation.
10 is the milestone we will achieve at the end of activity ‘A’. The theoretical formulation of the
variable latching phenomena is the milestone 10
B = over the next two months differential amplifiers will be built up with Current Mirror,
Symmetric Widlar and Widlar Current Sources as the dynamic load of the differential pair and
their single ended output gain will be measured by Oscillation Based Technique Method and by
Frequency Domain Method using Super- attenuator and the two results will be checked for
consistency. Next hybrid-pi parameters of the DUT (device under test) will be determined and
theoretical analysis done. The theoretical gain should correspond to the experimentally
determined gains by two methods. Once the correspondence is achieved we have validated the
Universal Hybrid –pi Model.
20 is the milestone we will achieve at the end of activity B. The Universal Hybrid-pi Model is the
milestone 20.
C and D are combined activities covering the same period of 2 months = We will take the
Universal Hybrid-pi Model and the theoretical formulation of the variable latching voltage to
develop a compact model which will incorporate the two features. This compact model will be
used for simulating the circuit diagram of μA741. This OP Amp’s open loop gain will be
measured experimentally measured by OBT method as well as by Frequency Domain Analysis
Method. The Open Loop Gain of the given OP AMP should come out to be the same by all three
methods. Once this correspondence is achieved we have determined an accurate compact model
for BJT.
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30 is the milestone we will achieve at the end of C and D. Development of an accurate compact
model in corpora ting the Universal Hybrid-pi model and variable latching feature is the
milestone 30
E = over the next two months a series of Op Amps will be checked by simulation and experiment
to develop a 90% confidence level about the validity of the new advanced compact model.
40 is the milestone achieved at the end of E. 90% confidence level build up is the milestone 40.
F= merging the new advanced compact model in the existing HICUM and use it to simulate the
same series of OP Amps and check the results vis-à-vis the results we got in activity E. If we get
the concurrence of the two results then it indicates the correct merger of our compact model into
the currently accepted HICUM .
50 The new all encompassing and comprehensive version of HICUM is the mile stone 50.
F= presenting this new expanded version of HICUM before the Compact Model Council and
before the international Patent Office and getting it accepted will be the activity of last two
months.
60 The patent of the new expanded version of HICUM and the acceptance of the same by the
Compact Model Council will be our final milestone 60.
APPENDIX III
The different current sources which will be used as the dynamic load of the differential pair are
given below in the figure.
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APPENDIX IV
The Circuit Diagram of the Super Gain Amplifier. This forms the first stage of any OP Amp. It is
a differential pair with one of the current sources acting as the dynamic load.
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APPENDIX V
Oscillation Based Technique method for measuring the super gain.
APPENDIX VI
Measurement of Super Gain by Frequency Domain Method using a super-attenuator.
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