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					            An improved RC6 algorithm with the same structure of
                            encryption and decryption


Abstract:


This paper proposed improved RC6 encryption algorithms that have the same structure
of encryption and decryption. So far, conventional RC6 algorithms have difference
structure    of encryption and decryption. We devise our algorithm by inserting a
symmetric layer using simple rotation and XOR operations, in which the half of whole
RC6 rounds uses encryption procedure and the rest of it are employs decryption one.
The symmetry layer is put between encryption part and decryption one. The proposed
RC6 algorithm has the almost same speed compared with the conventional RC6 one.
Nevertheless, the proposed algorithm improves encryption security by inserting the
symmetric layer because a differential and linear analysis has a difficulty in analyzing an
encrypted stream. The proposed algorithm will be useful to the applications which
require the same procedure of encryption and decryption such as light mobile devices and
RFIDs.
Architecture:




                Structure of improved RC6 algorithm
Existing system:
          RC6 algorithm


Existing system disadvantages:
          Rc6 algorithm requires 128-bit and variable-length block cipher encryption
algorithm. It has a modified Feistel structure and a disadvantage that it has different
algorithm between encryption and decryption. Thus, the RC6 algorithm needs double
space compared with the same structure of encryption and decryption when it is
implemented on hardware.


Proposed system:
          An improved RC6 encryption algorithm that have the same structure of
encryption and decryption. A symmetric layer is inserted between encryption part and
decryption using simple rotation and XOR operations.


Proposed system Advantages:
          The proposed algorithm improves encryption security by inserting the symmetric
layer because a differential and linear analysis has a difficulty in analyzing an encrypted
stream.


Software Requirements:
         Xilinx 9.1i and above
         Modelsim 6.0 and above


Hardware Requirements:
         FPGA kit
Introduction about the Software:
       Xilinx 9.1i software includes the new Xilinx Smart Compile™ technology, which
significantly improves run times by up to 6x faster than the previous version, while
maintaining exact design preservation of unchanged logic.
       Modelsim is a verification and simulation tool for VHDL, Verilog,
SystemVerilog, and mixed language designs.


Introduction about the domain:
       Due to the rapid advances in integration technologies, large-scale systems design -
in short, due to the advent of core VLSI. The number of applications of integrated circuits
in high-performance computing, telecommunications, and consumer electronics has been
rising steadily, and at a very fast pace. Typically, the required computational power (or,
in other words, the intelligence) of these applications is the driving force for the fast
development of this field. This trend is expected to continue, with very important
implications on VLSI and systems design. One of the most important characteristics of
information services is their increasing need for very high processing power and
bandwidth (in order to handle real-time video, for example).

				
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posted:7/27/2012
language:English
pages:4