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ECE 6420 – Final Design Project – Group 7 1
Design of a CMOS WiMAX Power Amplifier
using Power Combining Techniques
Michele Piccardi, Jason Pinto,Akshil Shah and Pritham Raja
section VI and limitations of the design in section VII.
Abstract – In this paper, we describe the design and implementation
of a CMOS WiMAX Power Amplifier implemented using a two- II. MARKET ANALYSIS
stage cascade topology. Multiple stages have been combined
utilizing power-combination transformer techniques. Simulation A. WiMAX Research
results show a power gain of 29 dB with a P1dB of 30.71 dBm and RF PA products are targeted at mobile phones and other 3G
an EVM of 3% @ 23.5 dBm with a PAE of 21.5%. The PA was
wireless devices, such as datacards, netbooks and technology
tested with IEEE 802.11a (WLAN) 54-Mbps OFDM signals at 2.4-
Ghz. It is proved that the PA fulfils the requirements of both WLAN products compatible with new standards like WiMAX. Mobile
and WiMAX standards. Additionally, a 3.5 Ghz version was phones and wireless products today use power amplifiers mainly
developed and the two PAs combined. based on Gallium Arsenide (GaAs) or Silicon Germanium (SiGe)
semiconductor technology. Replacing GaAs or SiGe with CMOS
Index Terms—CMOS, Class-AB, Power Amplifiers, WiMAX, silicon technology would improve manufacturing yield and cost,
transformer power combination, cascode, EVM, mask. but the efficiency could decrease, even though latest studies
suggest that a high PAE can be obtained. However, research is
still required for CMOS to be able to meet modern performance,
I. INTRODUCTION
battery life, and call quality requirements. Over time, CMOS has
T HE growing demand of wireless communication using
digital modulation has driven the adoption of orthogonal
frequency division multiplexing (OFDM) schemes which
replaced GaAs technology in many other applications from audio
chips to DVD decoders. However, CMOS does not lend itself
easily to use in power amplifiers, so that a novel architecture may
provides high data-rate transmission. This makes linearity of the be required.
transmitter a stringent requirement. The linearity of the whole The importance of this market is easily understood by
transmitter is a strong function of the linearity of PA and it is considering that 3G mobile phones typically employ more power
also a major parameter in determining the quality of the amplifier units than 2G or 2.5G phones. As an example, the
transmitter. iPhone, a 2.5G phone, integrates one cellular power amplifier
In the case of cellular applications, output power usually package while the iPhone 3G integrates five cellular power
reaches watt-levels. For example, most PA products for GSM amplifier packages. New products compatible with 4G
applications generate more than 2W. Hence, when using CMOS (WiMAX) are expected to require more of these packages.
processes which are known for low power-driving capabilities, it WiMAX products are predicted to hold a value of $1.7 billion
is necessary to have an additional function, i.e. a power with an 80% market penetration in the upcoming future.
combiner, to combine several power cells unit to generate the WiMAX penetration in December 2010 can be considered
required output power. One of the most popular combining significant. The number of people covered by WiMAX service
techniques is based on a Wilkinson-type combiner, which providers is more than 621 million, while the total number of
requires quarter-wavelength transmission lines and it is therefore deployed networks is shown in table I (i.e. included base stations
difficult to integrate in systems for typical cellular applications that are being deployed, but there are few subscribers yet).
frequency bands.
Recently, there have been several successful efforts to realize TABLE I
the function of power combination and impedance WIMAX PENETRATION
transformation at the same time by using transformer-based
Total Deployments tracked 592
networks. They can be categorized as series-combining
transformers (SCTs) and parallel-combining transformers (PCTs) Countries with WiMAX 149
depending on how the voltage and the current are effectively Deployments
combined at the output stage. Eastern Europe 86
In this work, we decided to investigate a transformer-based Western Europe 76
parallel-combining technique to deliver a high output power Africa 117
while using CMOS technology. Section II presents the market
Middle East 29
analysis for a WiMAX PA, section III describes the PA structure
and design methodologies, section IV describes the peripheral North America 57
circuitry associated with the PA. In section V package Asia/Pacific 109
considerations are presented, while results are provided in CALA 118
ECE 6420 – Final Design Project – Group 7 2
WiMAX is compatible with multiple frequency bands, Developing a PA targeted at the dual band 2.4 GHz and 3.5
depending on the market and the geographical region of interest. GHz seems consequently reasonable. Few companies providing
For this reason, a PA which is multi-standard compatible could CMOS solutions for the PA exist in the market. Blacksand
have a worldwide application and a wider market penetration. Technologies is an Austin based company with no available
Table II shows the number of deployments divided by frequency products. Javelin Semiconductors also based in Austin has a
bands. A PA compatible with the 2.3 – 2.7 GHz band and at the CMOS PA, JAV5001, with a selling price of $1.45 @ 10k.
same time compatible with the 3.5 GHz band would have a Skyworks solutions is another company developing a CMOS PA.
potentially high market diffusion. Industry stalwarts like RFMD, TI, Analog devices, Anadigics,
FairChild Semiconductors, Triquint Semiconductors and so on
TABLE II have PAs available but in different technologies such as InGaP
WIMAX FREQUENCY DEPLOYEMENT
HBT, GaAs HBT, and SiGe HBT. The next table shows the
Freq. Range BW Deployement #
performance and features of the products present on the market
2.3 GHz 5/10 MHz 55 and at the research level.
2.5 GHz 5/10 MHz 155
TABLE III
3.3 GHz 5/7 MHz 9 WIMAX PRODUCTS AND PROTOYPES
3.5 GHz 5/7 MHz 309 Freq Gain P1dB
Market (GHz) (dB) dBm EVM Supply PAE(%) Tech
5+ GHz 10 MHz 21 Analog 2.5-
Devices 2.7 29 29 3%@25 dBm 3.2 21 GaAs
2.3- InGa
The following maps show how different WiMAX bands are Anagidics 2.4 30 30 3%@25 dBm 3 or 5 20 P
SiGe 2.5- 2.9 -
geographically distributed. Figure I shows the 2.3-2.5 GHz band Semicon. 2.7 34 - 3%@25.5dBm 4.2 20 SiGe
penetration, while Figure II the 3.5 GHz band penetration. 3.3- InGa
RFMD 3.8 33 33.5 2.5%@26dBm 3 or 6 14.5 P
2.3- InGa
TriQuint 2.8 - 29.8 2.5%@23dBm 5 - P
2.3- InGa
Skyworks 2.5 - - 27.5dBm linear 6 - P
Research
Laskar at
al. 2.4 32 31 20 db @25 dBm 3.3 27 cmos
Mobility
Wireless 2.3-
Group 2.7 18 32 30 db @25 dBm 3.3 48 cmos
Chowdury
at al. 2.4 28 30 25 db @25 dBm 3.3 33 cmos
RF
Systems
Labs 2.3 22.4 24.7 3.3 22.6 cmos
Liu and 4.48%@14.5dB
Fig. 1 2.4 GHz worldwide diffusion Haldi 2.4 10 24 m 1.2 32 cmos
CMOS technology has been already used in WiFi applications,
where the required highly linear output power is around 24 dBm,
and in GSM-GPRS applications, where the output power can be
as high as 1 W, but the linearity requirements are less stringent
and operation in saturation is still admitted. WiMAX
incorporated the challenges of both worlds.
The requirements for a CMOS PA are pretty strict. Since the
minimum output power (Pout) at the antenna is 23dBm, the
power amplifier needs to deliver at least 25dBm linear power to
account for the loss between the PA output and the antenna. A
typical transmitter chip can only provide -5dBm linear power at
its baseband output. In addition, there may be a filter between the
Fig. 2 3.5 GHz worldwide diffusion TX chip and power amplifier for noise reduction purposes and
the typical filter loss is around 2 to 3dB. Consequently, to
achieve 25dBm of output power, around 33dB gain is required
from the power amplifier. To address mobile unit application, the
power amplifier is to be used in handheld devices and typical
available supply voltage is most likely 3.3V. Also, the amplifier
has to have sufficiently high efficiency so that the device be able
to operate for a longer time. The allocated frequency band is
anywhere between 100MHz to 500MHz, operation band of the
amplifier should be designed as broad as possible. An EVM of
less than 3% at Pout of 25dBm is required.
Fig. 3 Other bands combined worldwide diffusion WiMAX requires to respect a specified spectral mask for the
ECE 6420 – Final Design Project – Group 7 3
output signal, in order to reduce the risk of out of band differential stage has a very good common mode noise rejection
transmission of interferers which could disturb adjacent channels. capability as compared to other topologies. Another advantage of
The spectral requirements are shown in fig.4: the differential topology is the reduction of even harmonics at the
output, improving linearity. The power supply chosen is 3.2 V,
which is standard in CMOS Power Amplifier cascode designs.
From the literature, common biasing conditions for a cascode
stage are 0.6 V at the lower stage and 2.5 V at the upper stage.
From this starting point, we perform loadline analysis using
baluns at the input and output to transform the signal from single
ended to differential then back to single ended again. We decide
to bias for a tradeoff between linearity and efficiency in class
AB, with resulting optimal biases of 0.54V and 2.2V.
Loadline analysis is performed according to:
Iterative loadpull and sourcepull measurements lead to:
Fig. 4 WiMAX PA spectral mask
Based on the above mentioned research we decided to
implement a highly linear system with a high gain and a high Fig. 5 shows the driver stage. The devices sizes are L=0.18 µm
P1db compression point with a good EVM result and a good and W=1000 µm. Frequency traps are used to extract the third
efficiency. Clearly these requirements are stringent. Our aim is to harmonics from the output. A 0.3nH inductor with a Q of 50 is
try offering a product which can be comparable to market’s used at the source connection to ground to take into account
products as far as gain, P1dB, EVM and PAE are concerned, but bondwire degeneration effects.
implementing it using CMOS technology, in order to reduce the RF chokes of a value of 1 µH are used at the drains to provide
associated production costs and being able to aggressively isolation between DC and AC components and the appropriate
compete in the market. 3.2V bias. A transformer based balun is used to convert the
signal from single ended to differential while and to partially
transform the impedance seen from the input of the driver stage.
B. Justification of Strategy
Since there are no commercial products available in CMOS
technology, our strategy may take advantage of the high
integration capability of the CMOS industry, while would enable
an easy integration of wide devices, while guaranteeing a low
production cost. In the cellular device market, an important
concern is the battery life, so that PAE should be considered
when taking decisions in impedance matching problems.
III. POWER AMPLIFIER DESIGN
A. Design Criteria
WiMAX requires a good compromise between linearity and
efficiency. The power amplifier design unit consists of a driver
stage and a power stage in cascade. Three of these units are then
connected in parallel, to provide high output power with good
linearity. The driver stage is designed to have a gain of
approximately 20 dB, while the power stage adds approximately
8 dB. By power combination using transformers, the PA
manages to obtain approximately 30 dBm P1dB when lossy
inductors and capacitors are taken into account. We decided to Fig. 5 Schematic of driver stage
use the cascode topology for every elementary stage, since this
topology provides a good output power for realistic biasing C. Design choice for power stage (2.4GHz)
conditions without pushing any transistor into breakdown.
The power stage consists of a parallel combination of cascode
structures with the lower transistor sized at L=0.18 µm, W= 4000
B. Design choices for the driver stage (2.4GHz) µm, while the upper stage at W=4000 µm, L=0.35 µm. This
The driver stage is chosen to be a differential stage. The increases the robustness and reliability of the system, since the
ECE 6420 – Final Design Project – Group 7 4
outer stage can now withstand voltage sweeps up to 7V. The Overall, the results given by the loadpull and sourcepull
cascode structure also provides relative input/output measurements are taken as a starting point for the design and
independence in load/source impedance matching since the parameters tuning is necessary to achieve best linearity with the
Miller capacitor that usually connects input and output of a best output power. Matching of the real part of the load and the
common source stage is now connected to a common gate stage. source can be partially done using the power combining
Loadline analysis is performed according to: transformers, as shown in fig.7.
Iterative loadpull and sourcepull measurements lead to:
Fig.7 Balun
A degeneration 0.3nH inductor with a Q of 50 models bondwires The impedance transformation from the double branch to the
degeneration effects. From the image, we notice that the required single branch follows the following (the opposite holds in the
bias is provided using resistors: this choice is used only during other direction):
simulations, but in the final product a separate bias network will
provide the necessary bias.
Since three stages are connected in parallel, transformers are
used for power combining. The transformers can also be used for For example, as the single branch has a fixed number of turns
impedance matching of the real part of the impedance. Fig. 6 equal to 1, setting the number of turns for the double branch
shows the schematic of the power stage. A balun is used at the equal to 2 will result in upsizing the seen impedance by a factor
input to convert the differential output of the driver stage to two of 4. A downsizing is possible by by reducing the number of the
single ended inputs, to be given to the two parallel cascode double branch windings.
stages. This reduces the need for sharp integrated components. Fig. 5
shows the entire power amplifier design, with input and output
Fig. 6 Schematic of the power stage matching networks. The matching networks are implemented
using non ideal components (inductors with Q of 15 and
capacitors with Q of 100). Introduction of non ideal components
makes the matching trickier as non convergence issues are
experienced during H1B and H2B tone simulations.
D. Design Steps
The main steps used in the design process of the power amplifier
were loadline analysis, and iterative load and source pull
simulations. Agilent ADS was used for the optimization of the Fig. 8 The 2.4 GHz PA with matching networks
design. These steps are partially performed for each block of the
power amplifier, as well as for the entire power amplifier. In
particular, from loadpull and sourcepull measurements we obtain E. Additional 3.5 GHz Power Amplifier
that the optimal load impedance for the driver stage and the An additional 3.5 GHz Power amplifier is designed using the
optimal source impedance for the power stage could be made one same architecture to implement dual band functionality. The
the complex conjugate of the other with less than 2 dBm loss at schematic is shown in Fig. 9. Frequency traps are used to filter
the cascaded output. This enables us not to implement any out the third harmonics so as to improve the linearity. Load line
interstage matching network and connect the two stages directly, analysis is performed followed by iterative load and source pull
for the sake of design and implementation simplicity. We based simulations. Matching networks are then designed for maximum
this choice on loadpull and sourcepull measurements without power transfer and stability. The same procedure is followed for
having the time to actually implement lossy matching networks this design, which represents an addendum to the PA to improve
and compare the results for the two cases. versatility. The new PA is not able to behave equally well in
ECE 6420 – Final Design Project – Group 7 5
comparison with the 2.4 GHz version, possibly due to lack of
time for its design optimization.
The above equations are used to calculate the values of the
resistors employed in the biasing circuit. Also a RFC choke
comprising of an inductor of value 4nH in series and a capacitor
in parallel connected to ground is used to provide an isolation for
the biasing circuits from the RF circuits.
As can be seen from the schematic, there is a diode connected
MOSFET used in the circuit. This is used for providing
temperature compensation. As seen in the equations above if
there is a change in temperature (which causes an equal change
in the threshold voltage) the forward active voltage of the diode
connected MOSFET will reduce or try to cancel this deviation,
giving an almost constant stable output voltage. The precision of
this voltage in temperature cannot be compared to the precision
Fig. 9 Schematic for the 3.5 GHz Power amplifier with source offered by voltage references, but still can be considered a first
and load matching networks implementation for our chip.
IV. ADDITIONAL CIRCUITS
A. Bias circuits
Bias networks are an important part of the RF circuit design. A
good bias network is capable of providing stable sub voltages by
utilizing a single input power supply, thus reducing the pin count
and the package size.
The bias network determines the amplifier performance over
temperature as well as the RF drive. The DC bias condition is
usually determined independently of the RF design. Power
efficiency, stability, noise, thermal runway, and ease to use are
the main concerns when selecting a bias configuration.
A transistor amplifier must possess a DC biasing circuit for a
couple of reasons. We would require two separate voltage
supplies to furnish the desired class of bias for both the common
gate and the base gate voltages. This is in fact still done in certain
applications, but biasing was introduced so that these separate
voltages could be obtained from a single supply voltage.
Transistors are remarkably temperature sensitive, their threshold
voltage changing with temperature: this causes an undesirable
change at the drain and source of the MOSFET from which we
get the desired bias voltages, unless the amplifier is temperature Fig. 10 Schematic for the bias networks
stabilized to nullify this effect.
The schematic of the bias circuit is shown in fig.10. A passive
bias circuit approach using resistors can load the amplifier
creating extra losses and add source or emitter inductance. The
best practice is to directly ground the source for microwave
amplifiers. But, grounding the source leaves the devices wide
open to DC bias problems such as temperature drift of the bias
point for FETs. So, an active feedback circuit as shown below is
used. A simple approach utilizing a PMOS transistor is
frequently more efficient.
The equations governing the bias network are the following:
Fig. 11 Transient Response results for the bias circuit
ECE 6420 – Final Design Project – Group 7 6
We set the coupling efficiency K to 1 but we wanted to limit to
inductance of the transformer to 2 nH, as this is the common
upper limit for integrated transformers in planar CMOS
technology (i.e. if no MEMS are used).
Fig. 12 DC response of the system vs. a temperature sweep
B. Combining Circuit
This design implements power combination using both parallel Fig. 13 Investigated combining networks
combination (PCT) and series combination (SCT). In the power
stage, the two stages are combined using PCT, which has a
C. Switching Circuit
power combination ratio that depends on windings, load
impedance and source/load series resistances R1 and R2 by: Since a dual-band power amplifier was implemented, a switch
is required to switch between the power amplifiers depending on
the selected transmission frequency band. Figure 14 below shows
the switching circuit implemented in this design.
where M is the number of combined stages. On the other hand,
the three sub-Pas are globally combined using SCT, which power
combination ratio is:
At the inter-stage level, a secondary number of turns equal to 2 is
chosen in order not to modify the impedance seen by the two
stages, as discusses in the previous sections. At the source level
and at the load level, the number of windings is chosen based on
simulation data during loadpull and sourcepull as well as H1B
tone simulations results, in order to maximize to maximum linear Fig. 14 Switching circuit
output power.
Additionally, LC-lattice type balun combiners were investigated A binary input signal is received from the local logic processor.
to combine the output power of the three sub-stages. Following The input signal is 0V if the communication frequency is 2.4
the equations: GHz, and 3.2V if the communication frequency is 3.5 GHz.
Therefore the PMOS is turned ON for the 2.4 GHz
communication frequency and the NMOS is turned ON for the
3.5 GHz communication frequency. A current controlled voltage
source is connected to the drain of the PMOS and another to the
source of the NMOS. Therefore, when a particular MOSFET is
turned ON, the current controlled voltage source connected to the
MOSFET will have 3.2V across it. This voltage source behaves
we implemented the combiner, but we experienced difficulties in as the VDD to the power amplifiers. Therefore if the 2.4 GHz
using the LC-balun combiner together with the input/output communication frequency is selected, the VDD for the 2400PA
matching networks during the simulations. Hence, the design was would be 3.2V while the VDD for the 3500PA would be 0V.
implemented using transformers.
ECE 6420 – Final Design Project – Group 7 7
Implementing this design using power mosfets would be a The three power stages would then account for an approximate
possible design improvement. area of 250 by 150 µm. Assuming a similar reasoning for the 2.4
and the 3.5 GHz PAs, and estimating an output transformer size
of 1mm by 400 µm, an input transformer size of 250 by 400 µm
V. PACKAGING and accounting for on size matching networks and a shared bias
Amkor FlipChip technology is used in this design because of its circuitry for both PAs, the total area estimation would be around
high quality properties. This package family is specifically 1600 µm by 800 µm. By adding guard rings, bond pads for I/O
targeted for RF applications and the mobile handsets market, due pins and by letting some isolation space between critical sections,
to its low thermal resistance and low bondwire inductance added the worst case die size is estimated to be 3 by 3 mm.
to each I/O pin. The PA is then expected to work very similarly
to the original design even after packaging.
Since bondwires add to the inductance as a function of their
length and diameter thickness, by using the flipchip fcCSP1 their
impact is reduced. Flipchip does not involve interconnection
between the die and the package carrier using bond wires.
Instead, the connection is made through a conductive bump that
is placed directly on the die surface. The bumped die is then
flipped over and placed face down, with the bumps connecting to
the carrier directly. A bump is typically 70-100 μm high, and 90-
125 μm in diameter. The advantages of Flip Chip over bond
wires are reduced signal inductance, high signal density, die
shrink and reduced package footprint.
The identified package is 8mm by 8mm in size and can
accommodate a maximum die size of 7 by 7 mm, which is
compatible with this design. As far as thermal power dissipation
considerations are concerned, the 2.4 GHz power amplifier Fig. 15 Estimated die aspect, size and floor plan
dissipates around 3W (worst case condition in linear regime)
while 4.5W (worst case condition in linear regime) are dissipated Our design needs at most three pin types: ground, 3.2V Vdd, RF
by the 3.5 GHz power amplifier. Amkor’s fcCSP1 has a thermal input, RF output. At this high level the pin schematic is simple,
resistance (Rt) of 21.3˚C/W. but electromagnetic and thermal simulations and considerations
By following the next equation: would be necessary in order to decide where to distribute the pins
in a multiple fashion. Ground and Vdd would be distributed
using multiple pins, to increase voltage distribution uniformity
and reduce the amount of current flowing through every single
pin/pad. RF input and output signal would require a single pad,
= Junction temperature, limited to 125 °C due to signal integrity considerations. The 3.2V bias should be
= Ambient temperature (we have considered a temperature provided to the chip from the exterior using off chip power
range from 0 to 85 ˚C) inductors, like the MDT2012-CR from Toko, which has the
= Power dissipated required inductance (1 µH) and can withstand currents up to 1.55
A (our PAs require about 1 A in linear region).
This give a power dissipation range of 2W to 5.8W (assuming
that the PCB is an ideal heat sink). To operate in complete VI. RESULTS
reliability, the maximum ambient temperature for which the PA Results are schematically shown in table IV and they are
can transmit at full power at 2.4 GHz is 61.1 °C, which reduces compared to two PAs present on the market from Anagidics and
to 29 °C for the 3.5 GHz model. However, if we consider the Triquint. Some specifications are missing for the market
maximum output power for which the 3% EVM condition is products, but the comparison holds. The designed PA can
satisfied, there are no constraints since the PA have now a compete against these products, at least on a schematic
limited output power and the dissipation is much lower (reliable simulation level. However, the produced chip is expected to have
operation from 0 to 85 °C). worse performances. The linearity of the 2.4 GHz model is quite
As far as floor plan and die considerations are concerned, a rough good and EVM at 3% is obtained for an output power level of
die size can be estimated with the assumption of multi-finger 23.5 dBm, which is less than expected. The 3.5 GHz model only
transistor layout. The driver stage has transistors with W/L of reaches 12 dBm output power with EVM at 3%. The reason for
1000µm/0.18µm. The power stage has transistors with sizes W/L this results is the phase shift introduced on the output signal: this
of 4000µm/0.18µm and W/L = 4000µm/0.35µm. The estimated design has a very good gain compression for both bands, but the
size of the die is 3mm x 3mm, as shown in Fig. 15. AM-PM distortion is high. We could not improve this parameter
In the driver stage, each transistor can be designed with 40 no matter our efforts. One possible reason is the NMOS
fingers each 25 µm wide 0.18 µm long, so that a driver stage capacitance Cgs primarily at the input of the power stage. This
would approximately occupy an area of 60 µm by 20 µm. Since capacitance is a function of the bias point, which is variable for
we have 3 drivers, the total driver area would be 60 by 60 µm. class AB amplifiers. The biggest change in the capacitance takes
For the power stage, each transistor would occupy a 100 by 20 place for the transistor changing from saturation to triode region
µm area using 40 fingers layout (worst case).
ECE 6420 – Final Design Project – Group 7 8
and could be counterbalanced by using a varactor-connected
PMOS.
TABLE IV
Results comparison
2.4 GhZ 3.5 GHz
PA PA Triquint Anagidics
Current
P1dB 1.4 A 1.855 A - -
Current B 0.9 A 1.4 A - -
Current Idle 0.75 A 0.7 A - -
PAE B 21.5 % 18% 20% -
PAE B-5dB 9% 9.5% - -
PAE B-10dB 3% 4% - -
Absolute
Gain 29 dB 22.5 dB - 30 dB
Δ Gain -3dB -3.9 dB - -
Linear
Output
Power (-
0.25m) 28.15 dBm 29.74 dBm - -
P1dB 30.71 dBm 30.53 dBm 29.8 dBm 30 dBm Fig. 17 Gain
EVM 3% 23 dBm 12 dBm 23 dBm 25 dBm
Stability K>100 K>100 Stable Stable
Gain is very linear up to an output power of approximately 30
dBm. The third harmonic and the first harmonic behavior are
Bias 3.2 V 3.2 V 5V 3-5 V
shown next.
2.3 – 2.5 3.4-3.6 2.3-2.4 2.3-2.5
Band GHz GHz GHz GHz
A. Results (2.4GHz)
Results for the PA are shown in detail in the provided
attachment. Here we show just the most significative plots. The
waveform at the output is shown in fig.16.
Note that the voltage swing goes from -12 V to 12 V with the
input test signal and a gain of 29 dB, but the output voltage is
derived from the combination of three stages, that share the
swing equally. Moreover, each sub-PA consists of two output
power stages in parallel, with the last transistor 0.35 µm thick in
length. The operation is then safe.
AM-AM distortion is very small, but it can be seen that a phase
shift is present on the output waveform.
Fig. 18 Principal harmonic content
Gain compression and phase distortion are shown in the next
images. EVM is also plotted against a custom power index and
reaches 3% at about -8 dBm, which corresponds to
approximately 23 dBm output power. Any additional detail
about H1Btone simulation and H2Btone simulation, matching
networks details and EVM testing can be found in the addendum
and in the provided zap files.
The 2.4 GHz PA is also tested for compliance with the WiMAX
spectrum mask and the result is shown in fig 18. According to
fig. 1, the PA respects the spectrum limitations for WiMAX,
since the attenuation of the adjacent channels are sufficiently
high enough.
Fig. 16 Output voltage waveform
ECE 6420 – Final Design Project – Group 7 9
PAE also is too low at those conditions.
Fig. 19 Gain compression
Fig. 22 WiMAX mask compliance
B. Results (3.5GHz)
Detailed results for this PA can be found in the provided .zap
files.
VII. LIMITATIONS AND POSSIBLE IMPROVEMENTS
The linearity of the PA can be improved and techniques to
reduce the phase distortion should be introduced and
implemented. As mentioned, the PMOS exhibits an opposite
behavior of its Cgs capacitance as a function of gate voltage and
Fig. 20 Phase distortion could be used to counterbalance the Cgs variation of the input
NMOS of the power stage.
The EVM variation as an indirect function of input power is Additionally, the non idealities of the transformers should be
shown in the next figure:
better implemented, since a coupling factor K=1 was used in the
design. Each transformer should include a series resistance of a
few Ohms and a capacitance of a few fF to ground, for taking
into account the parasitic effects to the substrate. Moreover,
several coupling capacitors and additional resistances should be
included.
Finally, we would like to optimize the dual band aspect of the PA
by improving and optimizing the design of the 3.5 GHz version,
also trying different topologies and improved linearization
techniques. Especially considering the market analysis, a product
compatible with the two most widespread bands would have a
much greater chance to gain market share.
In conclusion, we would like to remark that we did try to include
a linearization system to improve the overall performances of the
PA, specifically digital predistortion. However, by using the
ADS template, we encountered major difficulties for
Fig. 21 EVM degeneration convergence and the required time for simulations was too high.
The 2.4 GHz PA can be considered our main design, while the
VIII. CONCLUSION
3.5 GHz an application to see if the same structure could have
been used for a different band, with the necessary tuning. Due to We successfully implemented a dual band CMOS PA with a
lack of time, we cannot say if the structure could be successfully two stage cascode amplifier topology and have met the
adapted for the 3.5 GHz band, since as it is now, it is not requirements for the 2.4 GHz band, while missing the
employable as a WiMAX product. The output power at which requirements in the 3.5 GHz band.
the EVM is 3% or less is too low, and doesn’t satisfy the
requirements for WiMAX at the antenna.
ECE 6420 – Final Design Project – Group 7 10
REFERENCES
[1] Ping Li, ”Overview of WiMAX system and related power amplifier
deisgn”, ICSICT 2008
[2] Kyu Hwan, “Power-Combining Transformer Techniques for Fully-
Integrated CMOS Power Amplifiers, IEEE JSSC 2008
[3] Kyu Hwan An, “A 2.4GHz Fully Integrated Linear CMOS Power Amplifier
With Discrete Power Control”
[4] B. Smith, “An approach to graphs of linear forms (Unpublished work
style),” unpublished.
[5] Bias Circuit Design for Microwave Amplifiers, UCSB ECE
[6] ……
