Heterogeneous Gateway for Wireless Multimedia by ajithkumarjak47


									National Conference on Role of Cloud Computing Environment in Green Communication 2012                                                                                           107

                             Heterogeneous Gateway for Wireless Multimedia
                                            Sensor Network
                                                                                  Asha Sharmi
                                                                      Computer Science and Engineering,
                                                     Sun College of Engineering and Technology, Anna University Chennai,

  Abstract- This paper presents the design and implementation of a Heterogeneous             instead of existing in isolation, multimedia sensor network should be accessed to
  Gateway for wireless multimedia sensor networks. The proposed framework is an              external networks, such as internet, PSTN (Public Switched Telephone Network),
  advanced FPGA (Field-Programmable Gate Array)-based sensor gateway. The                    Radio and TV Network and so on, via heterogenous gateway devices to supply
  Heterogeneous gateway provides interfaces for multiple networks like PSTN, CDMA,           remote access and monitoring of the wireless sensor network. In order to deliver
  Internet, and so on. It supports various application scenarios. The gateway also
                                                                                             the multimedia data from the multimedia sensor network to users with
  provides access to PSTN via HDLC protocol [1], which has been the widely used
  protocol in the field of data communications. This paper first analyzes the overall        convenience, the key is how to design heterogeneous gateway for multimedia
  structure and the implementation principles of HDLC, then illustrate the                   sensor networks.
  implementation of key modules by using FPGA.
  Keywords—Multimedia Wireless Sensor Networks; FPGA; PSTN; CDMA; HDLC                           In this paper we design a multi-access system architecture for smart home,
                                                                                             which is shown in Fig.1. The overall system made up of a core embedded
                  I. INTRODUCTION                                                            gateway, router nodes, sensor nodes, actuators and information-push nodes. The
     Environmental monitoring describes the processes and activities that need to            core embedded gateway analyses the data collected from sensor nodes and sense
  take place to characterise and monitor the quality of environment. As the                  corresponding commands to actuators. Information-push nodes are used for
  increasing complexity of environmental monitoring system, data such as                     illustrating important information from the gateway on to the LED (Light
  temperature, humidity and light gathered by common wireless sensor networks                Emitting Diode) display.
  cannot meet the overall human requirements of environmental monitoring. In
  general, most of the applications of wireless sensor networks have low bandwidth
  demands and are usually delay tolerant[2]. In order to achieve the fine-grained and
  accurate environmental monitoring, there is a pressing requirement to introduce
  image, video, audio and some other multimedia information to the sensor
  networks, so as to monitor the environmental activities. Multimedia Sensor
  Networks [3] have become a research hot spot. In some wireless multimedia sensor
  network applications, such as home automation, RMON (Remote Monitoring)
  through cell phone or internet has become a necessary requirement. Therefore,

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                                                                                       response, and predictable simulation. Additionally, by using dynamic and partial
                                                                                       reconfiguration technology to design HDLC protocol controllers, it can support
                                                                                       vast different types of applications.

                                                                                          In this paper, the implementation of the HDLC protocol controller is illustrated
                                                                                       during the design process of the interconnection of our gateway and PSTN. The
                                                                                       rest of the paper is organised as follows. Section 2 briefly summarizes related
                                                                                       works and Section 3 describes the overall design of the HDLC chip‟s architecture
                                                                                       based on FPGA. Section 4 illustrates the design of HDLC‟s on-chip modules.
                                                                                       Finally the paper is concluded in Section 6.

                                                                                                      II.   RELATED WORKS
                                                                                       1) Gateway in Wireless Sensor Network
                                                                                          Gateway is the bridge between sensor network and end users. Some gateway
                                                                                       prototypes for wireless sensor networks have already been proposed and
                                                                                       implemented. The gateway architecture proposed in [4] achieved web-based
                                                                                       management for wireless sensor networks. In [5], the author designed gateway of
                                                                                       wireless sensor networks based on Zigbee and GPRS. Some other gateway
     The embedded gateway is the core device in the system. The gateway receives       prototypes for wireless sensor networks also have been proposed in [6], [7] and [8],
  a variety of environmental data such as temperature, humidity, light, audio, image   but they are application specific and could not meet the variety requirements of
  and so on from the wireless multimedia sensor network. It then makes decisions       different environments and situations.
  and then sends commands. It connects heterogenous networks through the
  integration of ZigBee module, HDLC (High data Link Control) module, Bluetooth           The gateway architectures mentioned above are mostly weak in providing
  module, GSM and CDMA Module, as well as Wi-Fi module in the smart home               abundant interfaces and lack of network interoperability. Their capabilities of user
  system.                                                                              interaction are very limited and cannot meet the needs of modern home
     PSTN is the most commonly used circuit-switched voice communication               automation applications. The core embedded gateway proposed in this paper is
  network in our daily life. Hence, the introduction of PSTN into our system can       comprised of several key modules. Because of the providing of multi-interface of
  build a bridge between telephone users and wireless multimedia sensor networks.      the embedded gateway‟s architecture, it can support various user terminals and
  Moreover, the gateway is the hub of different networks hence its processing and      various application scenarios. In addition, the realization of PSTN access enriches
  transmission capacity should be high enough. Therefore when we design the            the access methods of the embedded gateway and obviously enhances both the
  access interface to PSTN network in order to ensure the reliability of information   practicability and flexibility of the whole wireless sensor network.
  during the process of data transmission HDLC protocol is adopted.
                                                                                       2) Implementation of HDLC Protocol
     Meanwhile, we use FPGA to design the HDLC protocol so as to improve the
  processing speed, since FPGA plays a significant role of prototype verification in     HDLC is a high-level data link control protocol established by International
  the development process of SoC (System on Chip) and is an indispensable              Organization for Standardization. It has been so widely implemented because it
  verification method of SoC design. FPGA has hardware processing speed and can        supports half-duplex communication, peer to peer and multi-point networks, and
  be reprogrammed on demand. Hence, it supports parallel process, real-time            switched and non-switched channels.

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National Conference on Role of Cloud Computing Environment in Green Communication 2012                                                                                         109

                                                                                              3) Receiving and sending interfaces of HDLC: Transmission between two
     HDLC procedures are commonly performed by ASIC devices, software                       HDLC chips is implemented via simply joint. HDLC chip supports two
  programming and so on. ASIC devices used to be designed for specific purposes,            transmission modes, BUS mode and TDM mode.
  so they lack flexibility in different applications and it is difficult for ASIC devices
  to meet all the requirements of various versions of HDLC protocol. In addition,           B. Design of On-chip
  on-chip data storage capacity in ASIC is limited. IF we intend to expand its data
  storage capacity, we can only use external storage devices or other circuits.             The internal design of HDLC chip is shown as Fig. 2 below.
  Software programming of HDLC procedures is flexible, which can be used in
  many different HDLC applications by modification of it. However, the programs                    1) Controller Module: The chip controller module includes R/W access to
  take many resources out of the processor and a lot of time when running. So               control registers and IRQ module. The controller module will be discussed in
  software programming is often used in single channel and low-speed signal                 more detail in subsection 4.1.
  processing system.

     FPGA device runs at hardware level, and its logic can be reprogrammed by                     2) Tx FIFO Module:         It is an asynchronous dual-port FIFO. CPU
  hardware processing technology. Hence, HDLC procedures can be implemented                 implements FIFO writing via SLB‟s write clock. After the read clock is generated
  in FPGA by hardware programming [8-11]. When using FPGA, multi-channel                    by Transmit FSM, FIFO data is transmitted to HDLC Transmitter.
  signals are processed in parallel, the real-time capacity is predictable and easy to
  be simulated. The advantage of implementing HDLC protocol in FPGA is that it
  gives you the flexibility, upgradability and customization benefits of
  programmable logic devices.


    In this design, a HDLC chip mainly consist of off-chip interfaces with
  peripheral equipments and on-chip modules.

  A. Design of off-chip Interfaces
     Off-chip interfaces of FPGA involve the three following parts:

     1) Interfaces between HDLC and CPU: CPU and HDLC chip are connected via
  a SLB (Simple Local Bus) interface. CPU operates HDLC‟s registers over this
  interface to implement configuration and data transmission.

    2) HDLC chip clock: The sending and receiving clock is generated by several
  external crystal oscillators (OCS). In addition, this chip is designed to support
  multiple clock modes.

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                             Clock                               Power                                   5) Rx Module: This module includes two modules, HDLC Receiver and
                                                                                                       Receive FSM. Implementation details are shown in subsection 4.3

                                     T*FIFO                 HDLC Transmitter      T*D
                                                                                                         6) Clock Controller Module: The time mode of the HDLC Receiver and
                                                                                                       Receive FSM. Implementation details are shown in subsection 4.3.

                                                           Transmit FSM
                                                                               Time-slot Control          7) Time-slot Module: We can also implement transmission control in time-slot
                                                                                                       mode. When time-slot comes, Time-slot module receives related configuration so
                                       IRQ                  Clock Controller                           as to output control signal to enable transmit FSM and Receive FSM. The state
               /OE                                                             R*clk/T*clk/A*clk(FS)

                                                                                                       machine only operates in the time-slot so that to control the receiving and sending
                                                              Receive FSM                              processes of data.
      SLB 0


               /WE                                                                                                       IV. DESIGN OF HDLC‟S ON-CHIP MODULES

               /CS                                                                                     A. Design and Implementation of Controller

                                      R* FIFO                HDLC Receiver              R*D                CPU and HDLC chip are connected via SLB Bus. By SLB Bus, CPU can
                                                                                                       operate FPGA HDLC chip‟s registers through the chip-select and address lines in
                                                  HDLC Controller                                      the same way as external memory. Through EMC (External Memory Controller)
                                                                                                       module, CPU maps FPGA HDLC module‟s register address to the chip‟s address
                                                                                                       space, and software only needs to read and write the appropriate address. SLB Bus
                       Figure2. Chips architecture diagram                                             is the minimum set of CPU External Memory Bus Operation. CPU interacts with
                                                                                                       FPGA HDLC by CS/OS/WE/Address/Data/INT etc. Tab.1 summarizes the
                                                                                                       definition of SLB pins.

      3) Tx Module: This module includes two sub-modules, HDLC Transmitter                                TABLE I. Definition of SLB Pins
  and Transmitter FSM, FIFO data is transmitted to HDLC Transmitter.
                                                                                                                        Pin                Type            Description
        4) Rx FIFO Module: In this module, several blocks combine to build up a
  queue, and every block is asynchronous dual-port FIFO. CPU implements FIFO                                            ___
  reading via read clock. After the write clock is generated by Receive FSM, data in                                    CS                In              Chip Select
  Receiver is transmitted to Rx FIFO can adjust the size of every Block and the total                                   ___
  number of all Blocks with flexibility. Flexible adjustment can meet various                                           WE                In              Write Enable
  receiving requirements. Small frame can be stored in every single block and large                                     ___
  frame can be stored in several Blocks. Through such design, interruption times to                                     OE                In              O-Enable
  CPU can be reduced effectively.
                                                                                                                        D[0:16]           I/O             Data-Line

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                   A[0:16]           In              Address-Line
                   _________                         HDLC Terminal
                   HDCCINT            Out            Service Request

     In controller‟s internal module, by SLB, register settings module receives R/W
  signal from CPU, configures related registers, and outputs related control signals
  to other modules. IRQ_Handler is an interrupt processing module. This module is
  connected with SLB, and it can read and write IRQ_Enable (interrupt enable)
  register and IRQ_Status (interrupt status) register. The other sending and
  receiving control signals, such as FIFO Empty, TX Under-run, TX Done and so
  on, access to this module and play the role of control signals which generate             b) State Transaction Module: This module is a combinational logic, and it is
  interrupts. Read-clear mode is adopted to clear the interrupt status register.         used to output the next_state signal to the State Machine Driver module.
                                                                                         According to the current state and semaphore‟s situation, the next state is
  B. Design and Implementation of Tx Module                                              determined.

      Tx Module includes two modules, HDLC Transmitter and Transmit FSM.                    As shown in Fig.4, the initial state of the machine is IDLE; once FIFO is not
  Transmit FSM is in units of 8 bits, and it sends control signals and frame head,       empty, which means there has data to be sent, the state machine jumps into the
  address, FCS etc. to HDLC Transmitter, and sends frame data in the way of FIFO.        FLAG state and sends 0x7e. According to the configuration, whether to send the
  After receiving the sent data bytes, Transmitter inserts extra zeros into the bit      address is determined. If sending address, the state machine jumps into the
  stream and sends them out. SSM (Sending State Machine) is the control center of        TXAD1/TXAD2 state. After jumping into the SDATA state, data in FIFO is
  the whole sending module. According to the writing state of Tx FIFO and the state      transmitted. If receiving the End of Package command, the state machine jumps
  of the registers of Controller module, it implements state skip, sends different       into the FCS state, transmits the frame check, then the TEM1 state, sends 0x7e,
  control instructions and data in different states, and starts HDLC sending.            and finally goes back to IDLE state. If FIFO Empty signal is generated in the
                                                                                         SDATA state, the state machine jumps into the URUN state, which means that
     1) Transmit FSM                                                                     under run is transmitted. If Abort command is received, the state machine jumps
                                                                                         into the ABORT state and cancels current frame sending.
          Transmit FSM adopts Driver-Transaction-Action as its design architecture,
  and it includes modules as follows:

      a) State Machine Driver: As shown in Fig.3, TxClk provides the clock.
  IRead signal (iRead signal, which comes from HDLC Transmitter module of the
  underlying state machine, indicates that a byte has been sent and needs data from
  the upper state machine) is enabled to drive the state variable‟s transferring. That
  is to say, next_state signal, which comes from the State Transaction Module, is
  converted into current_state, thus state skip is implanted. The output current_state
  is the current state.

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National Conference on Role of Cloud Computing Environment in Green Communication 2012                                                                                                112

                                  IDLE                                                           b) State Transaction Module: The State Transaction module is the
                                                                                             combinational logic of state machine‟s jump conditions. According to the current
                                              Tx Enable & FIFO Not Empty
                                                                                             transmission and state, the state of the next bit is output. Meanwhile, whether to
                                                                                             jump to zero insertion state to implement zero insertion is determined. The output
                                                                                             of the next state is next_state, and it is output to the State Machine Driver as the
                                 FLAG                                                        next state. State Transaction Module judges the total number of “1”, according to
                                                                                             the bytes sent by the higher layer. If the number of “1” is more than 5, jump to
                                               Tx Address Enable?
                                                                                             the zero-insertion state and send 1 bit 0;If not, send data directly. The state
                                                                                             machine has 9 states altogether, namely IDLE,BIT0-BIT7 and INS. IDLE is the
                                                                                             idle state; BIT0-BIT7 stand for the transmit states every bit of bytes; INS
           ABORT                          No
                                                                                             represents the zero-insertion state. In each state, the number of “1” of the sent data
                                                                                             is calculated by the bit-count register. When bit-count equals to 4, then jump into
                                                                                             the INS state.
                                                                                 Tx 2 Byte
                             SDATA                                               Address

                       End of package
                                                                                                 c) State Action Module: This module is responsible for implementing
                                                                      TXAD2                  different operations in different states. Clear bit-count in IDLE state; In BIT0-
        TEM1           No
                                                                                             BIT7 states, transmit the end of the data and clear bit-count or plus 1 to bit-count
                                                 FIFO Empty                                  according to the bit content. Transmit 1 bit 0 and clear bit-count, in INS state.
                     Yes                                                  URUN
                                                                                             C.   Design and Implementation of Rx Module
         FCS                                                                                     Similar to Tx Module, Rx Module adopts the state machine with double-layer
             Figure 4. State Machine Driver Module                                           architecture. That is to divide the whole sending procedure into two layers, and
                                                                                             two relatively independent state machines run in the two separate layers. The
      c) State Action Module: According to the current state, the State Action               upper state machine represents the Receive FSM, while the underlying state
  module implements corresponding operations, mostly determining the contents of             machine stands for the HDLC Receiver. As shown in Fig.5,Receive FSM receives
  the output data.                                                                           various kinds of control signals and data, implements state transition by various
                                                                                             kinds of control signals, decides the operations required in the current state, and
     2) HDLC Transmitter                                                                     transmits the operating instructions to underlying state machine HDLC Receiver.
                                                                                             Having received the data, the underlying state machine determines whether to
          HDLC Transmitter is a state machine, too. It adopts Driver-Transaction-            implement zero-remove to the received data, according to the instructions of the
  Action as its design architecture, and it includes modules as follows:                     upper layer. The processed data will be transmitting to the upper layer state
                                                                                             machine and the receiving FIFO. The upper layer‟s state and the Transmit FSM
      a) State Machine Driver: Driven by the sending clock TxClk, the State                  implement state transition and control, according to the received data and control
  Machine Driver sets current_state register‟s value to next_state to implement the          commands. The single-byte clock, which is generated after 8 bytes received (zero
  state‟s jumping at the clock rising edge.

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  remove or not) and is sent by the receiver Module, is the driver of the                                                                  REFERENCES
  implementation of state transition.                                                            [1]    ISO/IEC 3309:1993 (E), Telecommunication and information exchange between system-high-
                                                                                                        level data link control(HDLC) procsdures-Frame structure[s].

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                                                             iFlag & FIFO
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      Iflag?                                                                   Wrong
                                            Yes       text

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                                  iFlag       text    No                               2 Byte
                                                                               text   Adddress
                                  text                                                 Detect
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                                                                                                        Lv Richao; Shen Lianfeng; hu Jing; “Design and Implementation of a Wireless Sensor Network
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                                          Figure 5. Rx FSM                                              International Conference on Information Science and Engineering, 2009

                                                                    V. CONCLUSIONS
                                                                                                 [8]    Ye Dun-fan; Min Liang-liang; Wang Wei, “Design and Implementation of Wireless Sensor
     In this paper, we present the design and implementation of an advanced FPGA-                       Network Gateway Based in Environmental Monitoring”, International Conference on
  based heterogeneous sensor gateway for wireless multimedia sensor networks.                           Environmental Science and Application Technology, 2009
  According to different application scenarios, potential users can choose among
  PSTN, ZigBee, HDLC, Bluetooth, GSM, CDMA, and Wi-Fi interfaces to access
  to the network at their convenience and as their wishes. In conclusion, through our            [9]    Jun Wang;Wenhao Zhang;Yuxi Zhang; Wei Wu; Weiguang Chang, “ Design and
  gateway, a fully functional sensor network can be eaily built and deployed. Future                    Implementation of HDLC procedures based on FPGA”, Anti-counterfeiting, Security and
                                                                                                        Identification in Communication, 2009.
  work mainly focuses on security. As the gateway connects divided sub-networks
  together, it‟s necessary to prevent attacks from every sub-network. As sub-
  networks increase, we also need to deal with some data processing work such as
                                                                                                 [10]   Guozheng Li; Nanlin Tan, “Design and Implementation of HDLC Protocol and Manchester
  distributing storage and amalgamation.
                                                                                                        Encoding Based on FPDGA in Train Communication Network:, Information and Computing
                                                                                                        (ICIC), 2010 Third International Conference.

  Department of CSE, Sun College of Engineering and Technology
National Conference on Role of Cloud Computing Environment in Green Communication 2012            114

  [11]   Bi Huang; Zhigong Wang; LuFeng Qiao; Yuanlin Lu, “Design of a multi-channel high speed
         FIFO applied to HDLC processor based on PCI bus”, Circuits and System and West Sino
         Exposition, 2002

         Lufeng Qiao; Zhigong Wang, „Design of DMA Controller for Multichannel PCI Bus frame
         Engine and Data Link Manger”, Circuits and Systems and West Sino Expositions, 2002

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