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More on Mutual Exclusion with Read/Write Variables Slides by Prof. Jennifer Welch 1 Number of R/W Variables • Bakery algorithm used 2n shared read/write variables. • Tournament tree algorithm used 3n shared read/write variables. • Can we do (asymptotically) better, in terms of fewer variables? • No! 2 Lower Bound on Number of Variables Theorem (4.19): Any no-deadlock mutual exclusion algorithm using read/write variables must use at least n shared variables. Proof Strategy: Show by induction on n there must be at least n variables. For each n, there is a configuration in which n variables are covered: means some processor is about to write to it. 3 Appearing Quiescent • Two configurations C and D are P-similar if each processor in P has same state in C as in D and each shared variable has same value in C as in D. • A configuration is quiescent if all processors are in remainder section. • To make the induction go through, the configuration whose existence we prove must appear quiescent to a set of processors: – C is P-quiescent if there is a reachable quiescent configuration D such that C and D are P-similar 4 Warm-Up Lemma Before a processor can enter its CS, it must write to an uncovered variable. Lemma (4.17): If C is pi-quiescent, then there is a pi-only schedule such that (a) pi is in CS in (C) and (b) during exec(C,), pi writes to a variable that is not covered in C. 5 Proof of Warm-Up Lemma (a) • Since C is pi-quiescent, it looks the same to pi as some quiescent D. • By ND, some pi-only schedule exists starting at D in which pi enters CS. • When starts at C, pi also enters CS. D quiescent pi in CS by ND C pi-quiescent pi in CS 6 Proof of Warm-up Lemma (b) • Suppose in contradiction when is executed starting at C, pi writes to the set of variables W but all the variables in W are covered in C. • Let P be the set of processors covering the variables in W. C 1 E 2 Q some pj (not pi) one step by each successively invoke ND to takes steps alone; proc in P; over- cause all procs by ND eventually writes W to be in remainder; pj enters CS pi takes no step 7 Proof of Warm-up Lemma (b) C 1 E 2 Q overwrites W successively pj-only pj in CS invoke ND pi-only, writes to W C' 1 E' 2 Q' pi in overwrites W successively pj-only pj in CS, CS invoke ND pi in CS Only difference between C and C' are the writes by pi, but those values are overwritten in 1 so the info is lost. 8 Main Result For all k between 1 and n, for all quiescent C, there exists D s.t. (a) D is reachable from C by steps of p0,…,pk-1 only (b) p0,…,pk-1 cover k distinct variables in D (c) D is {pk,…,pn-1}-quiescent. implies desired result when k = n 9 Proof of Main Result - Basis By induction on k. Basis: k = 1. Must show for all quiescent C, there exists D s.t. (a) D is reachable from C by steps of p0 only (b) p0 covers a variable in D (c) D looks quiescent to the other procs. • By warm-up lemma (a), if p0 takes steps alone, it eventually writes to some var. • Desired D is just before p0 's first write. 10 Proof of Main Result - Induction Assume for k, show for k+1. 0 C C1 any qui. only p0 to p0 to pk-1 config. pk-1 take cover W steps pk-only D1' pk covers p0 to pk-1 overwrite W, pk in entry x not in W become quiescent looks qui. to rest 11 Proof of Main Result - Induction 0 C C1 D1 C2 any qui. only p0 to p0 to pk-1 qui. p0 to pk-1 p0 to pk-1 config. pk-1 take cover W only cover W steps pk-only but why is the same set of k vars covered again? D1' C2 pk covers p0 to pk-1 pk in entry p0 to pk x not in W o'write W, looks qui. cover W become to rest and x quiescent 12 Proof of Main Result - Fix • The result of applying to D1 might result in a different set of k variables, W', being covered instead of W. • If W' includes x, we have not succeeded in covering an additional variable. • To fix this problem, repeatedly apply inductive hypothesis to get C1,D1,C2,D2,C3,D3,… • Since number of variables is finite, there exist i and j such that in Ci and Cj the same set of k variables is covered. • Then apply same argument as before, replacing C1 and C2 with Ci and Cj. 13 Fast Mutual Exclusion • The read/write mutex algorithms we've seen so far require a processor to access f(n) variables in the entry section even if no contention. • It would be nice to have a fast algorithm: if no competition, a processor enters CS in O(1) steps. • Even better would be an adaptive algorithm: performance depends on number of currently competing processors, not total number. 14 Fast Mutual Exclusion • Note that multi-writer shared variables are required to be fast. • Combine two mechanisms: – provide fast entry when no contention – provide no deadlock with there is contention 15 Contention Detector Overview • A doorway mechanism captures a set of processors that are concurrently accessing the detector • Use a race to choose a unique one of the captured processors to "win" 16 Contention Detector Uses two shared variables, door and race. Initially door = "open", race = -1. 1 race := id 2 if door = "closed" then return "lose" 3 else 4 door := "closed" 5 if race = id then return "win" 6 else return "lose" 17 Analysis of Contention Detector Claim: At most one processor wins the contention detector. Why? • Let K be set of procs. that read "open" from door in Line 2. • Let pj be proc. that writes to race most recently before door is first set to "closed". • No node pi other than pj can win: – If pi is not in K, it loses in Line 2. – If pi is in K, it writes race before pj does but checks again (Line 5) after pj 's write and loses. 18 Analysis of Contention Detector Claim: If pi executes the contention detector alone, then pi wins. Why? • Trace through the code when there is no concurrency. 19 Ensuring No Deadlock • If there is concurrency, it is possible that no processor wins the contention detector. • To ensure progress: – nodes that lose the contention detector participate in an n-processor ME alg. – The winner of the n-processor alg. competes with the (potential) winner of the contention detector using a 2-processor ME alg. – Winner of 2-processor alg. can enter CS 20 Ensuring No Deadlock lose contention detector win n-proc. mutex play role of p0 play role of p1 2-proc. mutex critical section 21 Discussion of Fast Mutex • Be careful about the exit section: contention detector needs to be reset properly • This is a modular presentation: doesn't specify particular n-proc and 2-proc subroutine mutex algorithms • Not adaptive: even if only 2 procs are contending, execute the potentially expensive n-proc algorithm 22

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