High Speed Digital Systems Laboratory

Document Sample
High Speed Digital Systems Laboratory Powered By Docstoc
					                             HS DSL


   PowerBench
Programmable Power Supply



       Dror Lazar
     Moran Fishman
  Supervisor: Boaz Mizrahi
   Winter Semester 2009/10
   Project Overview - Reminder


  A versatile power supply unit with
multiple outputs for laboratory use and
testing of various electronic devices.
               Overview
        A brief reminder  Overview
                       A brief reminder




                                                   User interface


                                                Power               D
                                                supply              U
                                                                    T
  Control unit

                                          Measurement
                                              unit


 User interface for standalone
                      operation                Active load
LEDs       LCD            Keys
                                       Overview
                                 Control Scheme
                                           Overview
                                        Control Scheme




   Output
                                                             DAC
   setting
                                                                          Current
                 Controller                     DC-DC            Post
    Input                      PWM                                          Sense Output
   voltage         Block              Converter            regulator
    sense
                 & Registers
    feed-
                                                         Auxiliary
  forward
                                                          Voltage
   Tempe-
                                                   ADC      Sense
    rature

   Current                                                       ADC
      limit                                                             Voltage
                                                           ADC            Sense

Microprocessor                 FPGA
                        Implementation
1) System & Board design (2 semesters)– completed 
  3 separate boards :
    - “Digital” – control board
    - “Analog” – sink/source/measurement (SSM)
    - “Panel” – user interface (UI)

2) Hardware bring-up & FPGA design (semester) – our project
   - Analog board bring-up, Digital board power-path debug
   - FPGA design : A/D & D/A interfaces, PWM, SMPS controllers
   - PC –> Cypress –> PIC basic implementation
   - PIC – FPGA interface

3) Software design (semester) – another project
    - PIC microprocessor software
    - Cypress USB controller software
    - PC drivers and applications
                 Analog Board Bring-Up
- Buck converters
- Buck converters A/Ds
- LDOs
- LDOs D/As
- LDOs A/Ds
- Cuk converter
- Cuk converter A/D

- Source operation :
   - Full-path bring-up : PC  USB  PIC  FPGA  Bucks / Cuk  LDOs
    DUT
   - PWM duty-cycle step response with various loads connected to LDOs
     outputs

- Load operation :
   - FPGA configures path to load mode.
   - FPGA configures load-circuit D/A to constant current sink.
   - connecting laboratory power supply, checking current sink.
   - changing current sink amount – checking step response.
                FPGA Controller Design
• 2 control loops : Bucks / Cuk control loop
                   LDOs control loop
• implement controller using SMPS controller design principles.
• integrate with A/D & D/A interfaces in FPGA
• check controller performance : step response, O.S, settling time



           PC – PIC – FPGA Interface Design
• designing communication protocol to PIC microprocessor using SPI
interface (registers in FPGA)
• implementing basic software in PC & PIC – different scenarios in
Source & Load modes.
• check FPGA measurements from A/Ds in both modes with PC software
                                Timetable
               4/3
                      System introduction                         FPGA configuration-
               11/3     Verilog learning                   20/5   LDOs,2-ch A/D,D/A
                                                                      Bring up
                                                           27/5     Negative channel
               18/3      Design FPGA
                       Modules req. for                              Bring up (Cuk)
                                                           3/6
               25/3     Bucks bring-up                               SMPS controller
                                            Mid semester   10/6      Design – 2 loops
               1/4     FPGA modules         Presentation
                        simulations                        17/6
                                                                    Full path debug –
               8/4
                      FPGA configuration-                  24/6     Source operation
                        Bucks,4-ch A/D
               15/4
                           Bring up                        1/7
                        Design FPGA                                 Full path debug –
               22/4                                        8/7       Load operation
                       Modules for LDOs        Final
                           bring-up         Presentation
               29/4                                        END
      Char.
Presentation            Digital board
               6/5    Power path debug

               13/5     PIC – FPGA
                      Interface design
Questions




   ?

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:4
posted:7/21/2012
language:
pages:9