Document Sample

ASIC for Electronic musical keyboards.
Increased competitiveness using VHDL methodology in


AE abstract
KORG Italy, founded on October 1996, projects implements and produces innovative electronics musical
instruments, within the segment of digital pianos and ACC Keyboards, whose sound is generated by means
of digital synthesis. (prodcom code 3630: musical Instruments). KORG Italy (23 employees mainly involved
in electronic design, 20500 units sold in 1998) currently produces digital pianos and ACC (accompanying)
keyboards for end customers (amateurs musicians). The difference between an ACC keyboard and a digital
piano consists in the keyboard being more developed from an electronic point of view (sound reproduction)
while the digital piano focuses on high quality, realistic piano sound generation, and it has a weighted
keyboard.    The product application area is musical instruments for entertainment. All these families of
instruments will be replaced, within two years, by totally new products that must be more powerful but not
much more expensive than the current ones. The current technology knowledge of the company for what
concerns Hardware design consists in mixed analogue/digital PCBs. The products innovation is strictly linked
to the innovation of the mainboard, an analog/digital board with microprocessor, memories and peripherals
Object of this A.E. is a significant innovation to the mainboard of an ACC keyboard achieved through the
introduction of the gate array ASIC technology and VHDL design methodology, in order to integrate in a
single chip most      of the discrete electronics present in the mainboard. This modification allowed
performances improvement of the pianos functionalities, introduction of new features like Stereo Hard Disk
recording and playback, reduction of ‘time to market, a more user friendly interface, and can also be spread
out on many families of Korg’s products. All these improvements, achieved through this AE, were needed to
maintain and ameliorate the company market share and most of all its competitiveness, better answering to
the market needs.
The AE has a duration of 21 months and, within this period the AE had a cost of 114 Keur (FUSE funding for
110 KEUR). The costs of the Experiment with foundry efforts are 129 Keur. The payback period is 18 month.
The ROI is 322% over 5 years.
The application experiment is of interest for the electronic musical instruments industry.

Keywords and signature

4   0410-555-0410 2 3630            1   32     I


Musical instruments, digital pianos, VHDL, digital gate array ASIC, ACC keyboard, FPGA prototyping,gate

array, PC based tools,. music.

1.   Company name and address

Korg Italy S.p.A.

Via Cagiata 85 60027 Campocavallo di Osimo (AN) Italy

phone 071-7231309

fax 071-7231228

contact person Franco Ripa

2.   Company size

The company has 23 employees, 16 of which directly involved in software, hardware and mechanical design.
The company turnover referred to last year is 8000 Keur. KORG Italy is the Italian branch of KORG Japan,
devoted to the specific European market needs. The following pictures show respectively a typical home
keyboard and a typical digital piano.

3.   Company business description

KORG Italy business is the design, implementation and production of electronic music instrument in the
segment of digital pianos and home keyboards (ACC keyboard).
The typical selling price of a Digital Piano is 2,4 Keur, while for the ACC keyboard is about 1,3 Keur.
This business is supported by a strong R&D structure which covers many design areas (starting from
software development to 3D mechanical design, through hardware design and prototyping), a production
control department (to manage production done by third parties, so called “outsourcing”) and a musical
department where musical pattern are developed and tested.
Industrial sector: musical Instruments (.prodcom code 3630).

4.   Company markets and competitive position at the start of the AE

In Europe the Business to Business Musical instruments market is about 2500 bmillions of Euro.
About the 25% of this Market is on Electronic Musical Instruments.
This Market is evolving slowly (It's almost constant) but continuously mainly due to the following factors:
-- Number of working hours is decreasing in many industrial sectors, so there is much more time that can be
devoted to leisure (music, sports etc..)
-- Increasing welfare in European Countries
-- Climatic aspects (North European countries inhabitants for climatic reasons tend to remain more at home
and make large use of 'Home Keyboards' for free time)
-- Increased Musical culture in primary schools

The products of KI are mainly the Digital piano and the ACC keyboard. These two categories of musical
instruments comprising a series of products with different features.
Digital Pianos are vertical pianos whose sound is generated by means of digital synthesis.
ACC Keyboards are Electronic keyboards, having capability of digital synthesis of a wide variety of sounds;
such kind of instruments can generate various rhythmical patterns. The patterns can be used by musicians
as basis for a melody, played in real time.

The strategy of Korg Italy was focussed on the innovation of both categories of musical instruments, even if
this objective has been scheduled to be realised in different steps.
The first product that is innovated is an ACC keyboard (IS400) whose main board (the core of the entire
system) has become the object of the innovation to be carried out by technology barriers break through
(ASIC technology).

Through market research the company learned that today the market is basically divided in three segments:
professionals, amateurs, and beginners.
A brief abstract follows.


This segment includes:
•     People who perform music as a job, being involved in recording sessions, TV shows, live concerts, and
      so on.
•     Structures and institutions that deal with music, such as theatres, private and public TV networks,
The impulse to purchase comes from profession requirements; musicians want instruments to fit their skill.
No one of all the parameters which usually influence a choice - such as quality, performances, brand, and
price - clearly override the others.


This is the broadest and most complex segment, since it includes the large part of market's customers.

Consumers' attitudes cannot be reduced to a simple formula; for instance, the experienced customers - often
part-time professionals - act like real musicians rather than hobbyists.
Brand loyalty is a common element to all of such customers; however, as far as concerns semi-professionals
it is the result of a lasting satisfaction, while for hobbyists it is rather a status symbol.
Quality and performances affect the choice in direct proportion to skill increase.
Price is always important: to semi-professionals, who watch the quality/cost mix, and to hobbyists, in relation
to disposable cash.


Beginners buy a musical instrument once (or very few times) in their life.
They generally play music for passion or for fashion.
Price is a decisive element.
However, beginners' choice is also affected by the brand name, as this is often the only element customers
know about a product; therefore, marketing shall insist on advertising and sponsoring.

The AE market share is 14%. The industrial sector of the company is musical instruments.

The Company AE market targets are twofold:
•   Simplification of instruments utilisation that meets market requirements.
•    The second very important target to be reached by this AE consists in merging sampled sound and
    physical modelling (i.e. the capacity to reproduce natural sounds by means of mathematical process).
The innovation of the product will be shifted down to the lowest segment of the market (from professional to
KI's purpose is to use innovation in order to increase its presence in the amateurs segment, maintaining
unaltered its high quality standards.
The sales for end users market is carried out by external dealers network.

The new features that, according to us, are at the moment demanded by the market (and could be provided
thanks to this AE) are the following:
-   A raise of the performance/cost ratio.
-   Serial communication interface to a device used to display text on an external monitor or TV color
-    CD-ROM interface.
-   A more user friendly interface
-   A bigger LCD display
-   Hard Disk sound recording

The competitors of the company are the big manufacturers of musical instruments well known at an
international level.
From a technological point of view, some of them surely make use of high level technologies (i.e. ASIC),
therefore it was a company target to achieve their level.

KI's products will be destined, to a large extent, to the European market. Its sales channels are musical
instruments distributors in each country. The main idea is to create a wide range of instruments, fitting the
variety of European tastes. KI's purpose is to use innovation in order to increase its presence in the
amateurs segment maintaining unaltered its high quality standards.
Following these objectives the market share of company is increasing as shown in the following graph:

                                                Europe Market share






            5                                                                                             Market Share (%) 1997

            0                                                                                             Market Share (%) 1998

                                       Korg Italy


                                                                                                          Market Share (%) 1999

AE product pricing for the end user in 1999 is about 2,4 KEUR for Digital piano and 1,3 Keur                                     for ACC
keyboard. The lifetime of ACC keyboard is 2 years.

The AE product strengths are:
• PCM sound quality
• Styles quality
• Good ratio Quality vs. Price

In the following diagram the sales and the turnover produced in the last three years is shown:

year                                  1997                                        1998                             1999
                             units                  Keur             units                      Keur     units          Keur
Digital piano                        4000             3000                      5500              3500           6000          3350
ACC Keyboard                        10800             3900                 13200                  4000       11500             3650
Total                               14800             6900                 18700                  7500       17500             7000

5.   Product or process to be improved and the reasons to innovate

KORG Italy currently produces digital pianos and ACC keyboards.

The object of Application Experiment is the ACC keyboard. An improvement of digital piano is foreseen for
the next years but is not yet scheduled.
On these products a mainboard is used whose block diagram is shown in figure 1.

                                      Keyboard                 Panel
                                      controller              controller

      LCD                                   Microcontroller
    controller                                                                          DSP                 DAC
                                             (NEC V55)

                                           Memory controller

                          Rom                      DRam                    SRam

           Figure 1

The Keyboard Controller is an industry standard device:
•    Toshiba TMP87C847U

The Panel Controller is an industry standard device:
•    Fujitsu MB89635RP

The LCD Controller, built-in on the LCD module and already wired-up, is an industry standard device:
•    DM2023-7BL3 W/Harnesses

The Floppy Disk Controller is an industry standard device:
•    WD37C65C

The Memory Controller and the DSP are custom components, NOT developed by KORG Italy.
The µC is a standard microcontroller, provided with DMAC, I/O ports, etc.

The mainboard of a typical electronic musical instrument is made of two main functional blocks. The first
block includes a sound generation chip together with a ROM in which PCM samples are stored, to be used in
sound synthesis. The second block is composed of a microprocessor (CPU), storage memory and a set of
I/O peripherals.

         Figure 2:

The musician operates on a music keyboard, through which an electronic representation of a musical
message is transferred to the internal sound generation devices. Besides the keyboard, a set of pushbuttons
and a display device are available to the musician. Using them, he can configure the instrument, modifying
some global parameters that change the way the instrument works, or he can vary some particular
parameters of internal resources that act, as an example, on the characteristics of the musical sound to be
The display device of old product is an alphanumerical LCD having two rows of twenty characters (2x20) and
a built-in controller.
The need for a bigger display with superior graphical capability, means that some related devices like the
microcontroller and the dedicated memory had to be improved since they are not powerful enough for the
aimed functionality improvements. The main reason to innovate was to reach new market opportunities,
reducing time to market of “new” products, in order to quickly answer to new customers requests. This can
be achieved through the design of a new mainboard that can be dedicated to several different products only
with minor changes. This new board should be provided with new functionalities maintaining a production
cost close to the actual.

Improvements of the product have to be:
-   a bigger display with superior graphical capability
-   hard disk recording capability

-    support for a range of storage devices (hard disks, CD-rom, Flash disk,….).
-    Additional midi support capability (for future expansion).
The feasibility study made before the Experiment indicated that the Gate Array ASIC solution instead of the
assembly board would have allowed the company to save about 35 euro per board. This means a very big
cost saving since the number of keyboards foreseen for sales are more then 30K. This cost reduction is
mainly due (with a percentage close to 70%) to the replacement of the programmable logic (necessary to
interface different commercial components), with the gate array ASIC. More cost reduction is resulting from
the PCB reduction and the assembly optimisation.

6.   Description of the product or process improvements

The main target pursued by KORG Italy for future products is a high degree of competitiveness. This
competitiveness can be guaranteed only if the product finds the market backing, in terms of performances
and features.
The mainboard that was used in the first new product (whose production will start in Q2 2000 and will be
called iS400), implements the following added functionalities:

•    Interrupt Controller. By integrating an interrupt controller we can manage up to eight additional
     interrupting peripherals to microcontroller.

•    Sampling. Samples received from an external A/D converter can be used as PCM samples for sound
•    Stereo Hard Disk Recording and Playback. Samples received by an external A/D converter or from a
     sound generation chip or from an effect DSP will be stored in the microcontroller DRAM memory
     (Record) using a DMA channel of the microprocessor. Recorded samples can be used in Playback as
     PCM source for sound generation chip.
•    Serial communication interface to a masked device (an external ROM masked controller), supervising
     the panel and music keyboard I/O
•    Serial communication interface to a device used to display text on an external monitor or TV color
•     ATA interface.

Therefore the improvements of the new system are:

•    Integrating the LCD Controller we can use a Custom Graphical LCD Display 40 x 128 pixels

•    Midi: We can have an additional MIDI controller for future system enhancement trough addition of
     peripherals that require an asynchronous controller.

•    Storage device: we can interface a Flash disk (on board), an external Hard Disk or other storage devices
     (like CD-Rom).

Given these requirements, the Gate Array ASIC included the following peripheral devices:
•    Serial communication interface to Keyboard/Panel controller
•    Interrupt Controller

•    1 x UART,
•    Digital sampling and Hard-Disk recording logic
•    ATA BUS interface
•    CPU and LCD controller interface logic

The gate array has the following feature: 18814 gates; 100 pins, 0.5 ?m CMOS sea of gates 2-metal
process used, QFP package, chip size: 4.49 mm sq.
The block diagram and the picture of the main board of the innovated instruments are shown in figure
respectively in figure 3 and 4.

      IcBus(1)                            d
      IcBus(2)                                      controller

    Digital Audio
     Controller                                                                     DSP        DAC


                                           (MOTOROLA)                               Rom
        LCD                                                                         Samples)

Gate Array

                       Flash rom                    DRam                      Rom

Figure 3
-The new board is shown in figure 4.

        Figure 4

7.   Choices and rationale for the technologies, tools and methodologies

As the market imposes that the specifications, given by the product managers, are continually revised, it is
mandatory to use a range of technologies that allow flexible and modular design strategies.
The solutions considered for improving the product are FPGA technology, a Gate Array ASIC and a mixed
signal ASIC.
The FPGA technology was evaluated because it is an intermediate step for testing the ASIC design. As the
costs have to be decreased, this solution is not applicable because the number of pieces to be produced is
high (more than 30K) and the costs of FPGA components are not acceptable. Actual VHDL (implemented in
the final Gate Array) fits in a 20K antifuse FPGA, with 2Kbit of embedded RAM. This component (for our
production quantity) costs more than 60US$ ( Actel A32100dx).
A mixed signal ASIC solution did not justify the NRE cost increase (more than 200%) with the cost reduction
due to the integration of the DAC on the CHIP.
The gate array ASIC solution (a 20K Gate Array is the final implementation) had the best cost/performance
ratio, a reduced NRE cost (close to 20KEuro) with a production cost under 3US$/piece. The NRE due to the
foundry was 15 Keur or production of 30000 pieces per year.
Therefore the project consisted in the design of a digital ASIC. In the hardware design field, since the new
mainboards are provided with a set of specialised peripherals, it has been decided to design such parts and
to fit them in a digital ASIC. The system was integrated in a GATE ARRAY, using the VHDL methodology
that allowed, as an intermediate step, to make an FPGA, thus reducing the risks related to the development
of an ASIC device and finally saving the costs for the single chip.

The selection criteria for the VHDL design methodology adoption, especially related to the ASIC project,
were the following:
1. Technology independence. This means that having a project or a function described using VHDL, it is
    possible to switch among different makers and different technologies (i.e., from FPGA to Gate Array) by
    simply changing the target during the synthesis phase (which is automatic) of the project.
2. Very easy system simulation (functional simulation), meaning that a great amount of time is saved.
3. Flexibility. Once the system has been defined - and several different solutions have been evaluated by
    simulating the whole system - and the code has been translated in synthetizable code, the making of the
    device is left to the synthesiser. This translates the code in logic gates that physically implement the
    functions. This represents an immense advantage in terms of development time, since any change in the
    project leads only to the modification of the code that has to be recompiled. This obviously allows a strong
    reduction in time to market.
4. Ease re-use of “modules” that can be grouped in libraries. Library items can be subsequently customised
    in order to implement features of specific products.
All these advantages decrease dramatically the time to market and the human resources exploitation, thus
increasing the company’s competitiveness.

This ASIC integrated all the peripheral devices reasonably needed on a mainboard to upgrade a
family of future products. The peripherals were described in VHDL.

The VHDL methodology has been chosen to make the project. Specifically, VHDL has been used for the
functional description of the system. A VHDL simulator was then used to check the system at the behavioral
level. Next, the description of the system was translated to RTL level and the logic synthesis was used to get
a gate level description of the final device.
The target device is an ASIC (digital CMOS GATE ARRAY) that integrates all those peripherals we consider
a must for future products. By using the VHDL and logic synthesis, we were allowed to reach our goal
passing through an intermediate phase. In fact, an FPGA was made in order to check that the system works,
minimizing all project risks. Re-targeting the design during the logic synthesis completed the final GATE
The making of an intermediate FPGA device not only reduced the risks related to the production of
an ASIC, but it shortened the development time - allowing the software design to start several
months in advance.

Here follow the reasons for which we chose VHDL methodology and ASIC technology:
•   Time to market: the VHDL methodology granted us a better time to market, that is a crucial target in
    order to maintain competitiveness in our market segment.
•   Lower cost: the second fundamental target, in order to be competitive, is to keep costs as low as

Since in an ASIC development all the peripherals were designed ‘ad hoc’, they will include only what is
strictly necessary. Taking into account the development costs and the risks, those devices will surely be less
expensive than those provided by third parties as standard components.
Alternate solution evaluated:
Given the requirements of the project, a possible solution was that of using an FPGA. However, this solution
is absolutely not cost effective, related to the production volumes (30K pcs/year).

Fabrication methodologies
Once chosen the technology (DIGITAL CMOS GATE ARRAY) the services of EUROPRACTICE have been
evaluated. Particularly we found the Multiple Wafer Project very effective for prototyping, but we decided not
to use it for the following reasons:

1. Our target is production. Having realized the prototypes with a MPW run, we think it would be absolutely
    prohibitive to manage the schedule of our production needs with the projects included in the same wafer.
    A complete new mask set would have to be developed making this solution not effective from to points of
•   Time to production
•   Cost of new mask set
2. None of the foundries involved in EUROPRACTICE services have design centers in Italy. This would
    have implied more difficult and risky project management and more expensive communication costs.

Testing methodologies
Korg Italy has developed test programs to be used at foundry site to test the ASIC. A functional logic test has
performed at KORG Italy site in order to verify the functions implemented in the ASIC.

Hardware and software
KORG Italy during the AE has developed a complete innovative ASIC design flow under the Windows
NT Platform.
While PC Platform has been, historically, the platform used for FPGA development, Workstation has been
the ‘natural’ environment for ASIC development.
The use of PC Platform for ASIC development can be very effective for SME for the following reasons
•   Expertise: lower added expertise is needed in maintenance and use of PC compared to workstation.
    This lowers the barriers perceived by an SME when affording an ASIC development
•   Cost of hardware: PC hardware cost and maintenance is cheaper than Workstations hardware (cost
    saving more than 60%).
•   Cost of software development tools and maintenance: the same software development tool cost at least
    50% (!!) less on PC platform
•   ASIC design. Benchmarks show that a Pentium based PC running Windows NT operating system has
    performances comparable to those of a workstation. This makes this platform very attractive for ASIC

     CAE tools developers (many of them have already announced a PC version of their ASIC development
     Tools). Moreover by the same platform not only ASIC design can be implemented but also FPGA design.

For ASIC development software we decided to use MENTOR for the following reasons:
•    User friendly environment
•    Good synthesizer tool (EXEMPLAR LOGIC is one of the first company having concentrated their efforts
     on development of synthesis tool under PC platform). The same synthesis tool can target VHDL code on
     both FPGA or ASIC
•    Optimum VHDL simulator (possibility of mixed Verilog-VHDL simulations,VITAL COMPLIANT)
•    Availability of all major’s FPGA vendor’s design kit (and the larger, in comparison to competitors tools, for
     ASIC development)
•    COST

In addition in order to have a full ASIC prelayout development flow on PC, a new tool was introduced
in Europe from Japan. This tool runs under Windows NT and enables the user the following important tasks
in ASIC development:
•    Design Rule Check
•    Prelayout Delay Calculation
•    Netlist format conversion
•    Test Data Creation
•    Floorplan
•    Power Extimation

8.   Expertise and experience in microelectronics of the company and the staff allocated to the


The company carries out the design activity in the following field:
•    Software design
•    Hardware design: mixed Analogue/Digital PCBs;
•    Mechanical design

Totally 16 persons are involved in this activity. The personnel participating in the AE had expertise in PCB
design, microcontroller technology and DSP system development.
Concerning Hardware design, the expertise prior to AE are related to mixed Analogue/Digital PCBs; the
sound synthesis is obtained by means of specific analogue and digital PCBs : a key and panel scan PCB,
which produces codes to be interpreted by a CPU PCB where sound is synthesised by a DSP controlled by
a microprocessor. At the end of the process the elaborated digital codes are converted to analogue signal
that are amplified by a power amplify PCB.
In the Software design field, the sound synthesis process is a highly complex activity managed by a powerful
microcontroller. State of art software development methodologies are implemented in KORG Italy in order to
produce the necessary software code to make the microprocessor and the whole system work.

Three people having expertise on analog and digital PCB design have been involved on the Application
Experiment activities. They are electronical engineers with capabilities to develop microcontroller and DSP
system. Now these technicians of Korg Italy are able to manage the ASIC technology without external
9.   Workplan and rationale

The original project duration was 13 months, but during the Experiment development two extensions needed
to be requested, so the total duration was of 21 months.
The rationale of the workplan design was to get in-house know-how in ASIC design.
The workplan is divided into 5 workpackages:
•    Workpackage 1: Management
•    Workpackage 2: Training
•    Workpackage 3: Design
•    Workpackage 4: Fabrication
•    Workpackage 5: Test
It has to be noticed that an intermediate step (the implementation of an FPGA) has been realised in order to
test the ASIC functionalities before proceeding to the prototyping, in this way the risk of having to realise a
second run is reduced.
The technology transfer process was carried on with a preliminary theoretical course on the VHDL language
and logic synthesis on FPGA and ASIC and with a continuous and effective training on the job during the
design phase.

9.Workplan and rationale

The original project duration was 13 months, but during the Experiment development two extensions needed
to be requested, so the total duration was of 21 months.
The rationale of the workplan design was to get in-house know-how in ASIC design.
The workplan is divided into 5 workpackages:
? Workpackage 1: Management
? Workpackage 2: Training
? Workpackage 3: Design
? Workpackage 4: Fabrication
? Workpackage 5: Test
It has to be noticed that an intermediate step (the implementation of an FPGA) has been realised in order to
test the ASIC functionalities before proceeding to the prototyping, in this way the risk of having to realise a
second run is reduced.
The technology transfer process was carried on with a preliminary theoretical course on the VHDL language
and logic synthesis on FPGA and ASIC and with a continuous and effective training on the job during the
design phase.

Workpackage 1: Management

Task 1.1 Project Management
Description: Plan activities and resources for AE; establish and manage the interaction to subcontractors for
ASIC design (design flow), facing up question arisen, co-ordinating different activities like:
Planning & Schedule - Evaluation of tasks, timing for the AE and attribution of resources and
responsibilities for the tasks to be carried out. Assessment of correspondence between planning and results;
Budget - planning and monitoring costs for the AE. Evaluation of tasks cost
Duration all over the project
Roles & Responsibilities: This task has been accomplished by FU effort only.
Task 1.2 Reporting
Description production of report material on design status. Monthly reporting on review meeting with
subcontractors and monitoring of on going work
Duration all over the project
Roles & Responsibilities: This task has been accomplished by FU effort only.
Task 1.3 Dissemination
Description In order to create information material on the AE, the FU established contacts with the University
of Ancona Engineering department and informed the students about the AE; created a brochure on KORG
Italy AE for spreading among KORG Italy’ s suppliers and contacts.
Duration 2 months
Roles & Responsibilities: This task has been accomplished by FU effort only.

Workpackage 2: Training

Rationale: The training activities were carried out by FU and subcontractor. The FU attended the theoretical
course learning both the VHDL language and tools utilisation. The subcontractors supported FU for the
theoretical course and for the training on the job.
Objective: To get the Know How on the following items:
•   VHDL Language (syntax and structure)
•   Logic Synthesis (subset RTL of VHDL)
•   Advanced Logic synthesis for FPGA and ASIC design
•   TOOLS: Synthesis Tools, VHDL Simulator
Description for the Training we referred to subcontractor1, Innovative Design s.r.l. And we proceeded in the
following way:
Theoretical courses followed by on job training in order to apply the learned concepts in the design that is the
object of Application Experiment. The target of task is:
•   Rapid evaluation of different possible solutions for the implementation of a system described in VHDL,
through behavioural simulations and ability to produce a synthesizeble VHDL code
•   Optimisation of the produced VHDL in relation to the chosen technology (FPGA, ASIC)
•   To be able to control the synthesis process and be able to do a technology retargeting of the VHDL code,
in order to migrate from one technology to the other (i.e. FPGA à ASIC
Duration 6 months

Task 2.1 VHDL Language Training
Description Get knowledge of the VHDL language syntax and semantics. Self-training on MASTERCLASS (a
Windows based multimedia tutorial on VHDL language and its application to design of a system) followed by
exploration of VHDL structures using the VHDL simulator
Duration 1 month
Roles & Responsibilities F.U
Task 2.2 VHDL RTL (Logic Synthesis) Training
Description Produce a synthesizable VHDL code for system description (VHDL RTL code)
On job training on VHDL RTL methodology and introduction on synthesis environment
Duration 1 month
Roles & Responsibilities Subcontractor1: organised the course and F.U. attended it.

Task 2.3 VHDL RTL (Advanced Logic Synthesis for FPGA and ASIC) Training
Description Logic Synthesis for FPGA - Apply VHDL RTL methodology to a real FPGA design. Theoretical
course and On Job training on a real FPGA design Logic Synthesis for ASIC - Synthesis re-targeting of
VHDL model from FPGA to ASIC. Methods of generating test vectors for ASIC test in VHDL Theoretical
course and On Job training on methodology of re-targeting from FPGA to ASIC and on the methodology to
generate the test vectors

Duration 3 month
Roles & Responsibilities: Subcontractor1 organised the course and F.U. attended it.
Task 2.4: Training on FPGA development system
Description To get knowledge of the development system to be used to implement the design on FPGA. To
be able to place & route a design, fitting it on a vendor specific FPGA device. On Job training, trying the
entire design route on a small part of a design.
Duration 2 months
Roles & Responsibilities Subcontractor1: organised the course and FU attended it.

Workpackage 3: Design

Rationale this workpackage enabled us to describe, a complete system in VHDL. Knowledge of FPGA
development systems and of methodology to implement an ASIC starting from FPGA design (synthesis
retargeting of VHDL code). In this task the subcontractors help was fundamental. They collaborated with FU
for conceiving all the design phases from the specification to ASIC development. The system was described
in VHDL and, as intermediate step, was targeted to FPGA. The implementation of the FPGA enabled the
verification that the system works and at the same time enables the start of software development thus
reducing the RISK of ASIC development and gaining men-months for software development. Since the
system is produced in volumes, starting from the results obtained from FPGA design, the VHDL code was re-
targeted to an ASIC implementation (CMOS GATE ARRAY)
Task 3.1: Specifications
Description Definition of product functional specification. System functional sub-units definition. Interaction
between these subunits signals and between the system to be integrated and the outer world. Through
inputs coming from marketing department and feasibility study for the system, specification were laid out
Starting from the functional specification technical specification will be developed (i.e. clock speed, package,
pad’s drive strength etc.)
Duration 1 month
Task 3.2: VHDL System Design & Simulation
Description Implementation, starting from specifications, the VHDL code which defines the system object of
AE, divided on different block: UART + Interrupt Controller Design, LCD Controller Design, Serial
Synchronous Interface + Digital Audio controller Design. The system’s functional blocks were described in
VHDL and different alternatives (for system implementation) were explored through system simulations
(behavioural simulations)
Duration 3 months
Task 3.3: System synthesis & logic verification
Description the VHDL code was analysed and modified in order to use only synthesizeble structures. The
results of synthesis was verified (static timing analysis) and compared to logic simulation results
Duration 1 month
Roles & Responsibilities: Subcontractor1 supplied On job training and consultancy to the F.U.
Task 3.4: FPGA System implementation

Description FPGA development system was used to place and route the netlist obtained from logic
synthesis, (FPGA floorplanning, layout). Backannotation signal timing delay files for timing simulations were
produced. Brief timing simulations were executed before FPGA programming
Duration 1 month
Roles & Responsibilities F.U.
Task 3.5: FPGA functional testing
Description the FPGA device was programmed. The PCB for FPGA was prepared and the system verified.
Duration 1 month
Roles & Responsibilities F.U.
Task 3.6: ASIC development
Description A synthesis retargeting, using the foundry libraries, of the system’s VHDL description was made
in order to implement a CMOS GATE ARRAY. The test program(s) are developed. The Netlist was given to
silicon foundry engineering for Layout and the backannotation files are used for timing simulations (best &
worst case timing analysis).
Duration 5 months
Roles & Responsibilities       FIRST USER and Subcontractor1 for On job training and consultancy.
Subcontractor 3 (FOUNDRY) for the placement & routing of the supplied netlist. Backannotation

Workpackage 4: Fabrication

The validation of postlayout simulations has been effected at subcontractor 3 premises.

Task 4.1: Design Validation
Description Validation of simulation for prototype and prototype implementation in order to get sign off for
prototype production
Duration 2 months
Roles & Responsibilities FIRST USER and Subcontractor3: Foundry
Task 4.2: Prototype Production
Description Production of prototypes of Gate Array (10 Engineering sample)
Duration 2 months (post AE)
Roles & Responsibilities Subcontractor3 for the prototype realisation and test

Workpackage 5: Test

Rationale: Functional testing of prototype; Prototypes were mounted on PCB board and functionality verified
Duration 1 month (post AE)
Roles & Responsibilities FIRST USER
Two extensions have been required ad approved by EC. In the first case an extension of 4 months needed
for upgrading the specification defined at the start of the project, thanks to experience gained during the first
part of the experiment. The selection of foundry took on some time, but this collaboration with the Fujitsu
allowed FU to develop ASIC on PC environment. The Japanese foundry helped FU to define these new

specifications. The selection of foundry and the new re-definition has determined an increase of the training
The second extension has been required and approved on March for others 4 months fixing the AE end date
on 31st of August 1999. The reasons for a new extension request were related to a problem detected on a
microcontroller used on the board. The FU purchased this microcontroller that should have been used on the
board containing the ASIC. As a result of the intermediate FPGA TEST (used for prototyping the ASIC) the
F.U. learned that there was a BUG in the DMA section of COLDFIRE 5307.This BUG did not make possible
to use the two external DMA channels at the same time in cycle steal mode.
Investigating further they discovered that the acknowledge function as described in COLDFIRE MANUAL
would had to be implemented only in the new mask to be released April/may 1999. Then this fact delayed
the FPGA/ASIC development.
As mentioned on the workpackage description, the subcontractors charged of training are Innovative Design
s.r.l. while ACTEL was the supplier of FPGA components providing the support for FPGA development
The foundry Fujitsu, whose costs have not been charged on the FUSE Application Experiment but on the
company resources, supported the company during the ASIC design.           It provided the direct support for
Library on Windows NT and for tools utilisation. The foundry costs were as planned and not difficulties arose.
The relation between company and foundry were very good because this Experiment was very important
also for Fujitsu, since it was the first ASIC development on a PC environment at a European level.
Task 4.2 (Prototype production) and WP 5(Test) were accomplished respectively on September and October
since a new problem arose due to FPGA malfunctions and some modification had to be implemented on this
device. This further component redefinition postponed the delivering of the prototypes by the foundry.
Therefore the actual delivering occurred in September and the actual testing was accomplished in October.
However this further delay the ASIC has been implemented and Application Experiment has ended

                                     Total cost (Keur)
                                     planned               actual
Workpackage1: Managing                             4.167                 4167
Workpackage2: Training                            22.969                18000
Workpackage3: Design                              58.536                86693
Workpackage4: Fabrication                         21.308                 6071
Workpackage5: Test                                 3.021              1640(*)

Total project costs                                                   129.931
Total funding by CE                              110.000              114.931
(*) not funding by CE

                                  FIRST USER                         SUBCONTRACTOR
                                  Labour (Person-days)               Labour-cost (Keur)
                                  planned           actual           Planned       actual
Workpackage1: Managing                        25               25              0                  0
Workpackage2: Training                        45               23         15.782             15.782
Workpackage3: Design                         224              322          4.427                  0
Workpackage4: Fabrication                       5              30         20.526            15000(*)
Workpackage 5:Test                            20             22(*)             0                  0
Total project costs                          319         422(*)           40.735              30782
Total funding by CE                          319              400         40.735             15.782
(*) not funding by CE

The time schedule on the following page shows the different activities charged on AE FUSE funding

                             Original duration                                            1st extension        2nd extension
months                       1    2     3     4   5   6   7   8   9   10   11   12   13   14 15 16        17   18 19 20        21
Task     1.1     Project
Task 1.2 Reporting

Task 1.3 Dissemination

Task    2.1       VHDL
Language training
Task 2.2 VHDL RTL
Logic synthesis
Task 2.3 VHDL RTL
Advanc.logic Synth.
Task 2.4 Training on
FPGA dev.syst.
Task 3.1 Specification

Task        3.2     VHDL
Task 3.3 Synthesis &
logic verification
Task        3.4     PFGA
Task3.5 FPGA funct.
Task        3.6      ASIC
Task       4.1     Design
Task     4.2     Prototype

A risk analysis was realised before the Application Experiment start. This analysis underlined the following
q   It was not possible to outline in advance the design flow since the technology was implemented for the
    first time and therefore there was no prior knowledge of its specifications.
q   At the start of the project the necessary strong support by the foundry wasn't assured, but the high
    volumes of products units made our project proposal attractive for them.
These problems were prevented thanks mainly to the FPGA intermediate testing step and to the positive co-
operation with the foundry, but unforeseen problems arose during the project development.
Maybe the waste of time could have been avoided with an attentive foundry selection, but the opportunity to
develop ASIC design on PC environment was available only after the project start. Therefore the company
preferred to take on more time to evaluate this possibility instead of carrying on the typical solution by
workstation acquisition.
The unforeseen problem due to microcontroller bug caused a further waste of time but this fact was
completely unexpected by company that for the first time designed an ASIC.
However the Experiment duration scheduled at the start of the project was too short for an ASIC design
faced up for the first time.

10. Subcontractor information

Korg Italy needed a Subcontractor able to provide a good training in VHDL and ASIC synthesis and a
foundry able to carry out an ASIC development with design support.

The Korg Italy found help for training in microelectronics design particularly in VHDL language for FPGA and
ASIC design. They chose two different subcontractors for accomplishing this task.
The first is Innovative Designs S.r.l. This is a small enterprise with 6 employees that has a deep experience
on large commercial FPGA and ASIC design, using VHDL methodologies. They are expert on tools we used.
The selection criteria for choice were due to high level professional profile, VHDL expert, Deep experience
on large commercial FPGA and ASIC design, using VHDL methodologies.
Their main activity is microelectronics consulting.
In the developing phase of the ASIC, the company scheduled to implement an FPGA that should have to
simulate the behaviour of the circuit. For this reason it had to address to FPGA manufacturer and ACTEL
was selected. The selection criteria of this choice is due to the fact this supplier is leader in Antifuse FPGA
technology, the FPGA internal structure was very similar to Gate Array, and that it is available to support
Korg Italy by on job training during the FPGA implementation by development tools. Moreover the low cost of
development system determined the ACTEL choice.

The foundry has been chosen after the start of the project and company after deemed study to ask support
in the its first experience with ASIC from Fujitsu foundry. The first foundry selected was ES2, located in
France (Europe) with competitive prices, but as this foundry has been acquired by Atmel, Korg Italy decided

to follow another company. The selected foundry was Fujitsu. It added to competitive prices also an ASIC
development system on PC environment and this fact get added value to the Experiment.
As the company decided to follow this approach after business plan presentation, then it has been necessary
to extend the training phase, but this fact has increased the added value of the A.E. as one of the first
European ASIC realised with PC based development tool.
A standard contract was agreed with the Subcontractors with no specific discussion agreements were due to
their proved high reliability and their interest in our future production.
However Korg Italy found in this foundry a reliable partner, most of all because of the foundry own interest in
this project. The foundry as well was experimenting for the first time the ASIC design on PC environment,
which is an innovation at a European level. This proved to be a more than reliable guarantee, and the
foundry heavily supported the company because a good result for Korg Italy would have been also a good
result for the foundry.

11. Barriers

The main barriers perceived by KORG Italy are different depending on Experiment complexity:
•   Knowledge barriers:
The company understood that the technology applied to motherboard of its musical instruments could be
upgraded utilising ASIC technology but it found more difficult to select the right ASIC specifications.
The VHDL potentiality and the effort to be done to learn this language at high level were not easy to
•   Management barriers
Another problem arose in the quantification of perceived risks not only from economical point of view, but
also from management point of view. Korg did be able to evaluate how many efforts to be dedicated to
Application Experiment and also if this project realisation should have took off effort from other activities.
Moreover the company was afraid of possible lack of support from foundry because it happens this kind of
relation can become difficult.
•   Financial barriers
The tools cost were elevated whether for the ASIC development SW and also for efforts allocated on.
The main perceived financial risk on ASIC development was high because redesign and related delayed
time to market for the innovated product could be occur.

12. Steps taken to overcome barriers

The barriers have been overcome thanks to subcontractors and TTN help.
•   Knowledge barriers:
The knowledge barriers have been faced up with TTN help that defined with the company the suitable ASIC
•   Management barriers

The TTN and the subcontractor described the benefits that company would have acquired and delivered on
other products and that the difficulties encountered could be overcome.
The relation with foundry has been quite good and get complex only when a problem arose on
microcontroller mask.
•   Financial barriers
ASIC development risks was highly reduced by development of an intermediate FPGA that not only gave us
the chance to check in advance the functions that would be implemented in the ASIC, but also it allowed the
start of software development thus shortening the time to market for the product.

13. Knowledge and experience acquired

KORG Italy wanted to acquire design capabilities learning VHDL methodology, FPGA design through VHDL
RTL description and logic synthesis, ASIC design through synthesis retargeting of VHDL code used to
implement the FPGA.
Then the goals prefixed were increased capabilities on FPGA/ASIC design through VHDL methodology,
management of new FPGA/ASIC design tools in PC environment, have been reached.
Another strategic goal of KORG Italy was to achieve from AE a know-how in project management (business
plan and work plan compiling, management of contacts with foundries, subcontractors, suppliers, etc.).
These goals were achieved trough a training course dealing both with theoretical course and with a training
on the job.
It was structured as follows:

•   VHDL Language Training
•   VHDL RTL (Logic Synthesis) Training
•   VHDL RTL (Advanced Logic Synthesis for FPGA and ASIC) Training
•   Logic Synthesis for FPGA
•   Logic Synthesis for ASIC
•   Training on FPGA development system

Moreover the new technology allowed company to introduce added features on product and to decrease
time to market and through ASIC development also these targets were achieved.
In the future, this experience will allow KORG Italy to develop ASIC in autonomous way (without the
assistance on an external expert). The know how acquired by the AE will enable KORG Italy to develop
more complex ASIC (a second step in this direction, for example, could be the integration, in the ASIC, of the
microprocessor core itself) with lower risks.

14. Lessons learned

The main lesson learned during this AE is the importance to schedule all activities in a suitable way
(especially when an ASIC has to be implemented for the first time). This task has not been accomplished
and two extensions had to be required.
Even if the microcontroller problem was not our fault, it should have been our duty to foresee time to recover
delay coming from any possible difficulties arisen.
In the ASIC development the main step to decrease the risks is the intermediate implementation of FPGA
device for simulating all the ASIC functions. This phase has been very important to avoid a further delay in
the project timing. In fact several FPGA design have been realised in order to solve the problems coming
from the testing phase. Only when the test was successfully the ASIC was prototyped.
Another fundamental lesson learned on the ASIC design is related to the interface between the ASIC device
and the others components laid on the board. This interface has to be designed autonomously from the other
components in order to be free to change them (for example the microcontroller) without having to re-do the
whole design.
During the design realisation some difficulties had to be faced especially due to the design flow
implementation on a PC environment as test pattern generation and the clock tree generation.
The implementation on PC environment helped the company in the ASIC development because it produced
many benefits as mentioned above but brought some drawbacks related to this phase. As this is the first
experiment also for the foundry in Europe some difficulties had to be overcome during the prelayout checks
and test pattern. More support was needed in this step. Moreover the unexplored design flow determined
some little delay in the first phase of the application Experiment. This problem can be prevented with a more
suitable time schedule and a feasibility study carried out together with foundry.
The specification defined at the project beginning had to be reviewed and upgraded. This could be
previewed with a deeper feasibility study. An initial definition of the ASIC development environment (PCB
instead of a workstation) would have avoided a delay caused by the choice of the foundry to support the
necessary libraries. In fact also the foundry selection it’s an important issue not to be underestimated when
implementing such a risky innovation.

15. Resulting product or process, industrialisation and internal replication

The prototype was aimed to innovate an ACC keyboard that will be produced ion the second quarter of 2000.
Therefore the first prototype working correctly and the Experiment was successful.
The new functionalities related to Audio side that are the more innovative part of prototype were tested. The
HD recording working right as the sample function.
The new design methodology using VHDL approach is utilised by company for others products. This was a
main target of the AE then the internal replication will be carried out on other products. The first internal
replication foresees the introduction of ASIC technology (by VHDL logic synthesis) also in the Digital Pianos,
one of the main product of Korg Italy, then the board inside will be redesigned by this technology.

The industrialisation of ACC Keyboard, implementing new features thanks to ASIC development is foreseen
for May. 2000.

Prototype 1 - October 1999
Features – Hand made (numeric control) Case.

Prototype 2 - February 2000
Features – Final Case from moulding. Final Boards. Basically the instrument is the same as Production

Preproduction - April 2000
From Prototype 2 to Preproduction only production improvements will be made for cost optimisation and for
Test compliance (EMI etc.)

Production – May 2000

After the release of ACC Keyboard, others products related to this one will be delivered (they are
summarised in order of production):

    •   ACC Keyboard, implement new features thanks to ASIC development
    •   ACC Desktop Module, PCB-size reduction thanks to ASIC development- Oct. 2000
    •   ACC Keyboard, implement new Audio features thanks to ASIC development - Mar. 2001
    •   ACC Stage Keyboard, cost reduction thanks to ASIC development - Sep. 2001 -
    •   Innovative Stage Module, implement new Audio and User interface features thanks to ASIC
        development - Nov. 2001
    The whole industrialisation costs is: 781 KEUR -
    These costs include:
    •   Hand made housing case prototype realisation 40 Keur
    •   Realisation of the keyboard housing case moulds 135 keur
    •   Mechanical engineering 36 Keur
    •   Software development 370 Keur
    •   Hardware redesign 200 Keur

16. Economic impact and improvement in competitive position

The target of this Experiment is to producing an ACC keyboard whose main board (the core of the entire
system) has been innovated through ASIC technology introduction.
As we achieved this objective, the further step concerns the innovation also of digital pianos as this product
is based on the same main board as the ACC keyboards.

Due to the current situation in the market the company decided to commercialise the new motherboard first
on ACC products and later on Digital Pianos. ACC product sales have a much bigger impact on the
company’s turnover than piano products.
The mother board improvement is a must for the company for achieving a high degree of competitiveness.
This competitiveness can be guaranteed only if the product finds the market backing, in terms of
performances and features.
As the market imposes that the specifications, given by the product managers, are continually revised, it is
mandatory to use a range of technologies (3D CAD mechanical modelling, object oriented methodologies for
software design, ASIC design through VHDL methodology) that allow flexible and modular design strategies,
so that time to market can be shortened and competitiveness enhanced.
The comparison between the expected sales with and without the new technology and methodology
introduction is indicated in the following diagram for the next three years.
This high sales increase is achieved thanks to several positive factors: well-known Brand name ( org is
known at a professional level, and this provides a good promotion at an amateurs level), similar price
(affordable and the customer recognises the high quality level of the product), added functionalities (key
factor in the increase of the added value).
These features are strongly demanded by the market, and the time span from between this product and the
old one is big enough to provide a very good answer from the customers.
It has to be added that Korg Italy will heavily invest on a promotional campaign.
The profitability improvement due to the AE innovation can be estimated in a percentage increment of about


                   30000                                                                         Sales without FUSE
                                                                               Sales with FUSE
                                                                                                 Sales with FUSE
             Keur 20000

                   10000                                            Sales without FUSE

                             2000       2001         2002
       Sales without FUSE    16000      16500        17000
       Sales with FUSE       22400      31600        34500


The forecasted sales are expected to have a significant increase because in spite of maintaining the same
price the new product has an high added value in terms of:
•   A decrease of the cost/performance ratio
•   A shorter time to market
•   A more flexible product
•   A bigger display
•   Hard disk recording of new sounds
•   Supporting Hard disk and other storage devices
•   Supporting Flash disk

This sales increase is even fostered in the first phase of the product’s life –launch- by the consumer’s
(amateurs) attitude, proved to be very attracted by the combination of well-known brand name, added and
innovating functionalities and affordable price. Moreover, it is typical of the keyboards market segment that
the launch of a new product with an high quality level gives a strong impulse to the sales.

First the new mother board architecture leads to a cost reduction and a performance improvement. New
functionality could be introduced and the motherboard size shrunk compared to equivalent motherboards
using a traditional approach. The display device of the old ACC keyboard has been replaced with a bigger
display with superior graphical capability without the need to add electronic components like memories and
specialised controllers.

The pricing is similar to current products but important features have been added in order to achieve a
significant better market position.
The price of the new ACC keyboard to the dealer is increased to 8% of the old ACC keyboard (iS35), then
this price is quite the same. However the improvement of Application Experiment is related especially to the
added feature instead to the cost reduction.

The time to market is decreased as more flexible design flow has been adopted.
The VHDL methodology utilisation permits to implement an FPGA, as an intermediate step, thus reducing
the risks related to the development of an ASIC device.
The ROI calculation derived from the ratio of increase of profitability versus total project cost. The margin
increase is calculated over 6 years (because the first year is really only 6 months).

                           Years         2003             2004           2005

                           sales         33700            32500          19180

The total cost of AE encloses the industrialisation costs that are very high for keyboards. In fact only the cost
of realisation case is about 135 Keuro. This ROI calculated over five years and on total cost of Experiment (

AE funding and industrialisation cost) is 322% and in spite of high industrialisation cost it is very good
because thanks to AE innovation the sales increasing is very considerable.
The ROI calculated on AE funding only (enclosed foundry cost) is 1089% but this value without
industrialisation cost is less significant.
The payback period is 18 month and it has been calculated again with industrialisation cost resulting from
sales of 2000 (only six months) and 2001.

17. Summary of best practice and target audience

This application Experiment is a good example for gate array ASIC technology introduction. The product
improved has been obtained.
The good collaboration with Fujitsu foundry increased the value of the A.E. as the first European ASIC
realised with PC based development tool. This collaboration ensured a full support of the foundry that used
this project as a pilot one.
This is a very important fact in the ASIC development for a small enterprise that often encounters many
difficulties on collaboration with foundries. It has to be underlined that the ASIC development on a PC
environment permits SME to implement this technology without having to buy specific workstations, and with
a more user friendly interface.
The FU had to face up the question about a bug detected on microcontroller that it used for test, then they
had to schedule again the testing phase.
Thus in this Experiment also a new time schedule had to be done and a re-organisation of human resource
allocated has been effected.
The gate array ASIC technology has been realised in order to improve the whole design methodology and to
acquire a more flexible design flow.
The best practice of this Application Experiment is the intermediate FPGA prototype realisation before gate
array production. The VHDL adoption as a top down, platform independent design route allowed
transposition from FPGA to gate array in order to solve the problems before ASIC implementation phase.
The several FPGA prototypes done before this step indicate as this has been the right one.

The Korg Italy experience can be replicated for companies that want to implement an ASIC, because they
can understand the benefits and the questions related.

The manufacturers belonging to musicals instruments sector (but also any company able to buy PC-based
design tools), can take out information about new approach with design methodology and how this
innovation can upgrade all production.


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