Interrupts of 8085 by kmanraj

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									Interrupts of 8085
                  Interrupt I/O
• Memory-mapped & Peripheral-mapped I/O
  – process of data transfer b/w 8085 & I/O devices
    initiated by processor
• Interrupt I/O
  – process of data transfer b/w 8085 & I/O devices
    initiated by an external device
  – allows an input/output device to inform the
    processor that it is ready for communication &
    requests attention.
             8085 Interrupts
8085 has five interrupt inputs
1. TRAP
2. RST7.5
3. RST 6.5
4. RST5.5
5. INTR
     U7


 1                      40
 2   X1          VCC    39
 3   X2         HOLD    38
 4   RST-OT     HLDA    37
 5   SOD        CLKO    36
 6   SID       RST-IN   35
 7   TRAP      READY    34
 8   RST 7.5     IO/M   33
 9   RST 6.5       S1   32
10   RST 5.5      RD    31
11   INTR         WR    30
12   INTA         ALE   29
13   AD0           S0   28
14   AD1          A15   27
15   AD2          A14   26
16   AD3          A13   25
17   AD4          A12   24
18   AD5          A11   23
19   AD6          A10   22
20   AD7           A9   21
     VSS           A8



Interrupt pins of 8085
   8085
          Types of Interrupts
• Interrupts of 8085 can be classified as
  – Maskable (RST 7.5, RST 6.5, RST 5.5, INTR)
  – Non-maskable (TRAP)
• An interrupt is a request for attention/service
• 8085 may choose to service/not-service a
  maskable interrupt
• 8085 cannot ignore a service request from a
  non-maskable interrupt
          Interrupt process
• 8085 is executing its main program
• an interrupt is generated by an external
  device
• 8085 pauses execution of main program
• 8085 calls the Interrupt service routine
• 8085 executes the Interrupt service routine
• 8085 returns to execution of main program
  (from where it was paused)
 Example: Blinking LED Display with
 Interrupt-based Display-Pattern change

      Interrupt I/O              Peripheral-mapped I/O



Interrupt Switch      RST 7.5



                          8085
      Input
                                          LED
     Switches
                                         Display



 (Display-Pattern)
 Interrupt Service Routine (ISR)
• It is a subroutine
• 8085 calls an ISR in response to an
  interrupt request by an external device
• ISRs must be located in memory at pre-
  determined addresses known as Interrupt
  Vectors
 Interrupt Vector Table of 8085
       Interrupt                Interrupt Vector
         TRAP                        0024H
        RST 7.5                      003CH
        RST 6.5                      0034H
        RST 5.5                      002CH


Please Note: INTR is a non-vectored interrupt
 Using Vectored Interrupts of 8085
• By default, all the vectored interrupts (except
  TRAP) of 8085 are disabled
• 8085 vectored interrupts are enabled with
  two instructions: EI and SIM
• EI (Enable Interrupt): 1-byte instruction that
  sets the Interrupt Enable flip-flop
  – It is internal to the processor & can be set or reset
    by using software instructions
    Using Vectored Interrupts
Step-1
• Set Interrupt Enable flip-flop by using EI
  instruction to enable the interrupt process
Step-2
• Use SIM (Set Interrupt Mask) instruction to
  set mask for RST 7.5, 6.5 and 5.5
  interrupts
             SIM Instruction
• It is a 1-byte instruction
• Reads Accumulator contents
• Enables/Disables interrupts accordingly
• Used for three different functions
  – Set mask for RST 7.5, 6.5, 5.5 interrupts
  – Additional control for RST 7.5
  – Implement serial I/O
Accumulator bit pattern for SIM
D7   D6   D5     D4     D3        D2     D1        D0
SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5

                                    0 = Available, 1 = Masked

                                 Mask Set Enable, 0 = bits 0-2 ignored
                                                    1 = mask is set
                             IF 1, RESET RST 7.5

               If 1, bit 7 is output to
               serial output data latch

      Serial Output Data,
      ignored if bit 6 = 0
      8085 Interrupt process for
         Vectored-Interrupts
1. Enables Interrupt process by writing the EI
   instruction in the main program
2. Set interrupt mask using SIM instruction
3. 8085 monitors the status of all interrupt
   lines during the execution of each
   instruction
     8085 Interrupt process for
     Vectored-Interrupts (Cont.)
4. When 8085 detects an interrupt signal from
    an external device
   • It completes execution of current
      instruction
   • Disables the Interrupt Enable flip-flop
5. Executes a CALL to Interrupt Vector
    location for that interrupt
   • Before the CALL is made, 8085 stores
      return address in main program on stack
    8085 Interrupt process for
    Vectored-Interrupts (Cont.)
6. 8085 executes the ISR written at the
    specified interrupt vector location
   • ISR should include the EI instruction to
      Enable Interrupt again
   • At the end of ISR, RET instruction
      transfers the program control back to the
      main program
       Interrupt Programming
Problem statement:
a. Write a program for blinking a LED display (port
   address 80H) with interrupt-based display
   pattern change.
b. Write a subroutine to generate a delay of 50ms
   with 1MHz clock to set the blink rate.
c. Write a Interrupt Service Routine for vectored
   interrupt RST6.5 to read the display pattern for
   blinking from an input port with address 8000H

								
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