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M bius Microsystems
A 9.2mW 528/66/50MHz Monolithic Clock
Synthesizer for Mobile µP Platforms
Custom Integrated Circuits Conference (CICC) 2005
Michael S. McCorquodale, Ph.D.
Mobius Microsystems, Inc.
Slide 1 of 21 Mobius Microsystems
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Outline
Introduction
Background
Clock synthesizer reference oscillator and architecture
Experimental results
Conclusions and future work
Slide 2 of 21 Mobius Microsystems
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Introduction
Slide 3 of 21 Mobius Microsystems
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Introduction
Much recent work exploring alternative technologies to
XTALs for clock generation and frequency synthesis
MEMS microresonators
FBAR
Insufficient exploration of all-Si CMOS approaches
Build on recent work in free-running and open-loop
compensation of LC oscillators as frequency references for
clock generation
Slide 4 of 21 Mobius Microsystems
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Introduction
Goals
Develop an accurate and stable clock synthesizer without an external
frequency reference (i.e. XTAL or ceramic resonator)
Develop a clock synthesizer with very low frequency scaling latency
Develop a clock synthesizer with very low start-up latency
Characterize performance over PVT
Demonstrate in a multi-chip module
Approach
Explore free-running RF LC oscillators as frequency references
Utilize a “top-down” synthesis architecture
Slide 5 of 21 Mobius Microsystems
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Background
Slide 6 of 21 Mobius Microsystems
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Architecture
Reference oscillator
Free-running high-Q LC oscillator at a high frequency
Simple frequency trimming interface
Open loop compensation to stabilize over PVT
Very low phase noise
Very low start-up latency
Clock synthesis
Divide down to target clock frequencies
Decrease phase noise by 20log10(N) for divide by N
Slide 7 of 21 Mobius Microsystems
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Background
Resonant frequency
1 CRL L
2
1 CRL
2
o 2
CR L 1
Ro RL RC
_
+
LC L
+
v -gm i
ic LC C
_ _+
Ro L C
Sources of frequency drift
Real losses: RL and RC
i(t) ic(t)
Frequency modulation from
harmonic content of driving
gm0
t t amplifier
Filter response of LC network
and amplifier output resistance
Slide 8 of 21 Mobius Microsystems
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Background
fo
fmax
No
oscillation
fmin
gmo gm
fo vs. gm relationship
gmo → minimum gm for start-up
fo → decreases as gm increases (harmonic content increases)
fmin → approached as harmonic content approaches square wave
Can utilize harmonic modulation to self-compensate drift
by modulating gm through bias current
Slide 9 of 21 Mobius Microsystems
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Clock Synthesizer Reference Oscillator
and Architecture
Slide 10 of 21 Mobius Microsystems
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Reference Oscillator
R
Complementary cross-coupled MRp
architecture with PMOS tail for 250 2.5m
low phase noise 0.5 0.5
Bias current, temperature
dependent and scaled by R
430 430
MRn
~10x in mirror 0.53 0.53
Resistor divider self-biases 6.1nH 50kW
+out out-
control voltage and reduces 300mA
vcal
VDD sensitivity 50kW
0.8-2.5pF 0.8-2.5pF
vcal trims frequency 3pF
Reset transistors disable
215 215
MRn R
0.53 0.53
oscillator
Slide 11 of 21 Mobius Microsystems
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Architecture
1.056GHz
528MHz
1
R BUF ÷2 ÷10 Out
50MHz
0
vcal S EN0
66MHz
÷8 Out
EN1
“Top-down” or divisive architecture reduces phase noise and
period jitter of reference oscillator by 20log10(N) and sqrt(N)
RF reference oscillator can be started with low latency
Any available frequency can be selected asynchronously: low
scaling latency
Slide 12 of 21 Mobius Microsystems
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Experimental Results
Slide 13 of 21 Mobius Microsystems
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Die Micrograph
Fabricated in IBM’s 0.18mm
7RF-CMOS process
Core macro size: <0.4mm2
Test macros populate periphery
Output drivers drive 10pF with
100ps rise/fall times at 20mArms
Wire-bonded and characterized
in 16-pin ceramic DIP
Au studs for flip-chip module
assembly
Slide 14 of 21 Mobius Microsystems
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Temperature and Microsystems
Voltage Drift
VDD±10%
1.5 0.8 25°C: ±0.17%
1 100°C: ±0.33%
0.75
vcal Required to keep fo Constant (V)
Normalized Frequency Drift, f/fo (%)
Temperature
0.5
0 – 70°C: ±0.75%
0.7
0 VDD = 1.98V
VDD = 1.80V
-40 – 100°C: ±1.5%
VDD = 1.62V
-0.5
0.65 PVT Total
-1 Best: <±1%
-1.5
0.6
Worst: ~±1.5%
Temp. compensation
-2 0.55
-40 -20 0 20 40
Temperature (C)
60 80 100
Under-compensated
1.6mV/°C, R2 = 0.9984
Slide 15 of 21 Mobius Microsystems
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Start-up Latency
Measured 3.2ms
start-up latency from
leakage only power
state
3.2ms
Latency originates
primarily from bias
start-up time
Bias circuitry can be
modified to reduce
latency to ~ns
Slide 16 of 21 Mobius Microsystems
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Period Jitter
Measured with
Agilent Infinium
4GSa/s scope
250k samples per
edge
66MHz clock
measurement shown
RMS jitter
determined by
removing trigger jitter
J 40.32 34.42 21 ps
rms
Slide 17 of 21 Mobius Microsystems
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Performance Microsystems
Summary
Parameter Measured Unit
Power supply voltage (nom./min.) 1.8/1.12 V
Power supply current (VDD = 1.8V/1.12V) 5.1/3.5 mA
Standby power supply current (VDD = 1.8V) 300 nA
Power dissipation (VDD = 1.8V) 9.2 mW
49.5 – 56.2
Output frequencies 61.9 – 70.2 MHz
495.2 – 561.6
Frequency calibration (tuning) range ±6.2 %
RMS period jitter (528/66/50 MHz output) 7.4/21/33 ps
Temperature frequency drift (-40 to 100°C) ±1.5 %
Power supply frequency drift (VDD ±10%) ±0.33 %
Total freq. accuracy (process, voltage, temp.) ±1.8 %
Start-up latency 3.2 ms
Slide 18 of 21 Mobius Microsystems
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Conclusions and Future Work
Slide 19 of 21 Mobius Microsystems
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Conclusions and Microsystems
Future Work
Demonstrated a self-referenced LC clock
synthesizer with no external reference
Low jitter and scaling/start-up latency
Low overall drift, though drift under-compensated
Temperature compensation correction linear
Alternative compensation techniques already in Si
Very high total accuracy over PVT to be reported soon
Potentially an all-Si approach to stable and accurate clock
synthesis
Never underestimate what can be done with CMOS alone
Slide 20 of 21 Mobius Microsystems
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Questions welcome
Slide 21 of 21 Mobius Microsystems
