Quantum Wires by 06L9X5

VIEWS: 5 PAGES: 37

									The Long and Short of
   Quantum Wires
    In a solid state device



       Scott Beamer
      GuanXiong Mao
      Youming Yang
                       The Basics
• Different from classical in many ways:
   – Consequences of no cloning theorem means no fan out and
     calls for point to point transport of data
   – Decoherence (collapse of qubit through interaction with
     surroundings) means that wire lengths play a crucial role
   – Long and short range transport go by different processes
• Similar to classical wires in many ways:
   – Still used in principle to transport data from one location to
     another
   – Still relies on classical control mechanisms
   – Most practical (as of currently) implementation still relies heavily
     on classical circuitry
            Ballistic Transport
 Sending                                   Collector
Mechanism   |ψ>


• Why not:
  – Decoherence of qubit state during transport
  – Inability to physically implement sending the
    qubit in many cases
    Short range (Kane) proposal
                               •   Electron-coupled Phosphorous
                                   ions embedded in silicon
                               •   Qubits interact with nearest
                                   neighbor, exchanging information
                                   one “cell” at a time
                               •   Classical controls (AC driven
A    S   S   A    S   S   A        electrodes) are placed above the
                                   Qubits
                               •   Latency of roughly 1μs:60nm
P+           P+           P+
                                    – 1μm of wire ~ 17μs
                               •   Fidelity ~ e-λt
                                    – λ = time per operation (swap)~10-6
                                    – t = number of swaps
                               •   Maximum (error limiting)
                                   theoretical wire length (Threshold
                                   Theorem) ~6μm
                                    – Practical wire length ~60nm
                                            Long Wires
Physical Schematic
                                                                           •Generally uses shifts to
  Control/data Qubit
                               Classical Data Path                         transport the EPR pairs
       |a>
                                                                           •But assuming prepipelined EPR
                                                                           pairs (aka constant stream of
                                                                           pairs regardless of whether wire
   Source                                                   Target         is being used or not), it can be
Teleportation               EPR                          Teleportation
    Unit         |b>       Source              |c>           Unit          simply treated as a system with
                                                                           entangled pairs available for
                                                                           processing
                                                             |a>
                                                                                ->Latency only depends on
 Circuit schematic                                                              time required to perform
                                                                                teleportation ~20μs
 |a>                   H

                                                                           •Decoherence ~ e-λx10
 |b>                                                                           •independent of number of
                                                                               swaps!
 |c>                                                 X      Z        |a>
           Teleportation Unit: A closer look
           •Key factor is the purification process, which creates an asymptotically
           perfect subset of EPR pairs from a set of degraded ones




                                                         Data Target


Incoming     Incoming   Incoming                         Near perfect
                                    Purification Block
EPR Pair     EPR Pair   EPR Pair                          EPR Pairs


                                                                           Coded
                                                                        Teleportation
                                        Entropy
                                       Exchange

                                     (Provides |0>’s)
                    Big Picture
• When to use which?
  – Long wires require ~order of magnitude more
    overhead
  – Bandwidth of long wires/short wires ~e-2λ/λ
  – Error correction for short wires (swapping) also
    makes them more competitive against long wires for
    short lengths
  – But long wires have better latency past a certain point
     • Longer processing time = more bandwidth dedicated to error
       correction
         Architecture Basics
• Datapath
  – Contains all the data and operators
  – Contains the qubits
• Control
  – Asserts appropriate control signals at correct
    times to make datapath do appropriate
    operations
  – Will be done classically for simplicity
        Example Architecture
• Implementing Swap Channel for Second Kane
  Architecture
  – Will examine two possible layouts
     • 1-D Configuration
     • 2-D Configuration
  – Both layouts:
     • Produce a full duplex wire (bidirectional)
     • Will have one-directional bandwidth (ignoring error) that is
       half the maximum swapping frequency
  – Will simplify signals to classical control gates to be
    square
     • Actual signals will be fine tuned for electrons and transistor
       characteristics
     1-D Configuration Layout
S4   S1    A1      S2        S3    A2      S4   S1



           e1                      
                                   e2

                        Si
          P+ Ion                  P+ Ion




                    Side View
     1-D Layout Swap Operations
S4        S1             A1    S2    S3     A2   S4          S1


                         e1                 
                                            e2
          e1                         
                                     e2
          e1                   
                               e2
          e1             




                                                      Time
                         e2
          e1             
                         e2
          e1                   
                               e2
          e1                         
                                     e2
                         e1                
                                           e2
                               e1                
                                                 e2
                                     e1          
                                                 e2
                                           e1    
                                                 e2
     = Hyperfine interaction               e1    
                                                 e2
                                     e1          
                                                 e2
                               e1                
                                                 e2
1-D Layout Swap Timing




                   Isailovic et al. 2004
1-D Layout Swap Control Logic




                       Isailovic et al. 2004
     2-D Configuration Layout
S3     S4         S1      S2        S3      S4   S1




                  A
            e1                   e2 A
                                   
A                         Si                     A
             P+ Ion                P+ Ion



S1     S4         S3      S2        S1      S4   S3




                       Top View
 2-D Layout Swap Operations
S3     S4            S1           e1   S2   e1    S3           S4   S1

                      e1                          e1
                              A                              A
                                                        
A                     e   2                              e
                                                         1            A

                                                   
                      e2                           e2
                                             
S1     S4            S3           e2    S2   e2     S1           S4   S3



     = Step 1
     = Step 2
     = Step 3
     = Step 4
     = Hyperfine interaction (Step 5)
2-D Layout Swap Timing




                   Whitney et al. 2003
2-D Layout Swap Control Logic




                       Whitney et al. 2003
                Comparison
• At the cost of extra classical control gates
  – Control logic was simplified for 2-D
     • Less space, hardware, and energy
  – Less steps to execute due to parallelism
  – Lower probability of electrons interfering with
    each other since they are kept farther apart
  – Tradeoff:
     • Datapath complexity vrs. Control complexity
                                Optimization
• Use a SIMD approach to speed it up
    – SIMD (Single Instruction Multiple Data)
    – Wire multiple swap cells to same control unit
    – Will work correctly if no other operations need to be
      done

                                            Swap Control



S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S
A       A       A       A       A       A       A       A       A       A       A       A       A       A
S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S   S
    Classical Versus Quantum
            Correction
•  Classically, we can use the majority voting
   procedure and redundancy to fix any number of
   errors. Example: 0->000, 1->111 allows a
   maximum of 1 error.
• Given error (bit flip) rate p, this scheme would fail
   with probability 3p^2(1-p)+p^3=3p^2-2p^3 so for
   encoding to reduce error rate, we must have p<1/2.
• Quantum Mechanically, we have 3 problems:
1. No cloning
2. Errors are continuous
3. Measurement destroys quantum states.
Error Correction Conditions and
    Discretization of Errors
• Error E can be decomposed into operations Ei
  so that E|psi><psi|=Si Ei|psi><psi|Ei†
• Correctable Errors {Ei}. In order for error
  correction to succeed, we must have
  PEiE†jP=aijP for some Hermitian a of complex
  numbers.
• The basis errors: I, X, Z, and Y (XZ) form a
  discrete basis set for a single qubit errors.
• Thus things like Shor codes can protect against
  any arbitrary single qubit errors.
                      Basic Code: Bit-flip
    • Idea is to use a special code, with redudant
      ancillas designed so that a special
      (syndrome) measurement allows us to
      determine the error without collapsing the
      qubit.
                           The measurement results correspond to 4
                           projects:
                           P1=|000><000|+|111><111|
                           P2=|100><100|+|011><011|
                           P3=|010><010|+|101><101|

(Nelson and Chuang)
                           P4=|001><001|+|110><110|
    • The final step is recovery: depending on
       measurement result, we flip the corresponding qubit.
    • Similarly, a phase-flip code is just a Hadamard-
       conjugated bit-flip code (phase-flipbit-flip in
       hadamard basis).
•Shor code is just
concatenation of bit flip with
phase-flip codes:
•where
|0>

) 
and
|1> -
)

                   (Nelson and Chuang)
       CSS and Steane Code
• Calderbank-Shor-Steane codes are a class of error-
  correcting codes that uses 2 classical linear codes
  capable of correcting t errors into a quantum code
  capable of correcting t qubits.
• Steane is the result of CSS used on classical
  Hammond codes.
• Classical linear codes are compactly described by
  either an n-k by n parity check matrix or a n by k
  generator. Example: For Hammond, a 4 bit input is
  converted to a 7 bit code block; the parity matrix is
  H=                 [[0, 0, 0, 1, 1, 1, 1]
                     [0, 1, 1, 0, 0, 1, 1]
                     [1, 0, 1, 0, 1, 0, 1]]
            Fault Tolerance
• The aim of fault tolerance is to implement circuit
  gates using encoded gates so that encoded
  qubits do not need to be decoded or measure to
  be acted upon, while at the same time designing
  encoded gates so that errors do not propagate
  and also design similarly fault-tolerant error
  correction procedures.
• Example: UX1=UX1U†U=X1X2U
• Definition: Fault-tolerant procedure is a
  procedure such that given the failure of any one
  component (wire, gate, preparation) causes at
  most 1 error in each encoded output block of
  qubits.
             Error Model for Fault Tolerance
•   1)Random Errors: We have assumed that the errors have no systematic
    component. Errors that have random phases accumulate like a random
    walk, so that the probability of error accumulates roughly linearly with
    the number of gates applied. But it the errors have systematic phases,
    then the error amplitude can increase linearly with the number of gates
    applied. Hence, for our quantum computer to perform well, the rate
    for systematic errors must meet a more stringent requirement than the
    rate for random errors.
    2)Uncorrelated Errors: errors are both spatially and temporally uncorrelated
    with each other.
    3)No leakage errors: errors considered so far have either involved
    entanglement with the environment or some unspecified rotation; qubit can
    leak out of 2-dimensional Hilbert into larger space; we need to repeated
    interrogate qubit for leakage and discard/replace
    4)Limitless supply of fresh ancilla qubits
    5)Error rate independent on number of qubits--this is related to physical
    implementation and needs to be tailored.
    6) Maximal parallelism. We have assumed that many quantum gates can
    be executed in parallel in a single time step. This assumption enables
    us to perform error recovery in all of our code blocks at once, and so is
    critical for controlling qubit storage errors.
    Fault Tolerant Universal Gate Set
• The Hadamard, CNOT, P8, and
  Phase gate form a universal computational
  set.
• By the transversal effect, both the encoded
  (for 7 qubit Steane Codes) Hadamard and
  CNOT gates are already fault tolerant:




                       (Nelson and Chuang)
   Similarly, the P8 gate can be constructed from




(Nelson and Chuang)


Where the ancilla qubit is prepared in state (|0>+eiπ/4|1>)/2
through a fault tolerant measurement of eiπ/4SX. The phase
gate is simply two application of the P8 gate.
   • We can construct fault tolerant
     measurements as below:




(Nelson and Chuang)
                      Concatenation
                           • If probability of failure for
                             components at lowest code
                             level is p, then for second
                             level, it’s at most c*p^2; for
                             third level, it’s c*(c*p 2) 2 =c3
                             *p4.
                           • In general, after k levels of
                             encoding, probability is
                             (cp)2^k/c with the simulating
                             circuiting being of size d^k
                             times size of original circuit
                             where d is a constant
(Nelson and Chuang)
                             representing maximum
                             number of operations need
                             by fault tolerant procedure
                             for gate and error
                             correction.
        Threshhold Theorem
• Theorem: A quantum circuit containing p(n) gates
  may be simulated with probability of error at most e
  using O(Poly(log(p(n)/e)p(n)) gates on hardware
  whose components fail with probability at most p,
  provided p is below some constant threshold, p<pth
  and reasonable assumptions about the underlying
  hardware (such as the parallelism needed for wide-
  scale error correction and reliable classical
  computation to process error syndromes to
  determine recovery procedures.
• Basically says that in theory at least, quantum
  computation is not destined to be error-prone as
  long as we can achieve pth .
           Practical Example
• Factoring a 130 digit (430 bit) number would
  take months classically to do.
• Shor's algorithm would require 5*432=2160
  qubits and around 3*10^9 Toffoli Gates: error
  per gate needs to be less than 10EE-9
• Steane found that if we use codes of block size
  55 that can correct up to 5 errors and use
  400000 qubits, then we'd need a gate error on
  the order of 10^-5.
                  References
• Datapath and Control for Quantum Wires, Nemanja
  Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz,
  Dean Copsey, Frederic T. Chong, Isaac L. Chuang, and
  Mark Oskin. Appears in Transactions on Architecture
  and Code Optimization (TACO),Vol 1, No. 1, pp 34-61,
  March 2004
• Toward a Scalable, Silicon-Based Quantum Computing
  Architecture, Dean Copsey, Mark Oskin, Francois
  Impens, Tzvetan Metodiev, Andrew Cross, Frederic T.
  Chong, Isaac L. Chuang, and John Kubiatowicz,
  Appears in Journal of Selected Topics in Quantum
  Electronics, Vol 9, No. 6, pp 1552-1569.
  November/December 2003
                 References
• Building Quantum Wires: The Long and the Short of
  it, Mark Oskin, Frederic T. Chong, Isaac L. Chuang, and
  John Kubiatowicz. Appears in Proceedings of the 30th
  International Symposium on Computer Architecture
  (ISCA 2003)
• The Effect of Communication Costs in Solid-State
  Quantum Computing Architectures, Dean Copsey,
  Mark Oskin, Tzvetan Metodiev, Frederic T. Chong,
  Isaac Chuang, and John Kubiatowicz. Appears in
  Proceedings of the 15th ACM Symposium on
  Parallelism in Algorithms and Architectures (SPAA
  2003)
                  References
• Can we build Classical Control Circuits for Silicon
  Quantum Computers?, Mark Whitney, Yatish Patel,
  Nemanja Isailovic, and John Kubiatowicz. Appears in
  Proceedings of the Second Workshop in Non-Silicon
  Computing (NSC2), June 2003
• Nielsen, Michael A. and Chuang, Isaac L. Quantum
  Computation and Information, Chapter 10. Cambridge
  University Press: 2000.
• Preskill, John. “Fault Tolerant Quantum Computation.”

								
To top