electronics book part 6 by kamra.attock


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									      EXAMPLE 6.18   Determine IDQ, VGSQ, and VDS for the p-channel JFET of Fig. 6.56.

                                                                                             Figure 6.56 Example 6.18.

                                                         20 k ( 20 V)
                                                 VG                                              4.55 V
                                                         20 k 68 k
                     Applying Kirchhoff’s voltage law gives
                                                         VG         VGS             ID R S      0
                     and                                      VGS         VG           ID R S
                     Choosing ID     0 mA yields
                                                         VGS             VG            4.55 V
                     as appearing in Fig. 6.57.
                     Choosing VGS      0 V, we obtain
                                                         VG                    4.55 V
                                               ID                                               2.53 mA
                                                         RS                   1.8 k
                     as also appearing in Fig. 6.57.
                     The resulting quiescent point from Fig. 6.57:
                                                                  ID Q        3.4 mA
                                                              VGSQ            1.4 V

                                                          ID (mA)

                                      I D 3.4 mA                  Q - point

                                     – 5 – 4 –3 – 2 –1   01         234                         VGS
                                                                               VP                     Figure 6.57 Determining the
                                                                                                      Q-point for the JFET configura-
                                                                  VGS 1.4 V
                                                                     Q                                tion of Fig. 6.56.

290                  Chapter 6   FET Biasing
For VDS, Kirchhoff’s voltage law will result in
                                       ID R S       VDS       ID R D      VDD          0
and                      VDS           VDD         I D (R D     R S)
                                       20 V         (3.4 mA)(2.7 k               1.8 k )
                                       20 V         15.3 V
                                       4.7 V

Since the dc solution of a FET configuration requires drawing the transfer curve for
each analysis, a universal curve was developed that can be used for any level of IDSS
and VP. The universal curve for an n-channel JFET or depletion-type MOSFET (for
negative values of VGSQ) is provided in Fig. 6.58. Note that the horizontal axis is not
that of VGS but of a normalized level defined by VGS /VP, theVP indicating that
only the magnitude of VP is to be employed, not its sign. For the vertical axis, the
scale is also a normalized level of ID /IDSS. The result is that when ID IDSS, the
ratio is 1, and when VGS VP, the ratio VGS /VPis 1. Note also that the scale
for ID/IDSS is on the left rather than on the right as encountered for ID in past exer-
cises. The additional two scales on the right need an introduction. The vertical scale
labeled m can in itself be used to find the solution to fixed-bias configurations.
The other scale, labeled M, is employed along with the m scale to find the solution

                                                                                                   VP                 VG G
             I DSS                                                                          m=                 M= m
                                                                                                 RS IDSS               VP
      1.0                                                                                   5                  1.0

      0.8                                                                                   4                  0.8

      0.6                                                                                   3                  0.6

                     Normalized curve
                                       V     2
                     of ID = I DSS 1 – GSP
      0.4                                                                                   2                  0.4

      0.2                                                                                   1                  0.2

            –1             – 0.8                 – 0.6            – 0.4                – 0.2               0
                                                                                                                      VGS    Figure 6.58 Universal JFET bias
                                                                                                                       VP    curve.

                                                                                6.12       Universal JFET Bias Curve                                     291
                     to voltage-divider configurations. The scaling for m and M come from a mathemati-
                     cal development involving the network equations and normalized scaling just intro-
                     duced. The description to follow will not concentrate on why the m scale extends from
                     0 to 5 at VGS /VP 0.2 and the M scale from 0 to 1 at VGS /VP 0 but rather
                     on how to use the resulting scales to obtain a solution for the configurations. The
                     equations for m and M are the following, with VG as defind by Eq. (6.15).
                                                                m                                              (6.35)

                                                            M       m                                          (6.36)

                     with                                   VG
                                                                    R1 R2
                     Keep in mind that the beauty of this approach is the elimination of the need to sketch
                     the transfer curve for each analysis, that the superposition of the bias line is a great
                     deal easier, and that the calculations are fewer. The use of the m and M axes is best
                     described by examples employing the scales. Once the procedure is clearly under-
                     stood, the analysis can be quite rapid, with a good measure of accuracy.

      EXAMPLE 6.19   Determine the quiescent values of ID and VGS for the network of Fig. 6.59.

                                                                                         Figure 6.59 Example 6.19.

                     Calculating the value of m, we obtain
                                                    VP             3 V
                                             m                                          0.31
                                                   IDSSRS        (6 mA)(1.6 k )
                     The self-bias line defined by RS is plotted by drawing a straight line from the origin
                     through a point defined by m       0.31, as shown in Fig. 6.60.
                     The resulting Q-point:
                                             ID                                  VGS
                                                    0.18     and                        0.575
                                            IDSS                                VP

292                  Chapter 6   FET Biasing

                RB                    Io                                                             C                              Vo
                            C                           Vo
     Ii                                                                               Ii                                 Io
                                           C2                                                 B
                  B                                                           Vi
                                                  Zo                                                                    RC
          C1                                                                                                                       Zo
                                                                                             RB          E
           Zi                   E                                            Zi

Figure 8.1 Common-emitter fixed-bias con-                                    Figure 8.2 Network of Figure 8.1 following
figuration.                                                                  the removal of the effects of VCC, C1, and C 2.

                                                 Ii                    Ib                                          Ic

                                                                       b                                       c                   +
                                            + Zi                                                                              Io
                                            Vi                                      re            Ib
                                                            RB                                            ro       RC
Figure 8.3 Substituting the re              –                                                                                      –
model into the network of Fig.                                                                                               Zo

     The next step is to determine , re, and ro. The magnitude of           is typically ob-
tained from a specification sheet or by direct measurement using a curve tracer or
transistor testing instrument. The value of re must be determined from a dc analysis
of the system, and the magnitude of ro is typically obtained from the specification
sheet or characteristics. Assuming that , re, and ro have been determined will result
in the following equations for the important two-port characteristics of the system.
     Zi: Figure 8.3 clearly reveals that

                                                       Zi         R B re             ohms                                     (8.1)

    For the majority of situations RB is greater than re by more than a factor of 10
(recall from the analysis of parallel elements that the total resistance of two parallel
resistors is always less than the smallest and very close to the smallest if one is much
larger than the other), permitting the following approximation:

                                                       Zi              re                          ohms                       (8.2)
                                                                               RB 10 re
    Zo: Recall that the output impedance of any system is defined as the impedance
Zo determined when Vi 0. For Fig. 8.3, when Vi     0, Ii  Ib 0, resulting in an
open-circuit equivalence for the current source. The result is the configuration of
Fig. 8.4.                                                                                                                                                            Zo
                                                                                                                                                      ro        RC
                                                       Zo         R C ro                   ohms                               (8.3)

If ro      10 RD, the approximation RC ro RC is frequently applied and

                                                       Zo         RC                                                          (8.4)      Figure 8.4 Determining Zo for
                                                                               ro 10RC                                                   the network of Fig. 8.3.

                                                                 8.2        Common-Emitter Fixed-Bias Configuration                                                  339

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