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SEQUENTIAL LOGIC DESIGN PRINCIPLES

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SEQUENTIAL LOGIC DESIGN PRINCIPLES Powered By Docstoc
					SEQUENTIAL LOGIC
DESIGN PRINCIPLES
BISTABLE ELEMENTS
BISTABLE ELEMENTS
BISTABLE ELEMENTS
LATCHES, FLIP-FLOPS

LATCH: OUTPUT CHANGES AT ANY TIME
 BASED ON INPUT
FLIP-FLOP: OUTPUT CHANGES
 CONTROLLED BY SAMPLED INPUTS AND
 CLOCK
S-R LATCH
S-R LATCH SYMBOL
S-R LATCH TIMING
S-R LATCH TIMING
PARAMETERS
S\-R\ LATCH
S-R LATCH WITH ENABLE
D LATCH

NO PROBLEM WITH R=S=1
D LATCH

TRANSPARENT LATCH:
EDGE-TRIGGERED
D FLIP-FLOP

MASTER, SLAVE
EDGE-TRIGGERED
D FLIP-FLOP

DYNAMIC INPUT INDICATOR
EDGE-TRIGGERED
D FLIP-FLOP WITH ENABLE
SCAN FLIP-FLOP
MASTER/SLAVE S-R FLIP-FLOP

PULSE-TRIGGERED FLIP-FLOP
MASTER/SLAVE J-K FLIP-FLOP
SOLVE PROBLEM OF S=R=1
1s CATCHING, 0s CATCHING
EDGE-TRIGGERED J-K
FLIP-FLOP
SOLVES 1s AND 0s CATCHING PROBLEM
T FLIP-FLOP
CHANGES STATE EVERY CLOCK TICK
T FLIP-FLOP WITH ENABLE
CLOCKED SYNCHRONOUS
STATE MACHINES

STATE: COLLECTION OF STATE
 VARIABLES CONTAINING ALL
 INFORMATION FROM PAST NEEDED TO
 PREDICT FUTURE BEHAVIOR
STATE VARIABLES BINARY VALUES
CIRCUIT WITH n VARIABLES HAS 2n
 STATES
CLOCKED SYNCHRONOUS
STATE MACHINES

STATE MACHINE - GENERIC NAME
CLOCKED - FLIP-FLOPS HAVE CLOCK
 INPUT
SYNCHRONOUS - SAME CLOCK
STATE CHANGES BASED ON CLOCK
 ACTIVITY
STATE-MACHINE STRUCTURE

MEALY MACHINE
MOORE MACHINE
CHARACTERISTIC EQUATION

DESCRIBES FUNCTIONAL BEHAVIOR OF
 LATCH OR FLIP-FLOP
EXAMPLES:
 S-R LATCH                 Q* = S + R’  Q
 EDGE TRIG’D D FLIP-FLOP   Q* = D
STATE MACHINE

next state = F(current state, input)
output = G(current state, input)

ANALYSIS GOAL: DETERMINE F, G
STATE MACHINE ANALYSIS

DETERMINE F AND G
USE F AND G TO CONSTRUCT
 STATE/OUTPUT TABLE
DRAW STATE DIAGRAM (OPTIONAL)
STATE MACHINE DESIGN
CONSTRUCT STATE/OUTPUT TABLE
MINIMIZE NUMBER OF STATES (OPTIONAL)
ASSIGN STATE VARIABLES
CHOOSE FLIP-FLOP TYPE (D OR J-K)
CONSTRUCT EXCITATION TABLE
DERIVE EXCITATION EQUATIONS
DERIVE OUTPUT EQUATIONS
DRAW LOGIC DIAGRAM
DESIGN EXAMPLE
DESIGN A CLOCKED SYNCHRONOUS STATE
 MACHINE WITH TWO INPUTS, A AND B
 AND A SINGLE OUTPUT Z THAT IS 1 IF:
 A HAD THE SAME VALUE AT EACH OF THE
  TWO PREVIOUS CLOCK TICKS, OR
 B HAS BEEN 1 SINCE THE LAST TIME THE
  FIRST CONDITION WAS TRUE
OTHERWISE THE OUTPUT SHOULD BE 0.
STATE ASSIGNMENT

CODED STATE: BINARY COMBINATION
 ASSIGNED TO STATE
NUMBER OF FLIP-FLOPS NEEDED IS
 log2(TOTAL NUMBER OF STATES)
MAY HAVE UNUSED STATES
STATE ASSIGNMENT

CHOOSE INITIAL STATE CODE WHICH IS
 EASY TO FORCE
MINIMIZE CHANGES AT TRANSITIONS
EXPLORE UNUSED STATES
CONSIDER USING MORE THAN THE
 MINIMUM NUMBER OF STATE VARIABLES
ETC.
STATE ASSIGNMENT
UNUSED STATES

MINIMAL RISK APPROACH
MINIMAL COST APPROACH
 SYNTHESIS...

TRANSITION TABLE: NEXT CODED STATE
 FOR EACH STATE AND INPUT
EXCITATION TABLE: FLIP-FLOP
 EXCITATION INPUT VALUES NEEDED TO GO
 TO NEXT STATE
D FLIP-FLOPS: TRANSITION/EXCITATION
 TABLE
SYNTHESIS WITH J-K
FLIP-FLOPS

CHARACTERISTIC EQUATION:
    Q* = J  Q’ + K’  Q
NO INDEPENDENT EQUATIONS FOR J, K
J-K APPLICATION TABLE
FEEDBACK SEQUENTIAL
CIRCUITS

FUNDAMENTAL MODE CIRCUITS -
 INPUTS NOT ALLOWED TO CHANGE
 SIMULTANEOUSLY
ANALYZE: BREAK FEEDBACK LOOPS
INSERT BUFFER
FEEDBACK SEQUENTIAL
CIRCUITS

TOTAL STATE: INTERNAL AND INPUT
 STATE
STABLE TOTAL STATE
UNSTABLE TOTAL STATE
MULTIPLE FEEDBACK LOOPS

BREAK ALL LOOPS
CUT SETS
ANY MINIMAL CUT SET IS OK
NON-MINIMAL CUT SET GIVE SAME
 RESULT, MORE STATES
RACES

ONE INPUT CHANGES  MULTIPLE
 INTERNAL VARIABLES CHANGE STATE
NON-CRITICAL RACE
CRITICAL RACE
STATE AND FLOW TABLES

TRANSITION TABLE  STATE TABLE
STATE TABLE  FLOW TABLE
FLOW TABLES ELIMINATE:
 UNUSED STATES
 NEXT-STATE ENTRIES THAT CANNOT BE
  REACHED FROM A STABLE STATE WITH A
  SINGLE INPUT CHANGE
FEEDBACK SEQUENTIAL
CIRCUIT DESIGN

Q* = (forcing term) + (holding term)Q
FEEDBACK SEQUENTIAL
CIRCUIT DESIGN

HAZARD-FREE EXCITATION LOGIC
KARNAUGH MAPS - CONSENSUS TERM(S)
DESIGN EXAMPLE

PULSE-CATCHING CIRCUIT:
 DESIGN A FEEDBACK CIRCUIT WITH TWO
 INPUTS, P (PULSE) AND R (RESET), AND A
 SINGLE OUTPUT Z THAT IS NORMALLY 0.
 Z IS 1 WHENEVER A 0-TO-1 TRANSITION
 OCCURS ON P, AND SHOULD BE RESET TO
 0 WHENEVER R IS 1.
FEEDBACK SEQUENTIAL
CIRCUIT DESIGN
WORD DESCRIPTION  PRIMITIVE FLOW
 TABLE
MINIMIZE NUMBER OF FLOW TABLE STATES
RACE-FREE ASSIGNMENT OF STATES
CREATE TRANSITION TABLE
GET EXCITATION MAP, HAZARD-FREE
 EXCITATION EQUATIONS
ELIMINATE ESSENTIAL HAZARDS
DRAW LOGIC DIAGRAM
 RACE-FREE ASSIGNMENT
 OF STATES

ADJACENCY DIAGRAM
n-CUBE: 2n VERTICES LABELED WITH n-BIT
 STRING; EACH VERTEX ADJACENT TO n
 OTHERS WHOSE LABELS DIFFER IN ONE BIT
RACE-FREE ASSIGNMENT: MAP NODES
 AND ARCS OF ADJACENCY DIAGRAM ONTO
 NODES AND ARCS OF n-CUBE
FUNDAMENTAL-MODE
CIRCUIT REQUIREMENTS

ONLY ONE INPUT CHANGES AT A TIME
MAX. PROPAGATION DELAY LESS THAN
 TIME BETWEEN INPUT CHANGES
STATES ASSIGNED WITHOUT CRITICAL
 RACES
EXCITATION LOGIC HAZARD FREE
NO ESSENTIAL HAZARDS
ESSENTIAL HAZARDS

POSSIBILITY OF ERRONEOUS NEXT
 STATE
INPUT CHANGE NOT SEEN BY ALL
 EXCITATION CIRCUITS BEFORE SOME
 STATE VARIABLE TRANSITIONS
 PROPAGATE BACK TO THEIR INPUTS
ESSENTIAL HAZARDS

TIMING SKEW = DIFFERENCE IN INPUT
 ARRIVAL TIMES
TIMING SKEW HAS TO BE LESS THAN
 PROPAGATION DELAY OF EXCITATION
 CIRCUITS AND FEEDBACK LOOPS
ELECTRICAL CIRCUIT LEVEL PROBLEM

				
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