Cypress Semiconductor VHDL Training by 242CpTmR

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									PROGRAMMABLE LOGIC
  DESIGN WITH VHDL
                           Objectives

 Upon completion of this training, your VHDL knowledge will enable
  you to:

       Implement efficient combinatorial and sequential logic
       Design state machines and understand implementation trade-offs
       Use hierarchy / Create reusable components
       Identify how VHDL will synthesize and fit into a PLD, CPLD
        and FPGA
                    Objectives (contd.)
 Upon completion of this training, you will be able to use Warp to:
    Compile and synthesize VHDL designs for programmable
     logic devices
    Create VHDL or Verilog timing simulation models for
     popular third party simulators.
    Target PLDs/CPLDs
      • Simulate the resulting device with the Aldec full timing
         simulator
      • Use the report file to determine operating frequency, set-
         up time, clock to output delay, and device resource usage.
                                      Agenda
   Intro, Why Use VHDL?,                        Aggregates and Subscripts
   Design Flow                                  Registers, Latches and Implicit Memory
   VHDL Design Descriptions                     Exercise #4 - Design a counter
   The Entity, Ports, Modes, Types              Lunch
   Exercise #1 - Write an entity statement      State Machines and State Encoding
   The Architecture, differing styles           Exercise #5 - Design a state machine
   Concurrent and Sequential statements         Design Hierarchy - components, pkg’s, libraries
   Processes: Signals vs. Variables             Exercise #6 - Design a loadable counter hierarchy
   VHDL Operators/Overloading/Inferencing       Generate Statement
   VHDL Identifiers                             Multiplexing I/O pins
   Exercise #2 - write an architecture          Exercise #7 - DRAM output controller
   Tri-State Logic, Don't Cares                 User defined attributes
   Warp GUI overview                            CPLD synthesis directives
   Exercise #3 - Design a bus controller        Miscellaneous Topics and Wrap-up
                       Introduction
 VHDL is used to:
    document circuits
    simulate circuits
    synthesize design descriptions
 Synthesis is the reduction of a design description to a lower-
  level representation (such as a netlist or a set of equations).
 This training course covers VHDL for PLD synthesis
 The course will at times draw upon the concepts of VHDL as a
  simulation language
                  Why Use VHDL?
 Quick Time-to-Market
    Allows designers to quickly develop designs requiring
       tens of thousands of logic gates
    Provides powerful high-level constructs for describing
       complex logic
    Supports modular design methodology and multiple levels
       of hierarchy
 One language for design and simulation
 Allows creation of device-independent designs that are
  portable to multiple vendors. Good for ASIC Migration
    Allows user to pick any synthesis tool, vendor, or device
              VHDL vs. Verilog
                 History
 Developed by DoD in early    1983 -Gateway founded by
  80s as means for              Genrad’s HDL and HILO
  Contractors to Describe       simulator author.Releases
  Designs-Funded VHSIC          Verilog HDL and Simulator
 1987 IEEE ratified 1076      1985 Enhanced Verilog-
  and DoD mandated              XL-used for high end
  VHDL(F-22) and EDA            designs -Fast Simulator -
  vendors created tools.        interpretive-no need to
 1993 - IEEE 1076 ‘93          precompile
 1996 Commercial Sim and      1990 Cadence buys
  Synthesis tools become        Gateway-nearly all ASIC
  available and 1164 pkg        foundries used XL as
  enables multi value logic     Golden Simulator
                               1995 IEEE 1364
               VHDL vs. Verilog
 Compilation/Data Types/High Level Constructs/Verbosity/Ease

 Many E-A pairs may reside     Order or Code is crucial to
  in single system file.         obtaining desired output.
 User Can define Data          Simple Data Types are
  Types-Powerful                 controlled by language
 High Level Modeling w/        No Equivalent High Level
  Package, Config, Generate      Modeling Constructs
 Strongly Typed Language -     Verilog has looser
  models must be precisely       structure-can lead to
  coded-often longer code        unwanted and unidentified
 Less intuitive but much        errors-more concise code.
  more powerful constructs      Easiest to Grasp-more
                                 prone to create unwanted
                                 results
                         WARP5.0
   WARP2 Release 5.0 now supports Verilog Synthesis
   Same great Synthesis as VHDL
   Includes Aldec Full Timing Simulator and FSM Editor
   Generates timing simulation models for major third party
    VHDL and Verilog simulators
   New GUI-Microsoft Std Interface
   Even Better HDL Editor
   Supports All Cypress Devices
   Windows 95, NT, UNIX
   Same Great $99 Price
         VHDL Design Descriptions
 VHDL design descriptions consist of an ENTITY
  declaration and an ARCHITECTURE body

     The ENTITY declaration describes the design I/O

     The ARCHITECTURE body describes the
      content or function of the design

     Every architecture needs an entity so it is common
      to refer to them together as an
      ENTITY/ARCHITECTURE PAIR
Example Entity/Architecture Pair:
    A 2-Input And Function
ENTITY and2 IS PORT (
       a,b :   IN std_logic;
       f:      OUT std_logic);
END and2;

ARCHITECTURE behavioral OF and2 IS
BEGIN
    f <= a AND b;
END behavioral;
                 The Entity

 A “BLACK BOX”
    The ENTITY describes the periphery of the
      black box (i.e., the design I/O)‫‏‬


                      BLACK_BOX

                rst
                              q[7:0]
                d[7:0]
                                  co
                clk
          The Entity Declaration
ENTITY entity_name IS
-- optional generics
PORT (
    name : mode type ;
    ...
) ;
END entity_name;

 entity_name is an arbitrary name
 generics are used for defining parameterized components
 name is the signal/port identifier and may be a comma
  separated list for ports of identical modes and types
 mode describes the direction the data is flowing
 type indicates the set of values name may be assigned
                     Ports

 The Entity (“BLACK BOX”) has PORTS
    PORTS are the points of communication
      • PORTS are usually the device pins

    PORTS have an associated name, mode, and type
                   IEEE 1076 Types
 VHDL is a strongly typed language (you cannot assign a signal of
  one type to the signal of another type)‫‏‬
    bit - a signal of type bit that can only take values of '0' or '1'
    bit_vector - a grouping of bits (each can be '0' or '1')
     SIGNAL     a: BIT_VECTOR(0 TO 3);     -- ascending range
     SIGNAL     b: BIT_VECTOR(3 DOWNTO 0); -- descending range
                a <= "0111"; -- double quotes used for vectors
                b <= "0101";
     This means that:      a(0) = '0'     b(0) = '1'
                           a(1) = '1'     b(1) = '0'
                           a(2) = '1'     b(2) = '1'
                           a(3) = '1'     b(3) = '0'
      IEEE 1076 TYPES (contd.)‫‏‬

 INTEGER
   • useful as index holders for loops, constants, generics,
     or high-level modeling
 BOOLEAN
   • can take values ‘TRUE’ or ‘FALSE’
 ENUMERATED
   • has user defined set of possible values, e.g.,
   • TYPE traffic_light IS (green, yellow, red);
                     IEEE 1164
 A package created to solve the limitations of the BIT type
 Nine values instead of just two ('0' and '1')‫‏‬
 Allows increased flexibility in VHDL coding, synthesis, and
  simulation
 STD_LOGIC and STD_LOGIC_VECTOR are used instead
  of BIT and BIT_VECTOR when a multi-valued logic
  system is required
 STD_LOGIC and STD_LOGIC _VECTOR must be used
  when tri-state logic (Z) is required
 To be able to use this new type, you need to add 2 lines to
  your code:
      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
                  1164 Types
 std_logic and std_logic_vector are the industry
  standard logic type for digital design
 Values for Simulation & Synthesis
    ‘0’ -- Forcing ‘0’
    ‘1’ -- Forcing ‘1’
    ‘Z’ -- High Impedance
    ‘L’ -- Weak ‘0’
    ‘H’ -- Weak ‘1’
    ‘-’     -- Don’t care
 Values for Simulation only (std_ulogic):
    ‘U’ -- Uninitialized
    ‘X’ -- Forcing Unknown
    ‘W’ -- Weak Unknown
Exercise #1: The Entity - A Walk through
    Write an entity declaration for the following:
          Port D is a 12-bit bus, input only
          Port OE and CLK are each input bits
          Port AD is a 12-bit, three-state bi-directional bus
          Port A is a 12-bit bus, output only
          Port INT is a three-state output
          Port AS is an output also used internally
                             my_design

                       d[11:0]      ad[11:0]
                       oe            a[11:0]
                       clk               int
                                         as
                   The Architecture
 Architectures describe what is in the black box (i.e., the
  structure or behavior of entities)‫‏‬
 Descriptions can be either a combination of
    Structural descriptions
        • Instantiations (placements of logicmuch like in a
           schematicand their connections) of building blocks
           referred to as components
    Behavioral/Dataflow descriptions
        • Algorithmic (or “high-level”) descriptions:
           IF a = b THEN state <= state5;
         • Boolean equations (also referred to as dataflow):
           x <= a OR (b AND c);
    The Architecture Declaration
ARCHITECTURE arch_name OF entity_name IS
    -- optional signal declarations, etc.
BEGIN
    --VHDL statements
END arch_name;



 arch_name is an arbitrary name
 optional signal declarations are used for signals local to
  the architecture body (that is, not the entity’s I/O).
 entity_name is the entity name
 statements describe the function or contents of the entity
Architecture Body Styles : Behavioral
ENTITY compare IS PORT (
        a, b:    IN std_logic_vector(0 TO 3);
        equals: OUT std_logic);
END compare;
ARCHITECTURE behavior OF compare IS
BEGIN
    comp: PROCESS (a,b)‫‏‬
    BEGIN
        IF a = b THEN
             equals <= '1' ;
        ELSE
             equals <= '0' ;
        END IF ;
    END PROCESS comp;
END behavior;
Architecture Body Styles : Dataflow

ENTITY compare IS PORT (
       a, b:   IN std_logic_vector(0 TO 3);
       equals: OUT std_logic);
END compare;

ARCHITECTURE dataflow OF compare IS
BEGIN
    equals <= '1' WHEN a = b ELSE '0' ;
END dataflow;
Architecture Body Styles : Structural
ENTITY compare IS PORT (
        a, b:   IN std_logic_vector(0 TO 3);
        equals: OUT std_logic);
END compare;
USE WORK.gatespkg.ALL ;
ARCHITECTURE structure OF compare IS
    SIGNAL x : std_logic_vector (0 to 3) ;
BEGIN
    u0: xnor2 PORT MAP (a(0),b(0),x(0)) ;
    u1: xnor2 PORT MAP (a(1),b(1),x(1)) ;
    u2: xnor2 PORT MAP (a(2),b(2),x(2)) ;
    u3: xnor2 PORT MAP (a(3),b(3),x(3)) ;
    u4: and4 PORT MAP (x(0),x(1),x(2),x(3),equals) ;
END structure;
     Comparing Architecture Styles

 These examples synthesize to equivalent circuits
 In more elaborate designs, some descriptions may yield
  more efficient circuits
    sloppy code = inefficient results (see section 3.3.4)‫‏‬
 Use styles that make your designs easier to describe and
  maintain
    Behavioral/Dataflow exploit module generation
      (described later)‫‏‬
    Structural descriptions may make the design less
      portable (may rely on a library of vendor-specific
      components)‫‏‬
                Module Generation
 In Warp release 4.0, a package called ‘std_arith’ can be
  used to overload the arithmetic (+, -, etc.) and relational
  operators (=, /=, <, etc.,) for std_logic, std_logic_vector
  and integer types
    Using this package causes adders, counters,
       comparators, etc., to automatically replace the
       operators in the design. These are optimized for the
       target architecture and synthesis goal (area/speed)‫‏‬
        • This is known as module generation
                  VHDL Statements
 There are two types of statements, Concurrent and Sequential

 Concurrent Statements (means in parallel)‫‏‬
       Concurrent statements are “executed” concurrently (at
        the same time)‫‏‬
         The order of concurrent statements is not important
         Most of the examples we have seen so far have been
          concurrent statements:
             – Boolean Equations
             – WHEN-ELSE
             – WITH-SELECT-WHEN
           VHDL Statements (cont.)‫‏‬
 Sequential Statements (means in series)‫‏‬
       Sometimes we need to model complex functions.
         In that case, we can use an “algorithm” or model
         to describe the function. This is done with
         Sequential Statements
         With Sequential statements, the ORDER of the
          statements is important (example later)‫‏‬
         Therefore, we use a process to mark the
          beginning and end of a block of sequential
          statements
         Each completed process is considered to be one
          big concurrent statement (there can be many
          processes inside one architecture)‫‏‬
          What is a VHDL “Process” ?
 Processes are either awake or asleep (active or inactive)‫‏‬

 A process normally has a sensitivity list
    When a signal in that sensitivity list changes value, the
      process wakes up and all of the sequential statements
      are “executed”
    For example, a process with a clock signal in its
      sensitivity list will become active on changes of the
      clock signal

 At the end of the process, all outputs are assigned and the
  process goes back to sleep until the next time a signal
  changes in the sensitivity list
           The Process (contd.)‫‏‬

label: PROCESS (sensitivity list)‫‏‬
-- variable declarations
BEGIN
-- sequential statements
END PROCESS label ;

 The process label and variable declarations are
  optional
 The process executes when one of the signals in the
  sensitivity list has an event
          Combinational Logic

 Can be described with concurrent statements
    boolean equations
    when-else
    with-select-when
    component instantiatons
 Can be described with sequential statements
    if-then-else
    case-when
Combinational Logic w/ Boolean Equations

  Boolean Equations can be used in both concurrent
   and sequential signal assignment statements.
  A 4-1 multiplexer is shown below
                                                       s
                                                        2
  x <= (a AND NOT(s(1)) AND NOT(s(0))) OR
                                                a
       (b AND NOT(s(1)) AND s(0)) OR            b           x
                                                      mux
       (c AND s(1) AND NOT(s(0))) OR            c
       (d AND s(1) AND s(0)) ;                  d
           Selective Signal Assignment:
                 with-select-when
   Assignment based on a selection signal
   WHEN clauses must be mutually exclusive
   Use a WHEN OTHERS when all conditions are not specified
   Only one reference to the signal, only one assignment operator (<=)‫‏‬

WITH selection_signal SELECT
signal_name <= value_1 WHEN value_1 of selection_signal,
               value_2 WHEN value_2 of selection_signal,
               ...
               value_n WHEN value_n of selection_signal,
               value_x WHEN OTHERS;
      Combinational Logic w/
    Selective Signal Assignment
 The same 4-1 multiplexer is shown below

  with s select                                  s
         x <= a when “00” ,                       2

               b when “01” ,                a
               c when “10” ,                b         x
                                                mux
                                            c
               d when others ;
                                            d
      More on with-select-when

 You can use a range of values

  with int_value select
         x <= a when 0 to 3,
              b when 4 | 6 | 8 ,
              c when 10 ,
              d when others ;
    Conditional Signal Assignment:
              when-else
 Signal is assigned a value based on conditions
 Any simple expression can be a condition
 Priority goes in order of appearance
 Only one reference to the signal, only one assignment
  operator (<=)‫‏‬
 Use a final ELSE to avoid latches
signal_name <= value_1 WHEN condition1 ELSE
                        value_2 WHEN
condition2 ELSE
                        ...
                        value_n WHEN condition
N ELSE
                        value_x ;
    Combinational Logic w/
  Conditional Signal Assignment
 The same 4-1 multiplexer is shown below

x <= a when (s = “00”) else                      s
     b when (s = “01”) else                       2

     c when (s = “10”) else                 a
     d;                                     b         x
                                                mux
                                            c
                                            d
    Combinational Logic w/
  Conditional Signal Assignment
 The when conditions do not have to be mutually
  exclusive (as in with-select-when)‫‏‬
 A priority encoder is shown below

 j <= w when (a = ‘1’) else
      x when (b = ‘1’) else
      y when (c = ‘1’) else
      z when (d = ‘1’) else
      “000” ;
          Combinatorial Logic
        w/ Sequential Statements

 Grouped together with Processes
 Processes are concurrent with one another and with
  concurrent statements
 Order of sequential statements does make a
  difference in synthesis
Sequential Statements: if-then-else
 Used to select a set of statements to be executed
 Selection based on a boolean evaluation of a
    condition or set of conditions
 Absence of ELSE results in implicit memory
IF condition(s) THEN
    do something;
ELSIF condition_2 THEN -- optional
    do something different;
ELSE                           -- optional
    do something completely different;
END IF ;
                        if-then-else

 4-1 mux shown below
mux4_1: process (a, b, c, d, s)‫‏‬
      begin
             if s = “00” then x <= a ;              s
                                                     2
                elsif s = “01” then x <= b ;
                elsif s = “10” then x <= c ;   a
                                               b         x
                                                   mux
                else x <= d ;                  c
             end if;                           d
      end process mux4_1 ;
Sequential Statements: Case-When
CASE selection_signal IS
    WHEN value_1_of_selection_signal =>
      (do something)     -- set of statements 1
    WHEN value_2_of_selection_signal =>
      (do something)     -- set of statements 2
...
    WHEN value_N_of_selection_signal =>
      (do something)     -- set of statements N
    WHEN OTHERS =>
      (do something)     -- default action
END CASE ;
       The CASE Statement: 4-1 Mux
ARCHITECTURE archdesign OF design IS
   SIGNAL s: std_logic_vector(0 TO 1);
BEGIN
   mux4_1: PROCESS (a,b,c,d,s)‫‏‬
   BEGIN                                      s
         CASE s IS                             2

                WHEN "00" => x <= a;     a
                WHEN "01" => x <= b;     b         x
                                             mux
                WHEN "10” => x <= c;     c
                WHEN OTHERS => x <= d;   d
         END CASE;
   END PROCESS mux4_1;
END archdesign;
    Signal Assignment in Processes
 Inside processes, signals are not updated immediately.
  Instead, they are scheduled to be updated
 The signals are not actually updated until the END
  PROCESS statement is reached
 Therefore, on the previous slide, two registers will be
  synthesized (c <= b will be the old b)‫‏‬
 In some cases, the use of a concurrent statement outside
  the process will fix the problem, but this is not always
  possible
 So how else can we fix this problem ?
                     Variables
 When a concurrent signal assignment outside the
  process cannot be used, the previous problem can be
  avoided using a variable
    Variables are like signals, BUT they can only be
      used inside a PROCESS. They cannot be used to
      communicate information between processes
    Variables can be of any valid VHDL data type
    The value assigned to a variable is available
      immediately
    Assignment of variables is done using a colon (:),
      like this:
       c := a AND b;
      Using Variables vs. Signals

 Solution using a variable within a process:
-- assume a and c are signals defined elsewhere

ARCHITECTURE arch_reg OF reg IS
PROCESS
VARIABLE b: std_logic ;
BEGIN
    WAIT UNTIL clock = '1' ;
           b := a ; -- this is immediate
           c <= b ; -- this is scheduled
END PROCESS ;
END arch_reg;
                  Native Operators
 Logical - defined for type bit, bit_vector, boolean*
    AND, NAND
    OR, NOR
    XOR, XNOR
    NOT
 Relational - defined for types bit, bit_vector, integer*
    =       (equal to)‫‏‬
    /=      (not equal to)‫‏‬
    <       (less than)‫‏‬
    <=      (less than or equal to)‫‏‬
    >       (greater than)‫‏‬
    >=      (greater than or equal to)‫‏‬
 * overloaded for std_logic, std_logic_vector
          Native Operators (contd.)‫‏‬
 Unary Arithmetic - defined for type integer*
    -         (arithmetic negate)‫‏‬
 Arithmetic - defined for type integer*
    +         (addition), * (multiplication)‫‏‬
    -         (subtraction)‫‏‬
 Concatenation - defined for strings
    &
  Note, a STRING is any sequence of characters, therefore a
  std_logic_vector is an example of a STRING


 * overloaded for std_logic, std_logic_vector
          Overloaded Operators
 In VHDL, the scope of all of the previous operators
  can be extended (or overloaded) to accept any type
  supported by the language, e.g.,
   --   assume a declaration of a 16-bit vector as
        SIGNAL pc IS std_logic_vector(15 DOWNTO 0);
   --   then a valid signal assignment is
        pc <= pc + 3;
   --   assuming the '+' operator has been overloaded to -
   --   accept std_logic_vector and integer operands

 The std_logic_1164 package defines overloaded
  logical operators (AND, OR, NOT, etc.,) for the
  std_logic and std_logic_vector types
 In this training, you will learn to use overloaded
  operators, but not to define them
         Legal VHDL Identifiers
 Letters, digits, and underscores only (first character must
  be a letter)‫‏‬
 The last character cannot be an underscore
 Two underscores in succession are not allowed
 Using reserved words is not allowed (the VHDL editor
  will highlight reserved words for this reason)‫‏‬
 Examples
    Legal
        • tx_clk, Three_State_Enable, sel7D, HIT_1124
    Not Legal
        • _tx_clk, 8B10B, large#num, case, clk_
The Warp Design Environment
   Using the Project Wizard
   Entering Project Name / Path
   Adding Files to the Project
   Selecting a Device
   Opening up a File for Editing
   Additional Tools Review
      Describing the left hand files pane
      Overview of Pull down menus
      Reviewing On-line Help
     Using the Project Wizard
 Open Galaxy
 Using the <file> pull down menu, select <new>
 Select “Project - Target Device”, then <ok>
      Entering Project Name / Path
 In the Project Name dialog box, enter “exercise2”, then <ok>
 In the Project Path dialog box, browse to “C:\warp\class”,
  then select <next>
         Adding Files to the Project
 Highlight “ex2.vhd”, select <add> then <ok>
               Selecting a Device
 Double click on “Small PLDs”
 Select “22V10” on the left and “PALCE22V10-5JC” on the
  right, then hit <finish>, then <ok>
  Opening up a File for Editing
 In the left hand pane, double click on “ex2.vhd”.
  This will open the file up in the editor on the right
      Exercise #2: Architecture
     Declaration of a Comparator
 The entity declaration is as follows:
   LIBRARY ieee;                           a(3:0)‫‏‬
                                                          aeqb
   USE ieee.std_logic_1164.ALL;
                                           b(3:0)‫‏‬
   ENTITY compare IS PORT (
       a, b: IN std_logic_vector(3 DOWNTO 0);
       aeqb: OUT std_logic);
   END compare;


 Write an architecture that causes aeqb to be asserted
  when a is equal to b
 Multiple solutions exist
        Three possible solutions
 Concurrent statement solution using a conditional
  assignment:
   ARCHITECTURE arch_compare OF compare IS
   BEGIN
       aeqb <= '1' WHEN a = b ELSE '0';
   END arch_compare;

 Concurrent statement solution using boolean
  equations:
   ARCHITECTURE arch_compare OF compare IS
   BEGIN
       aeqb <= NOT(
           (a(0) XOR b(0)) OR
           (a(1) XOR b(1)) OR
           (a(2) XOR b(2)) OR
           (a(3) XOR b(3)));
   END arch_compare;
           Using Tri-State Logic
ENTITY test_three IS
      PORT( oe       :    IN std_logic;
             data    :    OUT std_logic_vector(0 to 7));
END test_three;
ARCHITECTURE archtest_three OF test_three IS
BEGIN
  PROCESS (oe)‫‏‬
  BEGIN
      IF (oe = '1')
        THEN data <= "01100100";
        ELSE data <= "ZZZZZZZZ";
      END IF;
  END PROCESS;
END archtest_three;
         Behavioral Don’t Cares

 Warp uses explicit "don’t care" conditions to
  produce optimal logic equations
       IF (a = '1') AND (b = '1') THEN
        x <= c;
       ELSE
        x <= '-';
       END IF;
 Produces the equation x = c
 To assign don’t cares in VHDL: mysig <= '-';
    'X' means "unknown" and is not useful for
      synthesis
     Comparing Vectors to Strings
        -more on don't cares-
   Comparing "1101" to "11-1" will return FALSE
   Use std_match(a,"string")‫‏‬
   Must include std_arith package
   Example:
...
signal a : std_logic_vector (1 to 4) ;
...
IF std_match(a,"10-1") THEN
     x <= '1' ;
END IF ;
     Additional Tools Review
 Describing the left hand files pane
    Source File Listing
    Design Hierarchy
    Output File Listing
 Pull down menus
    File, Edit, View, Format, Project, Compile,
       Templates, Bookmarks, Tools, Window, Help
 On-line Help
Source File Listing
 Click on the leftmost tab on the bottom of
  the left hand pane
 All source files for the current project
  will be displayed
 Double click on any file to open it up in
  the editor window on the right
 Hierarchy Listing
 Click on the centermost tab on the bottom
  of the left hand pane
 The project hierarchy will be displayed
Output File Listing
 Click on the rightmost tab on the bottom
  of the left hand pane
 All output files for the current project
  will be displayed
 Double click on any file to open it up in
  the editor window on the right
 By selecting a sub-heading within a file,
  the editor will go to that section
             Lower Status Windows
 The lower window pane of Galaxy displays the following
    Compiler - A line by line account of the entire compilation
      process. If an error is shown, you can jump into the proper
      file and line by double clicking on the error.
    Errors & Warnings - This tab only shows errors & warnings
    Search in files - Shows all occurrences generated by search
      in files     button
 Pull-down Menus
 Files Menu - Allows the opening or
  closing of files and projects, printing, and
  recalling of prior files and projects
 Pull-down Menus
 Edit Menu - Typical Cut, Copy and Paste
  commands as well as Find, Replace and
  Search all files. Additionally, the editor
  and project user preferences dialog box
  can be selected.
Output File Listing
           The Preferences screen
            allows the user to select
            editor options such as
            autosave, font size, tab
            spacing and highlighting.
            Additionally, project
            settings can be set up as
            well
 Pull-down Menus
 View Menu - Allows the user to select
  several viewing options such as viewing
  pane options and toolbars



 Format Menu - Allows block comment /
  un-comment as well as the setting of tabs
 Pull-down Menus
 Project Menu - Used to add and remove
  files from a project and perform library
  management. Additionally the user can
  select/change device types, set compiler
  options, set a project as the top level in a
  hierarchy as well as back annotate pins
  and nodes to a control file.
Compiler Options
        The Compiler options screen
         allows the user to choose
         generic attributes for his file
         such as area/speed and
         optimization effort, I/O
         voltage, slew rate and bus
         hold. Additionally
         technology mapping
         attributes can be set. Finally,
         the timing model output and
         test bench output formats can
         be selected.
 Pull-down Menus
 Compile Menu - Allows the user to compile
  the selected file or the entire project.

 Templates Menu - The user can browse
  through VHDL constructs or place LPM
  modules within his VHDL code.

 Bookmarks Menu - Allows the user to add
  and recall bookmarks within his files.

 Tools Menu - Launches the Jam Composer,
  Aldec Simulator and Aldec FSM Editor
 Pull-down Menus
 Window Menu - Allows positioning of
  files within the edit window as well as
  swapping between tabbed windows.



 Help Menu - Access to on-line help and
  device selector guide.
              Exercise #3: Instructions

 Create a new project using the Project Wizard
    Choose <file>, <new>, <Project - Target Device>
    Name your project exercise3, click <Next>
    Select the file ex3.vhd and <Add> it to the project
    To choose a device: In the left hand window, double click on
      the SPLD folder, then single click on the 22V10 folder. In the
      right hand window, select a PALCE22V10-5PC. Note that
      the details of the device are outlined below. Click <Finish>
    Double click on the ex3.vhd folder in the left hand window to
      open the file up into the editor window on the right.
      Exercise #3: Instructions (contd.)‫‏‬

 To designate that ex3.vhd is the top level design, either
  choose <Project> <Set Top> or hit the          shortcut button.
 Output an 1164/VHDL timing file by selecting <Project>
  <Compiler Options>. In the Simulation Timing Model box,
  select 1164/VHDL
 Modify the code in the editor window on the right to
  perform the function shown in the prior truth table.
    To compile your design, either choose <Compile>
       <Selected> or hit the       shortcut button.
    If an error appear in the lower window, double click on
       it to highlight the location of the error in the editor.
    Re-compile until all errors are gone
      Exercise #3: Instructions (contd.)‫‏‬

 Simulate the design using the Aldec simulator
    Select <Tools> <Active-HDL Sim>
    Select <File> <Open VHDL> and select
      c:\warp\class\vhd\ex3.vhd
    Select <File> <Open Waveform> and select
      c:\warp\class\wave_ex3.awf
    Assure the ‘Time To Run’ is 200ns
    Run the simulator <F5> or
    Review against output on the following page
 Reference the application note handout for additional details
Exercise #3: Aldec Simulator Waveform
           Exercise #3: The Solution
      The architecture is as follows:

ARCHITECTURE archex3 OF ex3 IS
BEGIN
  en(0) <= '0' WHEN (addr = "00" AND nvalid = '0') ELSE '1';
  en(1) <= (NOT addr(1)) AND addr(0) AND (NOT nvalid) ;
  en(2) <= '0' WHEN (addr = "10" AND nvalid = '0') ELSE '1';
  en(3) <= addr(1) AND addr(0) AND (NOT nvalid);
  dir <= '0' WHEN (addr = "00" AND nvalid = '0') OR
               (addr = "10" AND nvalid = '0') ELSE '1' ;
END archex3;
        Aggregates and Subscripts
 An aggregate assignment concatenates signals together
    Good for creating a bus from several inputs
 The concatenation operator can be used as well
    tmp <= (a,b,c,d);
    tmp <= a & b & c & d;
 Signals can be “pulled” from larger vectors
    Good for grouping outputs as an “alias”
 Sizes on both sides of assignment must match
    rw <= ctrl(0); ce <= ctrl(1); oe <= ctrl(2);
    highcount <= count(7 DOWNTO 4);
   Exercise #3: Alternate Solution
 Using With/Select and aggregates
   ARCHITECTURE archex3 OF ex3 IS
       SIGNAL control : std_logic_vector(2 DOWNTO 0);
       SIGNAL outputs : std_logic_vector(0 TO 4);
   BEGIN
       control <= addr & nvalid;
       WITH control SELECT
           outputs <= "00100" WHEN "000",
                      "10101" WHEN "001",
                      "11101" WHEN "010",
                      "10101" WHEN "011",
                      "10000" WHEN "100",
                      "10101" WHEN "101",
                      "10111" WHEN "110",
                      "10101" WHEN "111",
                      "-----" WHEN OTHERS;
       en <= outputs(0 TO 3);
       dir <= outputs(4);
   END archex3;
            Synchronous Logic

 PLDs work well in synchronous applications
 Two methods of creating synchronous logic
    Structurally
      • instantiating components with registers
    Behaviorally
      • Using a processes with a clock signal in the
         sensitivity list
     Registers in Behavioral VHDL
 Example: a D-type flip-flop
      ENTITY registered IS PORT (
                     d, clk: IN std_logic;
                     q:              OUT std_logic);
      END registered;
      ARCHITECTURE archregistered OF registered IS
      BEGIN
             flipflop: PROCESS (clk)‫‏‬
             BEGIN
                     IF rising_edge(clk)‫‏‬
                        THEN q <= d;
                     END IF;
             END PROCESS flipflop;
      END archregistered;
       Registers in Behavioral VHDL
 The synthesis compiler infers that a register is to be created
  for which signal q is the output because
    The clock (clk) is in the sensitivity list
    The construct, rising_edge(clk), falling_edge(clk) or
        clk’event AND clock=‘1’ appears in the process
 The rising_edge(clk) or falling_edge(clk) statement implies
  that subsequent signal assignments occur on the
  rising/falling edge of the clock
 The absence of an “else” clause in the “if-then” statement
  implies that if the clk’event and clk = ‘1’ condition is not
  fulfilled (i.e. not a rising-edge), q will retain its value until
  the next assignment occurs (this is referred to as implied
  memory)‫‏‬
       Rising/Falling Edge Functions

 The 1164 package defines 2 functions for edge detection
    rising_edge (signal)‫‏‬
       • similar to (signal’event and signal =‘1’)‫‏‬
    falling_edge (signal)‫‏‬
       • similar to (signal’event and signal =‘0’)

       if rising_edge(clk) then
                q <= d;
       end if;
        A Registered Process (3)‫‏‬
 A 4-bit loadable counter with asynchronous reset
        USE WORK.std_arith.ALL;
        ...                                data      count
        upcount: PROCESS (clk, reset)‫‏‬     load
                                             clk
        BEGIN
            IF reset = '1’                   rst
              THEN count <= x"0" ;
              ELSIF rising_edge(clk)
                THEN
                  IF load = '1'
                     THEN count <= data;
                     ELSE count <= count + 1;
                  END IF;
            END IF;
        END PROCESS upcount;
              Implicit memory
 Signals in VHDL have a current value and may be
  scheduled for a future value
 If the future value of a signal cannot be determined, a
  latch will be synthesized to preserve its current value
 Advantages:
    Simplifies the creation of memory in logic
       design
 Disadvantages:
    Can generate unwanted latches, e.g., when all of
       the options in a conditional sequential statement
       are not specified
     The rules to avoid implicit memory
 To avoid the generation of unexpected latches
    always terminate an IF...THEN... statement with an
      ELSE clause
    cover all alternatives in a CASE statement
       • define every alternative individually, or
       • terminate the CASE statement with a WHEN
          OTHERS... clause, e.g.,
           CASE coin_inserted IS
                     WHEN quarter =>   total<=total+25;
                     WHEN dime =>      total<=total+10;
                     WHEN nickel =>    total<=total+5;
                     WHEN OTHERS =>    total<=total;
                                          error<=‘1’;
           END CASE;
                     Exercise #4
 Making use of the previous examples, write an
  entity/architecture pair for the following design:

     ENC

                     COUNTER
     DATA
                 4
                     DIN
     LD                                               COUNT
                     LD      Q       4
                     ENC                 COMPARATOR
     CLOCK                               P
                       RST
 RESET (sync)‫‏‬                               P=Q
                                         Q
                      REGISTER
                     DIN
                             Q
     ENR                         4
                     ENR
             Exercise #4: Instructions
 Create a new project using the Project Wizard
    Choose <file>, <new>, <Project - Target Device>
    Name your project exercise4, click <Next>
    Select the file ex4.vhd and <Add> it to the project
    The target device is 32 Macrocell 8.5 ns CPLD in a 44 pin
      TQFP package. Choose CY7C371I-143AC
 Modify the code in the editor window on the right to perform the
  function shown in the prior diagram.
 Hints:
    Use 2 processes and a concurrent statement
    Use the register, counter, and comparator shown previously
    Incorporate count enable logic in count process
       Exercise #4: Instructions (contd.)‫‏‬
 To simulate your design with the Aldec Simulator, open the
  VHDL file C:\warp\class\vhd\ex4.vhd and then select
  <Simulation> <Initialize Simulation>
 Add all of the signals by selecting <Waveform> <Add
  Signals> (or using the shortcut     ). When the window
  opens, double click on each signal in the right hand box until
  all signals are added.
 Enter the stimulus found on the following page, reference the
  applications note handed out in class for additional details
       Exercise #4: Instructions (contd.)‫‏‬
 Add the following stimulus:
    reset <= formula 1 0, 0 20 ns, 1 300 ns
    clock <= clock of 100 MHz
    enr <= formula 0 0, 1 70 ns, 0 80 ns
    ld <= formula 0 0, 1 120 ns, 0 130 ns
    data <= 0000 0, 1100 50 ns, 16#3 100 ns, 16#0 150 ns
    enc <= formula 0 0, 1 160 ns
 After completing your design, back annotate the pin numbers
  by choosing <Project> <Annotate> and then <OK>. To view
  the back annotated pins, select <View> <Control File> from
  the pull down menu’s
          Exercise #4: Additional Help
 To get help on the format for adding stimulators (or any other
  topic), open up the stimulator dialog box and click on the
  question mark in the upper right corner ( ) then in the Enter
  Formula box.
Exercise #4: Aldec Simulator Waveform
        Exercise #4: Solution
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ex4 IS PORT (
    clock, reset, enc, enr, ld: IN std_logic;
    data:            IN std_logic_vector (3 DOWNTO 0);
    count:           BUFFER std_logic_vector(3 DOWNTO 0));
END ex4;
USE WORK.std_arith.ALL; -- for counter and Ultragen
ARCHITECTURE archex4 OF ex4 IS
    SIGNAL comp: std_logic;
    SIGNAL regout: std_logic_vector (3 DOWNTO 0);
BEGIN
    reg: PROCESS (clock)‫‏‬
    BEGIN
        IF RISING_EDGE(clock)
          THEN
            IF enr = '1' THEN
               regout <= data;
            END IF;
        END IF;
    END PROCESS reg;
 Exercise #4: Solution (contd.)‫‏‬
    cntr: PROCESS (clock)‫‏‬
    BEGIN
        IF RISING_EDGE(clock) THEN
            IF reset = '1'
              THEN count <= "0000";
              ELSIF ld = '1'
                THEN count <= data;
              ELSIF enc = '1' AND comp = '0'
                THEN count <= count + 1;
            END IF;
        END IF;
    END PROCESS cntr;
    comp <= '1' WHEN regout = count ELSE '0';
END archex4;
           Exercise #4: Control File
Ex4.ctl:

Attribute   PIN_NUMBERS   of   count(1) is "37" ;
Attribute   PIN_NUMBERS   of   count(2) is "30" ;
Attribute   PIN_NUMBERS   of   data(2) is "29" ;
Attribute   PIN_NUMBERS   of   data(1) is "27" ;
Attribute   PIN_NUMBERS   of   data(0) is "26" ;
Attribute   PIN_NUMBERS   of   count(3) is "25" ;
Attribute   PIN_NUMBERS   of   count(0) is "18" ;
Attribute   PIN_NUMBERS   of   data(3) is "15" ;
Attribute   PIN_NUMBERS   of   ld is "14" ;
Attribute   PIN_NUMBERS   of   enc is "13" ;
Attribute   PIN_NUMBERS   of   reset is "12" ;
Attribute   PIN_NUMBERS   of   clock is "7" ;
Attribute   PIN_NUMBERS   of   enr is "4" ;
               State machines

 Moore Machines
   A finite state machine in which the outputs
     change due to a change of state

 Mealy Machines
   A finite state machine in which the outputs can
     change asynchronously i.e., an input can cause
     an output to change immediately
              Moore machines

 Outputs may change only with a change of state
 Multiple implementations include:
    Arbitrary state assignment
       • outputs must be decoded from the state bits
           • combinatorial decode
           • registered decode
    Specific state assignment
       • outputs may be encoded within the state bits
       • one-hot encoding
        Example: The Entity Declaration

 The entity declaration remains exactly the same for each
  implementation.
 For example:
       LIBRARY ieee;
       USE ieee.std_logic_1164.ALL;
       ENTITY state_machine IS PORT (
              clock, reset:             IN std_logic;
              timer1, timer2, timer3:    IN std_logic;
              r, y, g:                         OUT std_logic);
       END state_machine;
               Example: Solution 1
   Combinatorial outputs decoded from the state registers
ARCHITECTURE arch_1 OF state_machine IS
 TYPE traffic_states IS (red, yellow, green); -- enumerated type
 SIGNAL sm: traffic_states;
BEGIN
fsm: PROCESS (clock, reset) -- the process describes the
  BEGIN                     -- state machine only
     IF reset = '1' THEN
        sm <= red;
     ELSIF rising_edge(clock) THEN
       CASE sm IS
           WHEN red => IF timer1=‘1’
                           THEN sm <= green;
                           ELSE sm <= red;
                         END IF;

          WHEN green => IF timer2=’1'
                          THEN sm <= yellow;
                          ELSE sm <= green;
                        END IF;
    Example: Solution 1 (contd.)‫‏‬
    WHEN yellow =>   IF timer3=’1’
                       THEN sm <= red;
                       ELSE sm <= yellow;
                     END IF;
     WHEN others => sm <= red;
   END CASE;
 END IF;
END PROCESS fsm;

-- the outputs are decoded from the state machine
-- registers using combinatorial logic
r <= '1' WHEN (sm = red) ELSE '0';
g <= '1' WHEN (sm = green) ELSE '0';
y <= '1' WHEN (sm = yellow) ELSE '0';

END arch_1;
                   Example: Solution 2
   Registered outputs decoded from the state registers
ARCHITECTURE arch_2 OF state_machine IS
 TYPE traffic_states IS (red, yellow, green);
 SIGNAL sm: traffic_states;
BEGIN
fsm: PROCESS (clock, reset) -- the process describes the
  BEGIN                      -- state machine AND the outputs
     IF reset = '1' THEN
        sm <= red;
        r<=‘1’; g<=‘0’; y<=‘0’;
     ELSIF rising_edge(clock) THEN
       CASE sm IS
           WHEN red => IF timer1=‘1’
                          THEN sm <= green;
                                r<=‘0’; g<=‘1’; y=‘0’;
                          ELSE sm <= red;
                                r<=‘1’; g<=‘0’; y=‘0’;
                        END IF;
               Example: Solution 2 (contd.)‫‏‬
              WHEN green =>   IF timer2=’1'
                                THEN sm <= yellow;
                                      r<=‘0’; g<=‘0’; y<=‘1’;
                                ELSE sm <= green;
                                      r<=‘0’; g<=‘1’; y<=‘0’;
                              END IF;
              WHEN yellow => IF timer3=’1'
                               THEN sm <= red;
                                    r<=‘1’; g<=‘0’; y<=‘0’;
                               ELSE sm <= yellow;
                                    r<=‘0’; g<=‘0’; y<=‘1’;
                             END IF;
              WHEN others => sm <= red;
     END CASE;
   END IF;
  END PROCESS fsm;

END arch_2;
                  Example: Solution 3
     Outputs encoded inside the state registers
ARCHITECTURE arch_3 OF state_machine IS
  SIGNAL     sm:       std_logic_vector(2   DOWNTO   0)   ;
  CONSTANT   red:      std_logic_vector(2   DOWNTO   0)   := ”100" ;
  CONSTANT   green:    std_logic_vector(2   DOWNTO   0)   := "010" ;
  CONSTANT   yellow:   std_logic_vector(2   DOWNTO   0)   := "001" ;
BEGIN
 fsm: PROCESS (clock, reset) -- the process describes the
          BEGIN                     -- state machine only
                 IF reset = '1' THEN
                          sm <= red;
       ELSIF rising_edge(clock) THEN
                         CASE sm IS
                             WHEN red => IF timer1=‘1’
                                            THEN sm <= green;
                                            ELSE sm <= red;
                                          END IF;
     Example: Solution 3 (contd.)‫‏‬
       WHEN green =>   IF timer2=’1'
                             THEN sm <= yellow;
                             ELSE sm <= green;
                           END IF;

          WHEN yellow => IF timer3=’1’
                             THEN sm <= red;
                      ELSE sm <= yellow;
                       END IF;
       WHEN others => sm <= red;
     END CASE;
   END IF;
  END PROCESS fsm;

r <= sm(2);   -- the outputs are just taken from
g <= sm(1);   -- the state machine registers
y <= sm(0);   -- (no decode logic required)‫‏‬

END arch_3;
 State Machines: One-hot Encoding
 One state per flip-flop
    in FPGA-type architectures
       • reduces the next state logic
       • requires fewer levels of logic cells
       • enables high-speed state machines (> 100MHz)‫‏‬
    in CPLDs
       • reduces the number of product terms
       • can eliminate ‘expander’ product terms (i.e.
          reduce delays, and increase operating speed)‫‏‬
       • but, uses more macrocells
        Example: One-hot-one Solution
   Combinatorial outputs decoded from the state registers
ARCHITECTURE arch_1 OF state_machine IS
 TYPE traffic_states IS (red, yellow, green); -- enumerated type
 SIGNAL sm: traffic_states;
 ATTRIBUTE state_encoding OF traffic_states: TYPE IS one_hot_one;
BEGIN
fsm: PROCESS (clock, reset) -- the process describes the
  BEGIN                     -- state machine only
     IF reset = '1' THEN
        sm <= red;
     ELSIF rising_edge(clock) THEN
       CASE sm IS
           WHEN red => IF timer1=‘1’
                           THEN sm <= green;
                           ELSE sm <= red;
                         END IF;

          WHEN green => IF timer2=’1'
                          THEN sm <= yellow;
                          ELSE sm <= green;
                        END IF;
Example: One-hot-one Solution (contd.)‫‏‬
        WHEN yellow => IF timer3=’1'
                         THEN sm <= red;
                         ELSE sm <= yellow;
                       END IF;
        WHEN others => sm <= red;
      END CASE;
    END IF;
   END PROCESS fsm;

   -- the outputs are decoded from the state machine
   -- registers using combinatorial logic
   r <= '1' WHEN (sm = red) ELSE '0';
   g <= '1' WHEN (sm = green) ELSE '0';
   y <= '1' WHEN (sm = yellow) ELSE '0';

   END arch_1;
State Machine Encoding: Example
        State Sequential   One-hot-one
         S0     000          000001
         S1     001          000010
         S2     010          000100
         S3     011          001000
         S4     100          010000
         S5     101          100000

   S3 State Logic
      Sequential - enable * /b2 * b1 * b0
      One-hot-one - enable * b3
     Moore Machines: Summary
 Outputs decoded from the state bits
       • flexibility during the design process
       • using enumerated types allows automatic
          state assignment during compilation
 Outputs encoded within the state bits
       • manual state assignment using constants
       • the state registers and the outputs are merged
       • reduces the number of registers
       • but, may require more product terms
 One-Hot encoding
       • reduces next state decode logic
       • high speed operation
       • but, uses more registers
      Example: Mealy Machine Solution
ARCHITECTURE archmealy1 OF mealy1 IS
  TYPE fsm_states IS (idle, retry);
  SIGNAL wait_gen: fsm_states;
BEGIN
  fsm: PROCESS (clock, reset)‫‏‬
  BEGIN
    IF reset = '1' THEN
        wait_gen <= idle;
    ELSIF FALLING_EDGE(clock) THEN
        CASE wait_gen IS
          WHEN idle     =>     IF req = '0'    THEN wait_gen <=
    retry;
                        ELSE wait_gen <= idle;
                END IF;
          WHEN retry    =>     IF pwait = '1' THEN wait_gen <= idle;
                        ELSE wait_gen <= retry;
                END IF;
          WHEN OTHERS   =>     wait_gen <= idle;
        END CASE;
    END IF;
  END PROCESS fsm;
  retry_out <= '1' WHEN (wait_gen = retry AND enable='0') ELSE '0';
END archmealy1;
            Exercise #5: Instructions
 Using the Project Wizard create a new project named exercise5
  and add the template ex5.vhd
 The target device is 32 Macrocell 10 ns CPLD in a 44 pin PLCC
  package. Choose CY7C371I-110JC
    Use automatic state bit assignment using an enumerated type
 Compile and synthesize your design using Warp
    Check the report file for the number of macrocells used.
    What is the clock-to-output time (tco)?
 Change your state machine to use constants as follows:
    hold=“10” sample=“01” extend=“11”
 Re-compile your design and check the report file again
    How many macrocells are utilized now ? What is the tco?
       Exercise #5: Instructions (contd.)‫‏‬
 To simulate your design with the Aldec Simulator, open the
  VHDL file C:\warp\class\vhd\ex5.vhd and then select
  <Simulation> <Initialize Simulation>
 Add all of the signals by selecting <Waveform> <Add
  Signals> (or using the shortcut     ). When the window
  opens, double click on each signal in the right hand box until
  all signals are added.
 Select the ‘clock’ signal with the <left mouse> button. Now
  depress the <right mouse> button and select <Stimulators>.
  Choose <Clock> from the stimulator type pull down menu, set
  the frequency to 50MHz and then depress <apply>.
       Exercise #5: Instructions (contd.)‫‏‬
 Select the ‘reset’ signal with the <left mouse> button. Now
  choose <Waveform> <Edit Mode> (or using the shortcut        ).
  Move the mouse pointer to <0ns> then hold down the <left
  mouse> button and drag to the <300ns> mark (section will
  highlight). Depress the <1> key. Select <50ns> to <250ns>
  and depress the <0> key. Select the ‘reset’ signal with the
  <left mouse> button. Now depress the <right mouse> button
  and select <Stimulators>. Choose <Custom> from the
  stimulator type pull down menu, then depress <apply>.
 Repeat the above for the ‘pos’ signal, making it high from
  <0ns> to <100ns>, low from <100ns> to <120ns> then high
  from <120ns> to <300ns>. Remember to set to <Custom>
 Run the simulator for 300ns
       Exercise #5: Instructions (contd.)‫‏‬
 If you are having a problem drawing waveforms, assure that
  the simulator is not running. To stop the simulation, choose
  <End Simulation> from the <Simulation> pull down menu.
 If you are having problems saving the waveforms that you
  have drawn in by hand, assure that the the letters ‘Cs’ are in
  the stimulator column of the waveform view. If a ‘Cs’ is not
  displayed it is because the <Apply> button was not depressed
  after setting the signal to a <Custom> stimulator type.
 After loading a new waveform it is best to reset the simulator
  by choosing <Initialize Simulator> from the <Simulation>
  pull down menu.
 Verify that your waveform is similar to the view on the
  following page.
Exercise #5: Aldec Simulator Waveform
           Exercise #5: Solution A
           Using an Enumerated Type
     Macrocells = 3, Tco2 (Tco + Tpd) = 10.5ns
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ex5 IS PORT (
    clock, pos,
    reset:            IN std_logic;
    clear, track:     OUT std_logic);
END ex5;

ARCHITECTURE archex5 OF ex5 IS
    TYPE states IS (hold, sample, extend);
    SIGNAL fsm: states;
BEGIN
    clear <= '0' WHEN fsm=sample ELSE '1';
    track <= '1' WHEN (fsm=extend or fsm=sample) ELSE '0';
      Exercise #5: Solution A (contd.)‫‏‬
  sync: PROCESS (clock)‫‏‬
  BEGIN
    IF rising_edge(clock) THEN
        IF reset = '1' THEN   -- synchronous reset
                fsm <= hold;
        ELSE
                CASE fsm IS
                       WHEN hold =>   IF pos = '0'
                                THEN fsm <= sample;
                                ELSE fsm <= hold;
                              END IF;
                       WHEN sample => fsm <= extend;
                       WHEN extend => fsm <= hold;
                       WHEN OTHERS => fsm <= hold;
                END CASE;
        END IF;
    END IF;
  END PROCESS sync;
END archex5;
               Exercise #5: Solution B
     Using Constants - Macrocells = 2, Tco = 6.0ns
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ex5 IS PORT (
    clock, pos,
    reset:         IN std_logic;
    clear, track: OUT std_logic);
END ex5;

ARCHITECTURE   archex5 OF ex5 IS
    SIGNAL     fsm    : std_logic_vector(1   downto   0);
    CONSTANT   hold   : std_logic_vector(1   downto   0) := “10”;
    CONSTANT   sample : std_logic_vector(1   downto   0) := “01”;
    CONSTANT   extend : std_logic_vector(1   downto   0) := “11”;
BEGIN
    clear <=   fsm(1);
    track <=   fsm(0);
      Exercise #5: Solution B (contd.)‫‏‬
  sync: PROCESS (clock)‫‏‬
  BEGIN
    IF rising_edge(clock) THEN
        IF reset = '1' THEN   -- synchronous reset
                fsm <= hold;
        ELSE
                CASE fsm IS
                       WHEN hold =>   IF pos = '0'
                                THEN fsm <= sample;
                                ELSE fsm <= hold;
                              END IF;
                       WHEN sample => fsm <= extend;
                       WHEN extend => fsm <= hold;
                       WHEN OTHERS => fsm <= hold;
                END CASE;
        END IF;
    END IF;
  END PROCESS sync;
END archex5;
   Hierarchical (Modular) Designs

 A hierarchical design is one which is broken down
  into many levels, with a top level design bringing all
  the lower-level components together

 This allows very complex designs to be divided
  down into smaller, more easily managed modules

 In the past, this was the major advantage of
  schematic capture tools

 But, VHDL also supports hierarchical designs !!
   Hierarchical Design Methodology
 Advantages:
    Components (VHDL models) can be created, tested
     and stored for later use
    Allows the re-use of common building blocks
    Allows you to purchase 3rd Party off-the-shelf
     modules (e.g. UART, PCIbus Interface etc)‫‏‬
    Makes the design more readable and easier to
     understand
    Complex design tasks can be split across many
     designers in a team
     VHDL Hierarchy Decomposition
 In VHDL, hierarchy is composed of:
     COMPONENTs
       • entity/architecture pairs which can be
         instantiated (placed) within other designs
     PACKAGEs
       • a collection of one or more COMPONENTs
         and other declarations
     LIBRARIES
       • a collection of COMPILED design units
       • e.g. packages, components, entity/architecture
         pairs etc.
                            Hierarchy Management
       Libraries are used to store re-usable components, type definitions,
          overloaded operators etc. You add the ‘LIBRARY’ and ‘USE’
          clauses to your code to get access to them
 Your Design (VHDL)‫‏‬          Library (Compiled)‫ ‏‬Packages (VHDL)‫‏‬   Others (VHDL)‫‏‬
LIBRARY ieee;                 ieee
                                                   std_logic_1164        std_logic
USE ieee.std_logic_1164..
                                                                         type
USE work.std_arith.all
                                                                         definitions



                              Library (Compiled)‫ ‏‬Packages (VHDL)‫‏‬   Others (VHDL)‫‏‬
                              work
                                                   std_arith            overloaded
                                                                        operators
             Package and Component
             Declarations: An Example
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mymuxpkg IS
    COMPONENT mux2to1 PORT (
      a, b, sel: IN std_logic;
                                         Package and Component
      c:          OUT std_logic);        Declaration File
    END COMPONENT;
END mymuxpkg;
                                         (VHDL)‫‏‬
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux2to1 IS PORT (
  a, b, sel: IN std_logic;
  c:          OUT std_logic);
END mux2to1;
                                          Entity/Architecture
ARCHITECTURE archmux2to1 OF mux2to1 IS    File (VHDL)‫‏‬
BEGIN
  c <= (a AND NOT sel) OR (b AND sel);
END archmux2to1;
                         Exercise #6
 Making use of exercise #4, we will use a separate
  entity/architecture for each block and use VHDL hierarchy

         ENC

                         COUNTER
         DATA
                     4
                         DIN
         LD                                               COUNT
                         LD      Q       4
                         ENC                 COMPARATOR
         CLOCK                               P
                           RST
     RESET (sync)‫‏‬                               P=Q
                                             Q
                          REGISTER
                         DIN
                                 Q
         ENR                         4
                         ENR
             Exercise #6 : Instructions
 Write a hierarchical VHDL description of the previous
  schematic which instantiates all of the components shown in
  the design
    The entity/architecture is given for all 3 components
        • count4.vhd, reg4.vhd, comp4.vhd
    Complete the package which has the component
       declarations for all 3 components
        • package.vhd
    Complete the top level file which instantiates the 3
       components and makes the interconnections
        • ex6.vhd
              Exercise #6: Instructions
 Using the Project Wizard create a new project named exercise6
  and add the templates count4.vhd, reg4.vhd, comp4.vhd,
  package.vhd and ex6.vhd in THE ORDER shown
 The target device is 256 Macrocell 7.5 ns CPLD in a 160 pin
  TQFP package. Choose CY7C37256P160-154AC
 Highlight the top-level (lowermost) file (ex6.vhd) and Click-on
  the Set top button
 Highlight the top 3 files (one at a time) and Click-on the Compile
  selected button
 Before compiling package.vhd and ex6.vhd, you must complete
  the files.
 Once all of the files have been compiled separately, use the
  Compile Project        button for subsequent compiles
  Exercise 6 Solution: package.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE ex6_pkg IS

 COMPONENT comp4 PORT (
   p, q : IN std_logic_vector (3 DOWNTO 0);
   peqq : OUT std_logic);
 END COMPONENT;

 COMPONENT reg4 PORT (
   clk, enr : IN std_logic;
   din      : IN std_logic_vector(3 DOWNTO 0);
   q        : OUT std_logic_vector(3 DOWNTO 0));
 END COMPONENT;
Exercise 6 Solution: package.vhd (cont)‫‏‬


 COMPONENT count4 PORT(
   clk, enc, ld, rst : IN     std_logic;
   din               : IN     std_logic_vector(3 downto 0);
   q                 : BUFFER std_logic_vector(3 downto 0));
 END COMPONENT;

END ex6_pkg;
Exercise 6 Solution: Top Level File - ex6.vhd
  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;

  ENTITY ex6 IS PORT (
    load, clock, reset : IN       std_logic;
    enr, enc     : IN     std_logic;
    data : IN      std_logic_vector(3 downto 0);
    count : BUFFER std_logic_vector(3 downto 0));
  END ex6;

  USE work.ex6_pkg.ALL;              -- get access to your components
  ARCHITECTURE ex6_arch OF ex6 IS

    SIGNAL regout   : std_logic_vector(3 downto 0);   -- internal bus
    SIGNAL peqq     : std_logic;                      -- internal net
    SIGNAL not_peqq : std_logic;                      -- internal net
Exercise 6 Solution :Top Level File - ex6.vhd

  BEGIN

     U1: count4 PORT MAP (din=>data, ld=>load, enc=>not_peqq,
                          clk=>clock, rst=>reset, q=>count);

     U2: reg4 PORT MAP (din=>data, enr=>enr, clk=>clock,
                        q=>regout);

     U3: comp4 PORT MAP (p=>count, q=>regout, peqq=>peqq);

     not_peqq <= enc AND NOT(peqq);   -- create the inverter

  END ex6_arch;
            The GENERATE statement
     Used to specify repetitive or conditional execution of
      a set of concurrent statements
     Useful for instantiating arrays of components
USE WORK.rtlpkg.ALL; -- User-defined package containing dsrff
ENTITY sipo IS PORT (
    clk, reset: IN std_logic;
    si:         IN std_logic;
    po:         BUFFER std_logic_vector(31 DOWNTO 0));
END sipo;

ARCHITECTURE arch_sipo OF sipo IS
SIGNAL p_temp: std_logic_vector(31 DOWNTO 0);
SIGNAL zero: std_logic := ‘0’;
BEGIN
    gen: FOR i IN 0 TO 30 GENERATE
        nxt: dsrff PORT MAP (p_temp(i+1), zero, reset, clk, p_temp(i));
    END GENERATE;
    beg: dsrff PORT MAP (si, zero, reset, clk, p_temp(31));
    po <= p_temp;
END arch_sipo;
LIBRARY ieee ;
                  Multiplexing I/O pins:
USE ieee.std_logic_1164.ALL;
USE WORK.std_arith.all ;
ENTITY ldcnt IS PORT (
           clk, ld, oe: IN std_logic;
           count:        INOUT std_logic_vector(7 DOWNTO 0));
END ldcnt;
ARCHITECTURE archldcnt OF ldcnt IS
    SIGNAL int_count: std_logic_vector(7 DOWNTO 0);
BEGIN
    cnt: PROCESS (clk)‫‏‬
    BEGIN
           IF RISING_EDGE(clock) THEN
                   IF ld = '1' THEN int_count <= count; -- count as
    "IN"
                                   ELSE int_count <= int_count + 1;
                   END IF;
           END IF;
    END PROCESS cnt ;
    outen: PROCESS (oe, int_count) BEGIN
           IF oe = '1’ THEN count <= int_count ; -- count as "OUT"
                                ELSE count <= (OTHERS => 'Z') ;--
    count as "OUT"
           END IF ;           -- equivalent to count <=
    "ZZZZZZZZ"
    END PROCESS outen;
END archldcnt;
                     Exercise #7
 Design a Moore Machine to implement the Output Enable
  Controller shown below:

        68040            DRAM BANK A     DRAM BANK B




                         DRAM BANK C     DRAM BANK D




                             Output
                                            DRAM
                             Enable
                                           Controller
                            Controller
         Exercise #7: The FSM chart
 Use the following FSM chart:
                        RM
                         A                              EE
                                                       RST

                                      L
                                    ID E

                                    E 11
                                   O = 11


                                             A
                                           /R M




                                    H OE
                                   C O S

                                    E 11
                                   O = 11


                                                                         O
                                                                       /E C

        3 N
      /A A D/A2           3 N 2
                        /A A DA    A A D/A
                                    3 N   2                  3 N 2
                                                            A A DA




      BN A
       A K        E C
                   O     A K
                         BN B       E C
                                     O         A K
                                              BN C     O
                                                      E C     BN D
                                                               A K

       E 11
      O =10               O =1 1
                           E10                 E11
                                              O =01            E01
                                                              O = 11

                                                         O
                                                        E C
           Exercise #7: Instructions
   The target device is a CY7C371I-143JC
   Use a synchronous reset
   Decode the outputs in parallel with the next state
   Compile and synthesize your design using Warp
   Determine the maximum frequency of operation
    using the report file
                Exercise #7: Solution
ENTITY ex7 IS PORT (
    clk, reset: IN std_logic;
    ram, eoc:   IN std_logic;
    a3a2:       IN std_logic_vector(1 DOWNTO 0) ;
    oe:         OUT std_logic_vector(3 DOWNTO 0));
END ex7;


ARCHITECTURE archex7 OF ex7 IS

   TYPE oe_states IS (idle, choose, banka, bankb, bankc, bankd);
   ATTRIBUTE state_encoding OF oe_states : TYPE IS gray ;
   SIGNAL present_state, next_state : oe_states ;
   SIGNAL oe_out : std_logic_vector(3 DOWNTO 0) ;

BEGIN
                    Exercise #7: Solution (contd.)‫‏‬
fsm: PROCESS (clk)‫‏‬
BEGIN
  IF RISING_EDGE(clock) THEN
          IF reset = '1' THEN
                 next_state <= idle;
          ELSE
                 CASE present_state IS
                         WHEN idle => IF ram = '0'
                                        THEN next_state <= choose ;
                                        ELSE next_state <= idle ;
                                      END IF ;
                         WHEN choose =>
                                CASE a3a2 IS
                                        WHEN "00" => next_state <= banka ;
                                        WHEN "01" => next_state <= bankb ;
                                        WHEN "10" => next_state <= bankc ;
                                        WHEN "11" => next_state <= bankd ;
                                        WHEN OTHERS => next_state <= banka ;
                                END CASE ;
                         WHEN banka => IF eoc = '1'
                                         THEN next_state <= bankb ;
                                         ELSE next_state <= idle ;
                                        END IF ;
                  Exercise #7: Solution (contd.)‫‏‬


                      WHEN bankb => IF eoc = '1'
                                      THEN next_state <=   bankc ;
                                      ELSE next_state <=   idle ;
                                    END IF ;
                      WHEN bankc => IF eoc = '1'
                                      THEN next_state <=   bankd ;
                                      ELSE next_state <=   idle ;
                                    END IF ;
                      WHEN bankd => IF eoc = '1'
                                      THEN next_state <=   banka ;
                                      ELSE next_state <=   idle ;
                                    END IF ;
                      WHEN OTHERS => next_state <= idle;
               END CASE;
       END IF ;
  END IF;
END PROCESS fsm;
    Exercise #7: Solution (contd).
output_logic: PROCESS (next_state)‫‏‬
BEGIN
    CASE next_state IS
        WHEN idle => oe_out <= "1111" ;
        WHEN choose => oe_out <= "1111" ;
        WHEN banka => oe_out <= "1110" ;
        WHEN bankb => oe_out <= "1101" ;
        WHEN bankc => oe_out <= "1011" ;
        WHEN bankd => oe_out <= "0111" ;
        WHEN OTHERS => oe_out <= "1111" ;
    END CASE;
END PROCESS output_logic ;

advance_state: PROCESS (clk)‫‏‬
BEGIN
    IF RISING_EDGE(clock)
      THEN present_state <= next_state ;
           oe <= oe_out ;
    END IF;
END PROCESS ;

END archex7;
   VHDL User-defined Attributes

 VHDL construct which is used to provide information
  about VHDL objects such as entities, architectures,
  types, and signals.
    Warp user-defined attributes are used as synthesis
      directives to the compiler. These include:
        • state_encoding
        • enum_encoding
        • pin_numbers
        • synthesis_off
     The state_encoding attribute

 This is used to specify the state encoding scheme of the FSMs
  in a VHDL file.
 The default scheme for CPLDs is sequential.
 Other schemes such as one_hot_one, one_hot_zero and gray
  encodings are available.

TYPE state_type IS (idle,state1,state2,state3);
ATTRIBUTE state_encoding OF state_type: TYPE IS sequential;
      The enum_encoding Attribute

 Used to specify the exact internal encoding to be use for
  each value of a user-defined enumerated type.
 Overrides state_encoding in same description.


TYPE states IS (idle,state1,state2,state3);
ATTRIBUTE enum_encoding OF states: TYPE IS "11 01 00 10";
    The pin_numbers attribute

 Used to map the external signals of an entity to the
  pins on the target device
    Allows the back-annotation of pin placements
       after synthesis, e.g.,
   LIBRARY ieee;
   USE ieee.std_logic_1164.ALL;
   ENTITY counter IS PORT (
       clock, reset: IN std_logic;
       count:        OUT std_logic_vector(3 DOWNTO 0)‫‏‬
       );
       ATTRIBUTE pin_numbers OF counter:ENTITY IS
       "clock:13 reset:2" &
       " count(3):3 count(2):4 count(1):5 count(0):6";
   END counter;
  The synthesis_off attribute

 Controls the flattening and factoring of signals
    Makes the signal a factoring point
 Useful when a signal with a large number of product
  terms is used in other equations
    Helpful in cases where substitution causes
      unacceptable compile time (due to exponentially
      increasing CPU and memory requirements)‫‏‬
    Achieves more efficient implementation
 Should only be used on combinatorial equations
    Registered equations are natural factoring points
      Without synthesis_off
 An implementation (without synthesis_off)‫‏‬
   LIBRARY ieee;
   USE ieee.std_logic_1164.ALL;
   ENTITY mux IS PORT (
       a, b: IN std_logic_vector(3 DOWNTO 0);
       c, d: IN std_logic_vector(7 DOWNTO 0);
       x:    OUT std_logic_vector(3 DOWNTO 0));
   END mux;

   ARCHITECTURE archmux OF mux IS
   BEGIN
       x <= a WHEN (c = d) ELSE b;
   END archmux;

 Resources used: 1092 product terms, 68 sum splits,
  72 macrocells - the comparison is not done on a bit
  by bit basis
        Comparison: with a 4-bit vector
S_2 =
  b * c_0 * /d_0 + b * /c_3 * d_3 + b * c_3 * /d_3 + b * /c_2 * d_2
+ b * c_2 * /d_2 + b * /c_1 * d_1 + b * c_1 * /d_1 + b * /c_0 * d_0
S_1 =
   a * c_3 * c_2 * c_1 * /c_0 * d_3 * d_2 * d_1 * /d_0
 + a * /c_3 * c_2 * c_1 * /c_0 * /d_3 * d_2 * d_1 * /d_0
 + a * c_3 * /c_2 * c_1 * /c_0 * d_3 * /d_2 * d_1 * /d_0
 + a * /c_3 * /c_2 * c_1 * /c_0 * /d_3 * /d_2 * d_1 * /d_0
 + a * c_3 * c_2 * /c_1 * /c_0 * d_3 * d_2 * /d_1 * /d_0
 + a * /c_3 * c_2 * /c_1 * /c_0 * /d_3 * d_2 * /d_1 * /d_0
 + a * c_3 * /c_2 * /c_1 * /c_0 * d_3 * /d_2 * /d_1 * /d_0
 + a * /c_3 * /c_2 * /c_1 * /c_0 * /d_3 * /d_2 * /d_1 * /d_0
 + a * c_3 * c_2 * c_1 * c_0 * d_3 * d_2 * d_1 * d_0
 + a * /c_3 * c_2 * c_1 * c_0 * /d_3 * d_2 * d_1 * d_0
 + a * c_3 * /c_2 * c_1 * c_0 * d_3 * /d_2 * d_1 * d_0
 + a * /c_3 * /c_2 * c_1 * c_0 * /d_3 * /d_2 * d_1 * d_0
 + a * c_3 * c_2 * /c_1 * c_0 * d_3 * d_2 * /d_1 * d_0
 + a * /c_3 * c_2 * /c_1 * c_0 * /d_3 * d_2 * /d_1 * d_0
 + a * c_3 * /c_2 * /c_1 * c_0 * d_3 * /d_2 * /d_1 * d_0
 + a * /c_3 * /c_2 * /c_1 * c_0 * /d_3 * /d_2 * /d_1 * d_0
 /x0 =
   /S_1.CMB * /S_2.CMB
         With synthesis_off
 A better implementation (with synthesis_off)‫‏‬
   LIBRARY ieee;
   USE ieee.std_logic_1164.ALL;
   ENTITY mux IS PORT (
       a, b: IN std_logic_vector(3 DOWNTO 0);
       c, d: IN std_logic_vector(7 DOWNTO 0);
       x:    OUT std_logic_vector(3 DOWNTO 0));
   END mux;

   ARCHITECTURE archmux OF mux   IS
       SIGNAL sel: std_logic;
       ATTRIBUTE synthesis_off   OF sel:SIGNAL is TRUE;
   BEGIN
       sel <= '1' WHEN (c = d)   ELSE '0';
       x <= a WHEN (sel = '1')   ELSE b;
   END archmux;
 Resources used: 24 product terms, 1 partial result, 5
  macrocells
Results with synthesis_off
DESIGN EQUATIONS

x_3 = b_3 * /sel.CMB + a_3 * sel.CMB

x_2 = /sel.CMB * b_2 + sel.CMB * a_2

x_1 = /sel.CMB * b_1 + sel.CMB * a_1

x_0 = /sel.CMB * b_0 + sel.CMB * a_0

/sel =   c_0   *   /d_0   +   /c_0   *   d_0   +   c_1   *   /d_1   +   /c_1   *   d_1
     +   c_2   *   /d_2   +   /c_2   *   d_2   +   c_3   *   /d_3   +   /c_3   *   d_3
     +   c_4   *   /d_4   +   /c_4   *   d_4   +   c_5   *   /d_5   +   /c_5   *   d_5
     +   c_6   *   /d_6   +   /c_6   *   d_6   +   c_7   *   /d_7   +   /c_7   *   d_7
      CPLD Synthesis Directives
 Some Warp synthesis directives only apply to CPLD
  architectures, e.g.,
    Floor planning
        • lab_force
        • node_num
        • pin_avoid
    Product Term distribution
        • sum_split
    Speed/Power/Edge rates
        • slew_rate
        • low_power
         The lab_force Attribute

 Forces signals into specific logic blocks in CPLDs
 Should be used sparingly as it restricts the fitter
 First example below forces signal to upper half of
  logic block A.
 Second example forces signal to lower half of logic
  block B


ATTRIBUTE lab_force OF mysig1: SIGNAL IS A1;
ATTRIBUTE lab_force OF mysig2: SIGNAL IS B2;
          The node_num Attribute

 Used to specify internal location for a signal in a CPLD
    Allows signals to be manually allocated to a
      specific macrocell location
    May be used to improve product-term allocation
       • Example: to assign a signal to the first buried
          macrocell in a CY7C372:
       ATTRIBUTE node_num OF buried:SIGNAL IS 202;
    More restrictive than lab_force
 Can be used with SPLDs too
             The pin_avoid Attribute

      Instructs Warp to leave specified pins unused
      Useful for avoiding ISRTM pins on FLASH370i
       devices with dual-function pins
      Could also be used to reserve pins for later use


ATTRIBUTE pin_avoid OF mydesign: ENTITY IS "21 24 26";
          The sum_split Attribute

 Sum splitting occurs in FLASH370 when a signal's
  equation requires more than 16 product terms
 Two types of sum splitting
    Balanced (default)‫‏‬
       • More reliable timing for combinatorial signals
       • Uses more macrocells
    Cascaded

ATTRIBUTE sum_split OF mysig:SIGNAL IS balanced ;
ATTRIBUTE sum_split OF mysig:SIGNAL IS cascaded ;
           The low_power attribute

 The low power directive can be used to lower the power
  consumption in a logic block(s) by 50%. As a result, the logic
  block(s) slows down by 5 ns. This directive is valid only for
  the Ultra37000 family of CPLDs.

 In VHDL, use the following syntax.
   ATTRIBUTE low_power OF entity_name: ENTITY IS “b g e”;


 In Verilog, use the following syntax.
   ATTRIBUTE low_power OF module_name: MODULE IS “b g e”;
           The slew_rate attribute

 The slew_rate directive can be used to control the output slew
  rate of individual pins. This directive is valid only for the
  Ultra37000 family of CPLDs.
 Legal values for the slew_rate directive are fast and slow.
 A value of ‘fast’ sets the output slew rate to 3V/ns.
 A value of ‘slow’ sets the output slew rate to 1V/ns.


ATTRIBUTE slew_rate OF sig_name: SIGNAL IS fast;
          Third Party Tool Support
 CAE Bolt-in Tools
    Viewlogic Workview Plus/Powerview/WorkView Office
    Mentor (CY3144), Cadence (Q4)‫‏‬
 Synthesis Tools
    Synopsys, Exemplar
 PLD Development Tools
    Data I/O Abel 4/5/6 and Synario, CUPL, LOG/iC, OrCAD
 Simulation Tools
    LMG SmartModels
    All VHDL and Verilog Simulators (with timing)‫‏‬
          Top Three Issues with ISR
#1: Large file sizes
     120KB to 22 MB for a 256-macrocell device
     complicates production
     impractical for field upgrades
#2: No Software Standard
     Beyond JTAG, each approach is different
     Confusing file formats
     Solutions are vendor and platform-specific
#3: Long Programming Times
     Time is money
     Programming can take several minutes on some equipment

								
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