Digital Circuit Design - PowerPoint by 773ElO84

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									Verilog Basics

   Nattha Jindapetch
    November 2008
Agenda
   Logic design review
   Verilog HDL basics
   LABs
Logic Design Review
Basic Logic gates
Additional Logic Gates
        Two Types
   Combinational circuit
       No "memory"
       Its output depends only upon the current
        state of its inputs.
   Sequential circuit
       Contains memory elements
       Its output depends not only upon the current
        state of its inputs, but also on the current
        state of the circuit itself.
       Two Styles: Synchronous and Asynchronous
    Combinational Circuits: examples
   Multiplexers
       2n x 1 multiplexer receives 2n input bits and n selector
        bits, and outputs exactly one of the input bits,
        determined by the pattern of the selector bits.
        Combinational Circuits: examples
   Demultiplexers
       1 x 2n DMUX is the
        inverse of MUX
       It takes 1 input and
        transmits that input on
        exactly one of its outputs,
        determined by the
        pattern of its n selector
        bits.
        Combinational Circuits: examples
   Encoders
       2n x n encoder takes 2n
        inputs and sets each of
        its n outputs, based
        upon the pattern of its
        inputs.
       an encoder is the
        inverse of a decoder.
        Combinational Circuits: examples
   Decoders
       An n x 2n decoder
        takes n inputs and
        sets exactly one of
        its 2n outputs,
        based upon the
        pattern of its
        inputs.
     Sequential Circuits
        Circuits with feedback

R
                       Q    R     S   Q Q’
                            0     0   No change
                            1     0   0 1 Reset
                       Q'   0     1   1   0 Set
S
                            1     1   Not allowed

    Cross-coupled NOR gates
        Sequential Elements
           Latches vs Flip-Flops
                   Latches work on Level-sensitive
                   Flip-Flops work on Edge-triggered
                   RS, JK, D, T

S   R       Q Q’              J   K   Q Q’        D   Q   T   Q
0   0       No change         0   0   No change   0   0   0   1
0   1       0       1 Reset   0   1   0   1       1   1   1   0
1   0       1       0 Set     1   0   1   0
1   1       Not allowed       1   1   Toggle
        Counters
   Synchronous counter
       Clock of synchronous
        counter are same clock.
   Asynchronous counter
       Clock of second flip-
        flop is Q of first flip-
        flop.
       The clock of
        asynchronous counter
        are different source.
       Registers
      A register is used for storing several bits of
       digital data.
      It basically consists of a set of flip-flops.
          each flip-flop representing one bit of the register.
          Thus, an n-bit register has n flip-flops.




A Simple Shift Register Consisting of D-type Flip-flops
Verilog HDL basics
    HDL (Hardware Description Language)
   Big picture: Two main HDLs out there
       VHDL
           Designed by committee on request of the
            Department of Defense
           Based on Ada
       Verilog HDL
           Designed by a company for their own use
           Based on C
   Both now have IEEE standards
   Both are in wide use
        Verilog Description Styles

   Verilog supports a variety of description
    styles
       Structural
           explicit structure of the circuit
           e.g., each logic gate instantiated and connected to
            others
       Behavioral
           program describes input/output behavior of
            circuits
       Mixed
  Verilog Module
module module-name (list-of-port);

    input/output declarations
    local net declarations

    parallel statements

endmodule
      Structural Module: example1

module half_adder (s, a, b, co);                           co
                                   a
  input    a, b;
                                   b           w0
  output   s, co;                                    w1

  wire   w0, w1, w2;                            w2
                                                                s
  assign   w0 = a & b,
           w1 = ~w0,
                                       a   b    s     co
           w2 = a | b,
                                       0   0    0     0
           s = w1 & w2,
            co = w0;                   0   1    1     0
endmodule                              1   0    1     0
                                       1   1    1     1
      Structural Module: example1

module full_adder (s, a, b, co, ci);          i0             w1       co
                                        a    a          co
  input     a, b, ci;
                                                   HA
  output    s, co;
                                        b    b           s

  wire    w0, w1, w2;                   w0    i1
  assign    co = w1 | w2;                    a          co   w2
  half_adder i0                                    HA
                                                                  s
      (.co(w1), .s(w0), .a(a), .b(b)); ci    b           s
  half_adder i1
      (.co(w2), .s(s), .a(w0), .b(ci));
endmodule
       Structural Module: example1
module adder4    (s, a, b, co, ci);                  i0
  input [3:0]    a, b;                         ci   ci
  input ci;                                  a[0]   a     FA    s    s[0]
  output [3:0]   s,                          b[0]   b          co
  output         co;                                                w0
                                                     i1
   wire      w0, w1, w2;                            ci
   full_adder i0                             a[1]   a     FA    s    s[1]
   (.co(w0), .s(s[0]), .a(a[0]), .b(b[0]),   b[1]   b
   .ci(ci));                                                   co
                                                                    w1
   full_adder i1                                     i2
   (.co(w1), .s(s[1]), .a(a[1]), .b(b[1]),          ci
   .ci(w0));                                                    s
                                             a[2]   a     FA         s[2]
   full_adder i2
   (.co(w2), .s(s[2]), .a(a[2]), .b(b[2]),   b[2]   b          co
   .ci(w1));                                                        w2
   full_adder i3                                     i3
   (.co(co), .s(s[3]), .a(a[3]), .b(b[3]),          ci
   .ci(w2));                                 a[3]   a     FA    s    s[3]
endmodule                                    b[3]   b          co        co
Behavioral Module: example1
module adder4 (s, a, b, co, ci);
 input  [3:0] a, b;
 input          ci;
 output [3:0]   s,
 output   co;

 reg [3:0] s;
 reg co;

 always @(a or b or ci)
     {co, s} = a + b + ci;

endmodule
        Verilog Data Types
   Possible Values:
       0: logic 0, false
       1: logic 1, true
       X: unknown logic value
       Z: High impedance state
   Registers and Nets (wires) are the main data
    types
   Integer, time, and real are used in behavioral
    modeling, and in simulation
       Note that they are not synthesized !
        Verilog Registers

   Abstract model of a data storage element
   A reg holds its value from one assignment
    to the next
       The value “sticks”
   Register type declarations
       reg a; // a scalar register
       reg [3:0] b; // a 4-bit vector register
        Verilog Nets

   Nets (wires) model physical connections
   They don’t hold their value
       They must be driven by a “driver” (i.e. a
        gate output or a continuous assignment)
       Their value is Z if not driven
   Wire declarations
       wire d; // a scalar wire
       wire [3:0] e; // a 4-bit vector wire
      Verilog Parameters


   Used to define constants
    parameter size = 16, value = 8;
    wire [size-1:0] bus; // defines a 15:0 bus
     Verilog Operators
   Arithmetic operators:   +, -, *, /, %
   Logical operators:      &&, ||, !
   Bitwise operators:      &, |, ~, ^, ^~
   Equality operators:     ==, !=,
   Relational operators:   >, <, >=, <=
   Reduction operators:    &, ~&, |, ~|, ^
   Shift operators:        >>, <<
   Conditional:            ?:
      Example2: 4:1 multiplexer

module mux4 (s, d, z); //bitwise operators
input [1:0] s;
input [3:0] d;
output z;
assign z =(~s[1] & ~s[0] & d[0]) |
           (~s[1] & s[0] & d[1]) |
           ( s[1] & ~s[0] & d[2]) |
         ( s[1] & s[0] & d[3]) ;
endmodule
       Example2: 4:1 multiplexer
module mux4 (s, d, z); //using conditional operators
input [1:0] s;
input [3:0] d;
output z;
assign z = s[1] ? (s[0] ? d[3] : d[2]) : (s[0] ? d[1] : d[0]);
endmodule
        Verilog Assignments

   Two types:
       Continuous Assignments
          assign values to nets

          This means combinational logic

       Procedural Assignments
          assign values to registers

          Only allowed inside procedural blocks
           (initial and always)
      Continuous Assignments
   Models combinational logic using a logical
    expression instead of gates
   Assignment is evaluated whenever any signal
    changes
      wire a, b, out;
      assign out = ~(a & b);

      wire [15:0] sum, a, b;
      wire cin, cout;
      assign {cout,sum} = a + b + cin;
        Procedural Assignments

   Assigns values to register types
   They do not have a duration
       The register holds the value until the next
        procedural assignment to that variable
   They occur only within procedural
    blocks
       initial and always
   They are triggered when the flow of
    execution reaches them
    always Blocks
   When is an always block executed?
     always

            Starts at time 0
       always @(a or b or c)
            Whenever there is a change on a, b, or c
            Used to describe combinational logic
       always @(posedge foo)
            Whenever foo goes from low to high
            Used to describe sequential logic
       always @(negedge bar)
            Whenever bar goes from high to low
Inside always blocks

   Procedural assignments
   if statements
   case statements
   for, while, forever statements
   wait statements
Blocking vs Non-blocking
      Blocking vs Non-blocking
                    Blocking
      begin
                 q1 = x1;
                 q2 = q1;
                 z1 = q2;
      end


            Non-Blocking
begin
            q1 <= x1;
            q2 <= q1;
            z1 <= q2;
end
        Quick Review

   Continuous assignments to wires
       assign variable = exp;
       Result in combinational logic
   Procedural assignment to regs
       Always inside procedural blocks (always blocks in
        particular for synthesis)
       blocking
            variable = exp;
       non-blocking
            variable <= exp;
       Can result in combinational or sequential logic
Quick Review
module name (args…);
  input …; // define inputs
  output …; // define outputs

  wire… ;   // internal wires
  reg …;    // internal regs, possibly output

// the parts of the module body are
// executed concurrently
<continuous assignments>
<always blocks>

endmodule
comment in Verilog_HDL
     // Single-line comment
      /*………….
         …………..*/ multiple-line comment
      module mux2_1(out,a,b,sel); // port declare.
         input a,b,sel;
         output out;
         wire sel_,a1,b1
        /* structural design using logic operator
           mux2_1 */
           not (sel_,sel);
           and (a1,a,sel),(b1,b,sel);
           or (out,a1,b1);
           endmodule;
        Naming in Verilog_HDL
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        ตัวอักษรตัวใหญ่ และ ตัวเล็ก จะมีควำมหมำยแตกต่ำงกัน
      ึ     ่
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