Dr Richard Reilly
           Dept. of Electronic & Electrical

           Room 153,
           Engineering Building
• The logic designers desire for faster switching logic circuits is
  evident in the development of the TTL subfamilies

• Speed-up techniques have been evident from the beginning.
   – main method of speedup has been trying to keep the transistor from
     going into saturation
        reduce storage charge problem
        faster speed

• Depart for the CE transistor configuration (DTL & TTL logic
   – develop a circuit around the Common-Collector circuit
    now saturation problem is eliminated

• A much more difficult logic family around which to
  design a digital system.
   –   Due to speed with which ECL operates
   –   Narrower Noise margins (Considered to have less noise immunity)
   –   Expensive
   –   Harder to cool
   –   Difficult to interconnect

• Also ECL may be faster than most applications require
ECL is used in supercomputers,
·   Also in specialist computing systems such as SGI.

Called Emitter Coupled Logic (ECL)
·    It operates on the principle of current switching
·       i.e. a fixed bias current less that IC(SAT) is switched from one
  transistor’s collector to another.

Due to this current-mode operation, Logic is sometime called
·   Current-mode logic (CML)
·   Current steering logic
·   Non-saturating logic
                      Basic ECL Circuit
• The basic ECL circuit is a differential amplifier
   – In a long-tail pair configuration

• A differential Amplifier in analog applications :
    output signal  voltage gain   Input_1 - Input_2 

• A differential Amplifier in switching applications :
  inputs are restricted to a defined value of 0 or 1
   – differential amplifier configuration must compare the logic input
     level to a reference and then generate an output level.
                       Basic ECL Circuit
• The name ECL is derived as :
   – The output of the ECL switching transistor is taken from the
   – Both emitter form a junction with a common pull down resistor
     to the negative power supply rail

                              Positive Power Supply

                                  Output 1             Output 2

                         Q1                       Q2

                              Negative Power Supply
                     Basic ECL Circuit
• In terms of a logic circuit:

• If input is greater than the threshold level
    Q1 will switch ON

• Ensuring that the emitter voltage is high enough to force the
  Base-Emitter voltage of Q2 to be low
    Switching Q2 OFF

Conversely if input is less than threshold level
    Q2 is switched ON

    forcing the voltage of the coupled emitters to be too high to
     turn on Q1
    Q1 is OFF.
Basic ECL Circuit
                          Positive Power Supply:     0V

                        RC1      220         RC2        245

                                   VC1                    VC2

              Input 1                                           Threshold
                            Q1                      Q2


                        Negative Power Supply :     -5.2 V
                    Basic ECL Circuit

• The power supplies Voltages:
      0V           for the positive power supply
   -5.2 V          for the negative power supply

 Logic levels are negative for ECL

       ECL logical 1 level   =   -0.8 V
       ECL logical 0 level   =   -1.6 V
• With these voltage supplies of 0v and –5.2v

   Is ECL positive logic or Negative Logic ?
      Is ECL positive logic or Negative Logic ?

•   Positive logic
    – although both are negative the more positive level –0.8V is the
      binary 1

• small signal difference between 0 and 1.

• With ECL, the high speed and low noise margins cause
  correct termination to be vital.
                  Motorola ECL : MECL
MECL device databook defines:
   VBE = 0.8 V for the transistors in the ECL 10K family

The threshold or reference voltage defines:
   – the voltage point around which Q1 and Q2 will switch
   VREF = -1.29 V
   VBE = 0.8 V

 VE2 = +VREF - VBE2
   = (-1.29 – 0.8) V
   = -2.09 V

Because both emitters are at the same node
   VE2 = VE1 = -2.09 V
              Operation of ECL Circuitry

VB1 must be 0.8 V greater than VE1 to get Q1 to conduct

 any voltage more negative than –1.29 V will put
  transistor Q1 into cut-off


Q1 begins to conduct whenever VIN = -1.29 V or greater.
          Input High Voltage                      CASE 1
VIN = Logical 1 = -0.9 V (ECL 10K Series : High-input Voltage)

 VE1     =     VIN - VBE1
         =     -0.9 – 0.8
         =     -1.7 V

 -IE  =        (VEE - VE1)/RE
      =        (-5.2 – (-1.7))/779
   IE =        4.49 mA

Let IE1 = IC1
                   IC1 = 4.49 mA
                   VC1 = -IC1 RC1
                       = -(4.49 mA)(220)
                       = -0.988 V
               CASE 2 Input Low Voltage
VIN = Logical 0 = -1.75 V       (ECL 10K Series : Low-input Voltage)

 VE1 = VE1    =       VREF - VBE2
              =       -1.29 – 0.8
              =       -2.09 V

with VIN = -1.75 V
 Q1’S VBE can be calculated
                 VBE1 = -1.75 – (-2.09)
                      = +0.34 V

      with the Base-Emitter voltage at 0.34V is not
       sufficient to turn Q1 on
      with Q1 cut-off no majority collector current flows
               VC1 = 0 V
                          CASE 2
The two logical input voltages at the Base of Q1 switch the
  collector of Q1 between :
·   0V             when VIN is a logical 0
·   -0.99V when VIN is a logical 1

Q2 (as the other half of the Differential Amplifier) switches
  oppositely from Q1

         when Q1 conducting                 Q2 is in cut-
      when Q1 is in cut-off                 Q2 is
                          CASE 2
Let Q1 be conducting                  VIN = -0.9 V
      (Logical 1 input)

VE1    =    VIN – VBE1
       =    -0.9 - 0.8
       =    -1.7 V

VBE2   =    -VE1 + VB2
       =    -(-1.7) + (-1.29)
       =    +0.41 V        NOT sufficient to turn on Q2.
                        Multi-input Devices
• Can add additional transistors in parallel with Q1 we can
  obtain additional logical inputs.
                                  Positive Power Supply:     0V

                                RC1         220      RC2        245

                                             VC1                  VC2

           I/p B        I/p A
                   QB              QA                       Q2



                                Negative Power Supply :     -5.2 V
                 Truth Table of Operation

 Input   Input      QA     QB   Q2       VC1          VC2
   A       B

   0      0         OFF   OFF   ON     0 V (1)     -0.8 V (0)

   0      1         OFF   ON    OFF   -0.8 V (0)    0 V (1)

   1      0         ON    OFF   OFF   -0.8 V (0)    0 V (1)

   1      1         ON    ON    OFF   -0.8 V (0)    0 V (1)

From Truth Table
 VC1 and VC2 can implement a NOR and OR function
            Output Voltage Levels
• The actual output levels are different from the input
  voltage levels
• For output voltage
      Logical Low level “0” =          -0.8 V
      Logical High level “1” =         0V

• The output voltage levels need to be corrected to be
  the same as the input voltage levels
          How is this done ?

 need to subtract 0.8 V from each output level to
  return it to the original input voltage level


• Hint
          This is the output stage
                                    Positive Power Supply:     0V
  How is this done ?
• Use an emitter follower
                                                         Voltage = (VC1-0.8 V)

                               0.8 V

                                   Negative Power Supply :     -5.2 V

• Required voltage drop of 0.8 V is then used to switch the
  Output stage ON.

• The emitter-follower circuit has several practical advantages
   – Restores output Logic Level
   – Fan-out is improved due to extremely low output impedance.
         ECL never reaches Saturation

ECL circuit avoids saturation when the LHS is ON.
           VC1      =      -0.8 V
               VE =        1.6 V
               VCE1 =      0.8 V
 LHS is ON then neither QA or QB ever reaches saturation

Conversely when Q2 is on
          VC2     =     -0.8 V
              VE =      -2.1 V
              VCE2 =    1.3 V

Clearly when any of the transistor is ON
        they cannot reach saturation
             ECL Fastest Logic
ECL is the fastest logic technology available
• Can achieve propagation delays < 1 nseconds
• due to avoidance of saturation
• also switching between logic levels that are very
  close together.

Since the logic levels differ by only a small amount
   noise margin is reduced
   extra care needed when implementing ECL circuitry.
• The emitter follower output stage together with the
  other circuit components in an actual ECL 10K gate

 requires more transistor etc.

 power dissipation is high

• Inevitable price paid for inherently high speed
Symbol for an ECL NOR/OR Gate

                  ECL Characteristics
1. The transistors never saturate
    Switching speed is very high
    Typical propagation delay is 1 nseconds
    ECL is faster than 74AS series.

2. The logic levels are normally
        -0.89 V                    for Logical 1
        -1.70 V                    for Logical 0

3. Worst case ECL noise margins are approximately 250 mV
   – These low noise margins are made ECL unreliable for use in
     noisy industrial environments
                    ECL Characteristics
4. An ECL logic block produces an output and its complement
     – Eliminates the need for inverters

5. Fan-outs are typically around 25
     – Owing to the use of the emitter-followers, low output impedance

6. Typical power dissipation for basic ECL gate is 40 mW
     – Higher than for the 74 AS series
                ECL Characteristics
7. Total current flow in ECL circuit remains relatively
   constant regardless of its logic state
   Q1 or Q2 either ON or OFF

 This constant current helps maintain an unvarying
  current drain on the circuit power supply, even during
  switching transistors

 Thus no noise spikes will be internally generated.
     – Not like those produced by TTL Totem-Pole circuits !!
                     ECL Characteristics
                                  Positive Power Supply:     0V

                             RC1         220         RC2        245

                                          VC1                     VC2

I/p A        I/p B        I/p C
        QA           QB            QC                       Q2


                             Negative Power Supply :        -5.2 V
                     ECL Characteristics
                                  Positive Power Supply:    0V

                             RC1         220         RC2    245

                                          VC1                 VC2

I/p A        I/p B        I/p C                                      Threshold
        QA           QB            QC                       Q2


                             Negative Power Supply :        -5.2 V
                  ECL Characteristics

ECL family is not as widely used as the TTL family
•   except in very high frequency applications, where its speed
    is superior
•   its relatively low- noise margins and high power drain are
    disadvantages compared with other logic families.

Another drawback is negative power supply and logic levels
•   Not compatible with other logic families
•   Difficult to use ECL in conjunction with TTL circuits
                ECL Specifications

There is two ECL series :
•   10K              use power supply voltage of –5.2 V
•   100K             use power supply voltage of –4.5 V

•   100K series is faster than 10 K series
     – with a propagation delay of < 1 nsecond
     – but power dissipation is twice that of 10K series.
                                                Positive Power Supply:                0V

                      R4        220     R6         245                     R8       




C         Q1    Q2     Q3                      Q4


    R1    R2    R3                      779
    50   50   50
                                  R5                           6.1K           R9

                                Negative Power Supply :             -5.2 V
     ECL to TTL ; TTL to ECL Interfacing
• Mixing logic families is often required
   – between PCBs
   – between sub-modules of a digital system.

• Consider a digital system designed with TTL
   – Require a new high-speed ECL module to be added.

   – TTL system must signal/control certain activities in the ECL
   – ECL must send results back to TTL system on completion of
     the task
How is the interfacing carried out as logic levels
    defining Logical 1 and 0 are different ?

• Use TTL-to-ECL and ECL-to-TTL translator devices

For example, a TTL to ECL translator integrated circuit
   – The input logic levels, VIH and VIL, compatible with TTL
   – The output logic levels, VOH and VOL, compatible with ECL

Notice that in such devices 2 power supplies must be used
   – to provide +5 V and –5.2 V
   – Needed to generate the logic voltage levels for TTL and ECL
   How is the interfacing carried out as logic levels
       defining Logical 1 and 0 are different ?

• Similarly with ECL-to-TTL translators for converting
  ECL logic levels to TTL

• Such devices are used to provide logic designers with
  a tool that allows them to partition their designs to
  realise speed and power requirements by choosing
  either TTL or ECL
• ECL a difficult logic family around which to design a
  digital system.
   – Due to speed with which ECL operates
   – Narrower Noise margins
   – Expensive
   – Harder to cool
   – Difficult to interconnect

• But can be useful when fast implementation is
  required for an application.

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