Verification-Aware Microprocessor Design

					Multicore Power Management:
  Ensuring Robustness via Early-
    Stage Formal Verification
  Anita Lungu*, Pradip Bose**, Daniel Sorin*,
      Steven German**, Geert Janssen**


 *Duke   University      **IBMT. J. Watson
                         Research Center
  High Level Motivation and Goal

• Dynamic Power Management (DPM) is useful for
  multicore processors with power constraints

• Goal: Enable DPM to be more easily adopted in
  current processors
  – Observation: A DPM that is easier to verify is more
    robust and more likely to be included in processors
  – Proposal: Design verification-aware DPM schemes




                      Memocode 2009
   DPM for Multicore Processors

• We expect DPM to
  –   Increase power efficiency
  –   Avoid power spikes
  –   Cap power to allocated budget
  –   Etc.
• But, if incorrect, DPM can
  – Throttle performance to unacceptable level
  – Exceed allocated power budget
  – Lead to data corruption
                                         Need to verify DPM
                                       schemes for correctness!
                       Memocode 2009
  DPM Scheme Verification Goals

• Safety: Power usage within desired levels & no
  deadlocks in DPM protocol
  – Bug: Power capping DPM often exceeds budget
• Performance: resulting performance loss is
  acceptable

• Functional Correctness: correct results with DPM
  – Bug: DPM increases dI/dt problem  data corruption



                        DPM verification is important!

                      Memocode 2009
   Importance of DPM Verification Effort

• Design verification is challenging even without
  DPM!
  – ~60% of resources for new processor
    development allocated to verification


                       ?



• Important to consider DPM verification effort!
  – We approximate it as number of reachable states

                      Memocode 2009
    Current DPM Design and Verification
                                                DPM Scheme Concept
• Early design stage
                                                 High-Level Model
  – Focus on DPM
    performance, power         Early in
                               Design
                                           No       Acceptable

  – DPM verifiability often
                                                 Power/Performance?

    not considered
• Late design stage
  – Verify DPM scheme                            Detailed Simulation

  – DPM can have
                                                                       Yes
    enormous reachable           Late in
                                 Design
                                                     Found Bug?

    state space                                            No

  – Difficult to change DPM                 No        Sufficient
                                                      Coverage?
    concept                                                Yes
                                                        Done

                          Memocode 2009
      Proposed DPM Design and Verification
                                                     DPM Scheme Concept
• Validate high-level DPM
  concept through formal                  High-Level Model     High-Level Formal Model

  verification            Early in
                          Design     No      Acceptable                Verification

• Formal verification                     Power/Performance?           Scalability?
                                                                                Yes
                                                                                       No

  benefits:                                                             Successful
                                                                       Verification?
   – Exhaustive traversal of
     reachable state space                              Detailed Simulation
     (of high-level model)
   – Estimation of size of           Late in                 Found Bug?
                                                                             Yes

     reachable state space           Design
                                                                  No
     (verifiability)                               No        Sufficient

   – Catch design bugs early
                                                             Coverage?
                                                                  Yes
                                                               Done

                             Memocode 2009
     Research Contributions

• Use verifiability as
  additional metric
  considered at early
  DPM design stage
                                                 Verification Effort
• Compare verifiability of
  different DPM schemes

• Evaluate trade-offs                                 Performance
  between verification
                                             X
  effort, efficiency and
                                                 X
                                                     DPM Parameter

  safety of DPM schemes

                             Memocode 2009
  Outline

 Motivation & Proposed Approach
• Illustrative DPM Verification Examples
• Experiments and Results
• Conclusion




                     Memocode 2009
    Considered DPM Scheme
• Goal: Maintain
  multiprocessor power
                                                            Power
  usage below an                                            Budget
  allocated budget                               Global Controller
                                 Actuate VDD,
                                  Frequency
                                                Monitor
• Important problem for                         Power Use

  multicores                    VDD     Freq
                                      IPC
                                                    VDD     Freq
                                                          IPC
                                                                     VDD     Freq
                                                                           IPC
  – Increase in number of         Core 1              Core 2          Core 3
    cores  increase in
    gap between average
    and peak power use


                            Memocode 2009
   Considered DPM Scheme
                                                                              Power
                                                                              Budget



• Global controller
                                                                        Global
                                                                       Controller




  – Monitor power usage
                                           Actuate VDD,
                                            Frequency           Monitor
                                                                Power Use
                                         VDD    Frequency        VDD    Frequency       VDD    Frequency

  – Actuate VDD and                             IPC
                                               Core 1
                                                                        IPC
                                                                       Core 2
                                                                                               IPC
                                                                                              Core 3

    Frequency of cores to
    cap power                                                                             Actuate
                               Global          Actuate VDD
     • Actuate VDD and     Power Use                                                     Frequency
                           Max Power
       Frequency every                                  *
                                                                         *
                                                                                                       * *
                              Budget
       500us
     • Actuate only
       Frequency every
       100us                               1      2     3   4      5     6      7   8    9     10 11 12 13 14
                                                                                                                Time



                         Memocode 2009
    DPM Parameters and Verifiability
                                                                 Utilization (IPC)
• Controller algorithm:             Budget
                                                 Controller      Actuator      System
                                             +
   – Set next VDD and Frequency so
     power usage < budget
                                                       Approximate
• Design parameters:                                   Power Usage
                                                    f(IPC, VDD, Freq)
   – Voltage levels, Frequency
     levels, Cores per controller
   – Homogeneous vs.
     heterogeneous VDD values

                                        2 Cores per controller      3 Cores per controller
• Questions:
   – What is the impact on verifiability of above design decisions?
   – What are the tradeoffs between performance, verifiability
     and safety?


                               Memocode 2009
   DPM Verification with PRISM Model Checker
• Model Description
                                                   State       Transition              Correctness
   – State variables                             Variables       Rules                  Properties
      • Current VDD, Frequency, Utilization
        values for all cores (~IPC)
      • Possible State:                                             Model
          – One assignment of values to state                      Checker
            variables from their domain
      • Reachable State:                                                              0.2
                                                                               0.4
          – One assignment of values to state                0.4
            variables allowed under DPM                0.3
                                                                   0.1
                                                                             0.6
                                                                                     0.4
                                                                                           0.4

   – Probabilistic transition rules                          0.2         1
      • Probabilistic changes in utilization
                                                                                      NO
   – State rewards
                                                                   Correct?
      • To each state, assign tokens
        representing power & performance                              YES
                                                                    Done


                                 Memocode 2009
    DPM Verification with PRISM Model Checker
• Correctness Properties
                                                State       Transition              Correctness
   – For every reachable state                Variables       Rules                  Properties
      • VDD and Frequency values matched
        and within range
      • No deadlock                                              Model
   – Along model execution paths                                Checker

      • Power over budget < X% of total                                            0.2
        power                                                               0.4
      • Performance loss < Y% of baseline           0.3
                                                          0.4
                                                                          0.6           0.4
                                                                0.1               0.4

                                                          0.2         1
• Model Check
   – Build model                                                                   NO

      • Reachable states, expected values                       Correct?
        of rewards                                                 YES
   – Check correctness properties                                Done


                              Memocode 2009
  Outline

 Motivation & Proposed Approach
 Illustrative DPM Verification Examples
• Experiments and Results
• Conclusion




                     Memocode 2009
    Methodology

• Modeled 6 SPEC2000 benchmarks and their combinations
   – Art, bzip, crafty, eon, mcf, parser
   – Used probabilistic utilization transitions from simulation
   – Budget set to 25%, 40%, 50%, 70%, 100% of maximum
• Trade-offs analysis
   – Verifiability metric
       • Number of reachable states and transitions
   – Performance metric
       • % Performance (Frequency) vs. baseline without DVFS
   – Safety metrics
       • % Power over budget of baseline system without DVFS
       • % Intervals over budget



                              Memocode 2009
                                Results: Voltage Levels
                                1 CPC       2 CPC       3 CPC

                 95                                                                       5
 % Performance




                                                                       % Power Excess
                 93                                                                       4
                 91                                                                       3
                 89                                                                       2
                 87                                                                       1
                 85                                                                       0
                        2           3       4       5       6                                    2       3       4       5        6
                                   Voltage Levels                                                        Voltage Levels




                                                                       Reachable States
% Intervals Over




                   10                                                                     1600
                   8                                                                      1400
                                                                                          1200
    Budget




                   6                                                                      1000
                   4                                                                       800
                                                                                           600
                   2                                                                       400
                                                                                           200
                   0                                                                         0
                            2           3       4       5       6                                    2       3       4        5       6
                                   Voltage Levels                                                            Voltage Levels

                                                                Memocode 2009
                                 Results: Freq. Levels per Voltage Level
                                 1 CPC   2 CPC       3 CPC

                     95                                                               5
     % Performance




                                                                   % Power Excess
                     93                                                               4
                     91                                                               3
                     89                                                               2
                     87                                                               1
                     85                                                               0
                             1       2    3      4       5                                   1       2       3       4       5
                          Frequency Levels / Voltage Level                                Frequency Levels / Voltage Level




                                                                   Reachable States
                     10                                                               1400
% Intervals Over




                     8                                                                1200
                                                                                      1000
     Budget




                     6                                                                 800
                     4                                                                 600
                                                                                       400
                     2                                                                 200
                     0                                                                   0
                             1      2     3      4       5                                       1       2       3       4       5
                      Frequency Levels / Voltage Level                                       Frequency Levels / Voltage Level

                                                             Memocode 2009
    Conclusions

• Making design choices with verification in mind
  does impact the resulting verification effort

• Adding verifiability as a separate metric to be
  considered together with performance, reliability,
  and safety may lead to different design choices




                     Memocode 2009
Thank You!




             Memocode 2009

				
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