# Dunn et al Foundation of rf CMOS and SiGe BiCMOS Technology IBM JR es Dev vol 47 no 2 3 March May 2003

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```					                  Monolithic RFIC Design

Chapter 03

Bipolar Junction Transistor Device Modeling
- SiGe HBT Technology

“The more correct the device model is,
the shorter time the design cycle needs!”

T.H.Huang
Before Discussing on Device Modeling

Let us figure out:

(1)Linear / Non-linear system?
(2)Linear region (of operation) / Saturation region?
(3)Large signal / Small signal ?

Then, a brief introduction to SiGe HBT technology.
Linear and Non-Linear

A linear System :

A linear system prohibits the feature of

Y = A‧X

That is, the output Y of a system is just related
to its input X variables with a certain relationship
of A (Amplification factor).

•We neglect the singularity property of the system.
If there is no relationship existed among
the input variables, they are independent.
In mathematical expression:

Xi’s are independent, if only ai=0 to make

Σai xi = 0      (summation)

 Xj’s are independent variables.
Linear (-operation) Region for a transistor :
The operation region where
the output of the transistor is
linearly proportional to its input signal.
However, the definitions of “input” and “output”
are related to the case what we investigate on.

saturation vgs
Id                        3             Id vs. Vds?
linear                   vgs2               Id vs. Vgs?
vgs1
Vds
Non-linear Case:

(1) Current is a function of voltage I(V) = a0+a1 V+a2 V2+…(多項式)
(2) The drain current of a MOSFET :

 W                VDS 
2
I D (VGS , VDS )  μ n Cox  VGS  VT VDS      
 L                 2 

Discussion:
(1) if VDS >> 1, pinch-off, ID saturated. (not this form!)
(2) if VDS << 1  approximation further.
(3) under VDS << 1, ID vs. VGS  also linear!
In general, (in an analog viewpoint)

BJT  a current-to-current converter;
MOS  a voltage-to-current converter.

IC            IG=0        ID
IB                             X
VG
I

Large Signal or Small Signal

              1 Vth = 0.0259 (V) = 26 mV
Another Viewpoint of “Small signal” or “Linear operation”:
-- by Power Compression

[Ex. LNA]
(ideal)
Pout (dBm)

(real)

Pin         Amp       Pout

Pin (dBm)
Bipolar Transistor
Part A BJT Devices :
N-P-N / P-N-P Structures
Poly-Emitter Bipolar Transistor
Bipolar Transistor’s Applications

• 優點
–操作速度快
i C          iC          v
–驅動電流大                 gm          exp( BE )
v BE        0.0259       0.0259

• 類比電路
–放大器(Amplifier )
–射頻電路(RF circuits)
–汽車電子(Automotive Electronics)
[ref]: 陳福騫, “RF 主流製程技術與趨勢分析”, 拓樸產業研究所焦點報告, No.6, Jul. 2007.
[ref]: 陳福騫, “RF 主流製程技術與趨勢分析”, 拓樸產業研究所焦點報告, No.6, Jul. 2007.
SiGe Bipolar Transistor

Introduction to SiGe HBT technology

Two main approaches:
(1)Differential epitaxy technology;     (Jazz)
(2)Selective epitaxy technology.        (IBM)

State-of-the-art : SiGe HBT fT = 350 GHz (in 2002*)
and fmax = 270 GHz,
for ≧ 100 Gbits/sec data transmission.

Conexant / tsmc 0.35um SiGe technology;
tsmc : 0.25 / 0.18 um SiGe technology;
Jazz semiconductor : 0.18 um SiGe200 technology;
IBM SiGe BiCMOS : (in 2004)
IBM SiGe BiCMOS :   (high-performance HBT)
IBM SiGe BiCMOS :
SiGe Bipolar Transistor

IBM SiGe BiCMOS 8WL Process :
Japan NEC SiGe BiCMOS :
Japan NEC SiGe BiCMOS :
Jazz SiGe BiCMOS :
Jazz SiGe BiCMOS : (Application  802.11b/g, Tx PA)
(Airoha’s AL2230 by Jazz’s SiGe60)
SiGe Bipolar Transistor

SiGe HBT的截止頻率比較

•Jazz Semiconductor
SiGe Bipolar Transistor

SiGe HBT的截止頻率比較

•IBM

[Ref]: J.S. Dunn et al.,”Foundation of rf CMOS and SiGe BiCMOS Technology,” IBM J. Res. & Dev., vol. 47, no. 2/3,
March/May 2003.
(IBM BiCMOS)
SiGe Bipolar Transistor

(A) Differential Epitaxy (Jazz) :                This part,
single crystal region

•P+ SiGe layer is grown after oxide isolation formation.
•A nucleation layer for improvement of adhesion of polysilicon.
•P+ SiGe layer will be single crystal over the exposed collector region.
•Issue of transient enhanced boron diffusion when doing extrinsic base
implantation.
SiGe Bipolar Transistor

Main (simplified) process flow for differential expitaxy

Shallow Trench                         •Exposed collector
•Shallow/deep
trench;
•n+ buried layer

•Nucleation layer;
•Single crystal /
polysilicon growth;
•Defects (cause
the leakage curr.)
SiGe Bipolar Transistor

•Thin oxide layer
•Emitter poly formation
•Similar to double
poly process
•Low BC parasitic cap.
•Transient enhanced
boron diffusion

•Silicide option to
reduce the extrinsic
base resistance
•self-alignment tolerance
SiGe Bipolar Transistor

Polysilicon Nucleation Layer       •Exposed collector
 single crystal silicon;
•Over the nucleation layer
 polysilicon layer;
•Defect issue;
•Nucleation layer thickness
 optimized for growth rate.

Nucleation Layer functions:
(1) Protect the gate oxide
from contamination during
emitter processing;
(2) Hydrogen passivation
before epitaxy, while
etching back stop is hard
to detect if the most part
of the wafer is oxide;
(3) Easy to control growth rate
due to the similar condition
of blanket silicon wafer.
SiGe Bipolar Transistor

Self-aligned Emitter Process (1)
(emitter window define)
(a conversion layer,
for the dummy emitter)

(release the stress)

* SiO2 deposition +
anisotropic (RIE) etching
back  spacer.
SiGe Bipolar Transistor

Self-aligned Emitter Process (2)

•Local oxidation
for the dummy emitter.

Stop layer for Si3N4
RIE; and then using
wet etching to
open the emitter
completely.

•Emitter poly deposition
•Emitter poly implantation
•Emitter poly define.
SiGe Bipolar Transistor

(B) Selective Epitaxy (IBM) :
Void (空隙) issue

•P+ polysilicon extrinsic base is formed before epitaxy process;
•Void issue in P+ extrinsic base and intrinsic base epitaxial layer contact;
•Self-align for extrinsic base implantation.
SiGe Bipolar Transistor

Main (simplified) Process flow for selective expitaxy

•Thermal oxidation
•Extrinsic polysilicon
base deposition/
implantation.

•Nitride layer deposition
•Emitter window opening;
SiGe Bipolar Transistor

•nitride spacer formation;
•Wet etching laterally
to expose the bottom
surface of the extrinsic
base polysilicon.

•Epitaxy :
single crystal over collector;
polysilicon over the extrinsic
base poly.
Difficulties: (刻面)
Voids (空洞)         (1) Facet formation voids;
resistance.             the epi growth rate.
SiGe Bipolar Transistor

Germanium (Ge) Doping Profile :

Electron
transition
Ebuilt-in     enhancement
due to
the built-in E.
SiGe Bipolar Transistor

(Energy) Band Engineering :

Narrower Bandgap in Base region!
SiGe Bipolar Transistor

Typical I-V :

Ic level increases
due to lower EC barrier.
SiGe Bipolar Transistor

SiGe:C technology: (0.1~0.4% carbon)

Carbon-doped process helps in preventing
from the so-called “transient enhanced boron
diffusion” when doing the extrinsic base
implantation.

•Note : another technology for “High Power/Breakdown”
applications is the Si-C technology.
 for PA applications!
Low-Cost SiGe Technology

Germanium-Implantation technology:

self-aligned double poly
BJT process.  low-cost.
the base width wider.
 lower fT and fmax. (~75GHz)
Low-Cost SiGe Technology

Germanium implantation process
B-C

•Ge-implantation does : ~ 3x1016 cm-2, to
amorpholize the silicon bulk
to eliminating the channeling
tail of base boron profile.
Self-Alignment Technology

Self-Alignment Technology
-- to reduce the parasitic E-B overlap capacitance

•Like a differential epitaxy process.
•But get improved fT performance.
Lateral PNP

Lateral PNP in BiCMOS/CMOS technologies

Current Gain Enhancement:
(1) Collector: surrounding
the emitter;
(2) Base: n+ buried layer
to form a n+/n barrier

Beta ~ 30 available.

poor high-freq.
operation.
(due to wide base
and heavier Cap.)
Parasitics in a BJT device



Parasitics!
Large-Signal Model



Large-Signal Model
Large-Signal Model



[to be continued]

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