LD 02sept2008

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					 AMICSA 2008 31 August – 02 September
 Sintra, Portugal




Multi-Gbit/s Capable 65nm CMOS Ser/Des
Design Analysis for Space Application
 Dugoujon, L.1; Hili, L.2; Skoulaxinos, S.3; Papadas, C.3; Baguena,
L.4; Childerhouse, M.5; Tonietto, D.1; Ramet, S.1; Badets, F.1;
Lavastre, S.1; Briand, P.1

1STMicroelectronics(France); 2ESA (The Netherlands);
3ISD Athens (Greece); 4Thales Alenia Space (France);
5EADS Astrium (United Kingdom)
                  ST Global Presentation




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             1
                            Thales-Alénia Space
                  ST Global Presentation




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             2
                            Thales-Alénia Space
                  ST Global Presentation




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             3
                            Thales-Alénia Space
                  ST Global Presentation




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             4
                            Thales-Alénia Space
          ST Space & HighRel History & Policy


  First space supplier ever SCC-B Qualified (1979)
  Major ESA QPL contributor
  1999: Creation of Rad Hard Design Center in ST-Sicily
      Expanding product portfolio
  ST Space & HiRel Policy:
      Wide & stable Product Range offerings
      300krad at High Dose Rate & ELDRS (world leadership).
      Top level Heavy Ions requirements
      Top Level Space Quality
      Develops world business through QML-V Qual (1998)
      Full support & commitment to Europe national Space Programs:
           « GalileoSat », « NGP », « Digital Divide », « COSMO » , « XMM »
  Dedication to custom products support




                                 STMicroelectroics, ISD
AMICSA 2008, September 02        EADS-Astrium                           5
                                 Thales-Alénia Space
                 Space Product Portfolio extract

Available:
    Classical bipolar Transistor                               2N2222’s series
    300krad ELDRS-free Bipolar Linear Regulators: RHFL4913, L7913
    300krad ELDRS-free Bipolar Op-Amps:           RHF43B
    300krad Bipolar fast Op-Amps             RHF300=>RHF350 series
    100krad Logic series:          54HC00’, CD4000B’s (Escc)
    300krad Logic serie:                     54AC00’s        (Qml-V)
    300krad 16-bit Bus Interfaces:           54VCXH162244’s (Qml-V)
    300krad 12-bit AD-Converter:             RHF1201         (Qml-V)
    300kRad 14-bit ADC                       RHF1401 Qml-V in 2008.

In the pipe:
    Smd Diodes                                    1N5822-5819-5811-5806 ‘s
    100 kRad PowerMOS
    100kRad ELDRS-free 2N Transistors redesign
    300krad 32-bit Bus Interface                  54VCXH322245 EM avail, qual ‘08
    300krad ELDRS-free Quad Op-Amp                RHF484
    300krad ELDRS-free fast Op-Amp                RHFS111 of a new RH-SOI techn
    Clock Distributor                              RHFLVDS111,      650MHz, EM avail




                                      STMicroelectroics, ISD
  AMICSA 2008, September 02           EADS-Astrium                                 6
                                      Thales-Alénia Space
                                              MSL ROVER
ST INSIDE
Juno Spacecraft
                                                       L = ~9’


                              JWST Telescope




                              STMicroelectroics, ISD
  AMICSA 2008, September 02   EADS-Astrium                       7
                              Thales-Alénia Space
 Need & constraints for Gbit/s SerDes

   Main application:
   Next Generation Telecom Satellites Digital Payload

   Partnering with European space industry primes:
   EADS-Astrium, Thales-Alenia Space

   Key objectives of KIPSAT project (under ESA contract):
        Assessment of ST 65nm long term reliability
        Demonstration of SerDes 6.25Gbit/s performances
        Baseline for a space-grade ASIC technology




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium                  8
                            Thales-Alénia Space
        System Architecture example




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             9
                            Thales-Alénia Space
            Payload ASICs constraints

    Payload Processor ASIC requirements:
    10-30 Millions gates- 3-8Mb RAM - 6Gbit/s
    Serial I/Os – 200-400MHz Processing Clock –
    Low dissipation – High-Reliability - RadHard –
    Hermetic Package – Moderate customization
    costs for Manufacturers

    Such performances are only achievable with
    Deep Sub Micron

    ST proposed its CMOS 65nm, commercially
    qualified in 2007.


                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             10
                            Thales-Alénia Space
     ESA Requirements / Intrinsic 65nm

    10-30 Mgates                             750 kgates/mm2
    400MHz clock                             2GHz stdcells
    Low power < 10W                          5.7nW/(MHz x gates)
    >20 x 6.25Gbit/s HSSL                    1.25-7.5GBit/s modules
    Available before 2011                    Production in 2008
    Non ITAR                                 Made in Crolles (Isère-F)
    TID > 200krad(Si)                        No variation 100krad(Si)
    No SEL 80MeVcm2/mg                       OK with process option

    SEE<10-10/b/day in geo                   Efforts needed for SEUs
    15 years opl. lifetime                   Achievable
    Viable business model                    MPW/MLR or Platform


                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium                      11
                            Thales-Alénia Space
                 What? 65nm for Space!

     Do we risk in such recent technology?

     What about:
          Rad-hard capabilities
          Reliability
          Cost
          Design flow




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             12
                            Thales-Alénia Space
                Rad-hard maximisation

    Rad-hard capabilities measured under ESTEC-ST
    contracts (ST 130nm, 90nm, 65nm and 45nm)
    Usage of process option for SEL (1mask)
    Experimental confirmation on worst case supply and
    Temp
    Validation of « analog » HSLL IP (LC-tank VCO)
    Re-use of SEU mitigation techniques (ST patented) on
    Std. Cells and clock-trees specificaly developed for
    this 65nm platform
    Usage of a mix of SRAM or rSRAM (ST patent) cuts to
    be defined with end-users
    RH by design ST (+CERN) know-how enriched by
    end-users cooperation.



                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             13
                            Thales-Alénia Space
               Reliability maximisation

   Analysis of reliability figures from Std
   qualification

   Systematic application of ST DiR methodology
   (focusing HCI and NBTI) with dedicated tools for
   ageing simulations

   Eventual specific layout rules for reliability
   enhancement

   Study of tighter controls at process level

                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             14
                            Thales-Alénia Space
           Reliability summary for ST 65nm


LEVEL1 (Wafer Level Reliability):
   Even with Worst Case test conditions, all but two items
   (NBTI+HCI) exceed 15 years spec on test structures.
   NBTI + HCI: Accurate simulation methodology +
   design guidelines provide means to exceed 15 years
   on actual IC.


LEVEL2 (Early Failure Rate + Over Life Test ) :
   Qualification step: 8 fails out of ~ 6000 samples. All
   explained by defectivity/SPC.
   Post-Qual monitoring: 0 fail (10 years) out of ~4000
   samples.
   Huge enhancement of D0 with the PDF program.




                             STMicroelectroics, ISD
 AMICSA 2008, September 02   EADS-Astrium             15
                             Thales-Alénia Space
              Device Reliability Modeling
                                                                         VG+
        Goal: Cover all VG/VD domain                                                  HCI
                                                                  PBTI
             VG
                                                                                      Off-state
                                                                                      VD+

        GATE
       GRILLE



                            VD                                           VG+
        BULK
      SUBSTRAT




                                                     Off-state                        VD+

                                                                               NBTI

                                                            HCI
                                 STMicroelectroics, ISD
AMICSA 2008, September 02        EADS-Astrium                                  16
                                 Thales-Alénia Space
                     Transistor-Level Reliability Simulation
                                      Flow
                                                                    Reliability model (Eldo UDRM)


                                                                              Reliability
     •Extended models           SPICE model
                                                                             parameters



                                                         Description of                       Description of
                                                        Transistor Stress                   SPICE parameters
                                                          as function of                      evolution as                 •Age.lib object Library
                                                             Activity                       function of Stress




     Netlist                                                                                                     Simulate Aged               Aged Results



                               Simulate Fresh


Model Parameters
                                                                                                                                             Comparison
    (Fresh)                                                                 Updated SPICE
                                                                             parameters


  Aging related
                                    Stress analysis                                                                                         Nominal Results
   commands
                                                                                                                            Eldo




                                                      Stress File


                                                             STMicroelectroics, ISD
                                                             Optional
                  AMICSA 2008, September 02                  EADS-Astrium                                                              17
                                                             Thales-Alénia Space
       Reliability Modeling/Simulation Flow
   NBTI, HCI stress experiments                              Reliability Modeling
   Multiple Vgs/Vds conditions
                     Model describing the degradation
Extractionof         f(Ids,Ib,W)-HCI
degradation          f(Vgs,Vds,T,L,t)-NBTI
parameters such as
Vt, gm and curves
           IV         ModelSPICE
during stress         parameter evolution           Add toSpice model



STEP 1 Estimation of degradation of At designer end
       Different transistors
                                                                     Circuit spice n/l
                                                                           +
                                                                      Input stimuli

 Evaluation of       Iterativ           Reliability Simulation
 degradedSPICE       e
                                    STMicroelectroics, ISD
                    Running
   STEP 22008, September 02 Simulation
    AMICSA                          EADS-Astrium
                                    Thales-Alénia Space
                                                                        Compare
                                                                          18
                      with degraded models
                       Silicon Validation
        Inverter ring in 65nm technology
        Simulations similar to HTOL of fab silicon




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             19
                            Thales-Alénia Space
                NBTI simulation: digital buffer




Note the delay introduced by the NBTI
in comprison to the same buffer
without NBTI

                                        STMicroelectroics, ISD
  AMICSA 2008, September 02             EADS-Astrium             20
                                        Thales-Alénia Space
                                   NBTI: Vth shift




Illustration of the input
threshold shift in I/O buffer




                                      STMicroelectroics, ISD
       AMICSA 2008, September 02      EADS-Astrium             21
                                      Thales-Alénia Space
                                                                  SERDES principle
                                                                                                            /2
                                                    Ref Clk                                                      Q
                                                                                                        I




                                                                                                                  3.125GHz
4 to 10 data Slices per Clock Slice




                                                         RX
                                      Data Slice        input
                                      Data Slice
                                      Clock Slice                 offset
                                      Data Slice                Cancellation
                                      Data Slice




                                                        TX
                                                       output

                                                                               STMicroelectroics, ISD
                                           AMICSA 2008, September 02           EADS-Astrium                      22
                                                                               Thales-Alénia Space
                            SerDes features
   Technology         65nm LP ,7 metal ,triple VT, Dual Gate oxide 50A

   Power S.           Single 1V2

   Data Rates         1.25, 2.5, 3.125, 3.75, 5, 6.25, 7.5Gbps with a single
                      156.25 ref. clock. (125Mhz ref clock supported )

   IO                  RX equal. adaptive , linear up to 15dB + 4 tap DFE
                       TX: 5 Tap FIR, programmable

   Stackability       4 links per macro

   Power               250 max @7.5Gbps, 200 max @ 5Gbps
   (mW/Link)
   Area/Bump          900u x 640u /link ( 10 bumps)         designed for 2-2-2 FCBGA

   Reference          CEI-6 LR
                      Use: Long reach backplanes lines
   Maturity           IP Test chip fully tested, ASIC products in qualification

   Doc                Data sheet available ; CAD views available


                                   STMicroelectroics, ISD
AMICSA 2008, September 02          EADS-Astrium                            23
                                   Thales-Alénia Space
                                                                              SerDes Packaging constraints
Bump              usage                                                                                                                                       Power     consumption table
             Clock + 4 Data slices Bump out                                                                                                                                    data slice            clock slice
                                                                                                                                                                               power supply          power supply
                                640u
                                                                                                            Edge of die
                   RXP               TXP           RXP           TXP                                  TXP          RXP          TXP            RXP               Rate     1.1      1.2       1.3    1.1   1.2       1.3




                                                                                                                                                RXP
                   _LI_              _LO           _LI_          _LO         CKP          CKN         _LO          _LI_         _LO            _LI_
                    3P               _3P            2P           _2P                                  _1P           1P          _0P             0P




                          RXP
                          _LI_
                                             TXP
                                             _LO
                                                          RXP
                                                          _LI_
                                                                       TXP
                                                                       _LO
                                                                                                TXP
                                                                                                _LO
                                                                                                            RXP
                                                                                                            _LI_
                                                                                                                          TXP
                                                                                                                          _LO
                                                                                                                                        RXP
                                                                                                                                        _LI_
                                                                                                                                                                  1.25
                           3N                _3N           2N          _2P                      _1P          1N           _0P            0N
            900u




                                                                                                                                                                  2.50
                                                                                    RT
    1200u




                                       VCC




                                                                 VCC




                                                                                          VCC




                                                                                                      VCC




                                                                                                                                  VCC
                                                                                                                                  VCC
                    VSS




                                                   VSS




                                                                             VSS




                                                                                                                   VSS
                                                                                                                   VSS




                                                                                                                                                VSS
                                                                                                                                                VSS
                   VSS               VSS                                                                                         VSS           VSS




                                                                                                                                                                 3.125
                          VCC




                                                           VCC




                                                                                                            VCC




                                                                                                                                        VCC
                                                                                                                                         VCC
                                             VSS




                                                                       VSS




                                                                                                VSS




                                                                                                                          VSS
                                                                                                                          VSS
                          VCC                                                                                                           VCC




                                                                                                                                                                  3.75
                                       VCC




                                                                 VCC




                                                                             VCC




                                                                                                      VCC




                                                                                                                                  VCC
                                                                                                                                  VCC
                    VSS




                                                   VSS




                                                                                          VSS




                                                                                                                   VSS
                                                                                                                   VSS




                                                                                                                                                VSS
                                                                                                                                                VSS
                   VCC               VCC                                                                                         VCC           VCC




                                                                                                            Core side                                             5.00              172       200          63
                                                                                                      Core side
                                                                             CN




                                                                                          CN
                                                                                          CP




                                                                                   480u                                                                           6.25              187                    68
 Update : 1clock slice support 8 data slices
                                                                                                                                                                    7.5             201       250          73
           (tbv)              12 @7.5G
           (tbv)              16 @6.25                                                                                                                        Power at Vod peak =400mV

Bump                     to ball ratio
                                 Bump                     Ball
                                                                                          Package                              notes
 Signal                          1                        1
                                                                                                Require 1 Resistor and 1 Cap on package
 AVDD                            4                        1
                                                                                                Designed for FCBGA build up 2-2-2 substrate.
 AGND                            4                        1

 VCC                             TBD                      1
                                                                                                                                                      STMicroelectroics, ISD
                                  AMICSA 2008, September 02                                                                                           EADS-Astrium                                        24
                                                                                                                                                      Thales-Alénia Space
           SerDes Terrestrial > Space

     Organic fcBGA Pkg, 17x17, 2-2-2, 256 Balls, 1.0 mm ball
     pitch
          Hermetic package solution under analysis

     Target BER <10-18 (on CAT4K legacy backplane)
           ESA specs of <10-12 (medias to be defined)

     250mW max power @7.5Gbps, 200mW max power @
     5Gbps
           ESA spec=200mW, slight power reduction under study

     Re-simulations with ageing effects and eventual rework
          15-20 years verification in worst case conditions




                              STMicroelectroics, ISD
AMICSA 2008, September 02     EADS-Astrium                    25
                              Thales-Alénia Space
             SEUs mitigation techniques

       Analysis of SerDes critical areas
       Replacement of standard dffs by robust dffs
       (ST patents)
       Use of robust clock-trees (ST patents) where
       critical
       Implementation of TMV where necessary
       Continuous reading of configuration registers
       and automatic recovery in case of corruption




                            STMicroelectroics, ISD
AMICSA 2008, September 02   EADS-Astrium             26
                            Thales-Alénia Space
                       Ser/Des Validation (1)
Astrium has evaluated and tested Texas and Xilinx Ser/Des systems.
Texas TLK2711 – 1.6 to 2.5 Gbps
    Tested with parallel clock at 1.6Gbps and 2.5Gbps.
    Tested with nominal supply voltage (2.5V) +/-0.1V.
         No noticeable correlation was apparent.
    Tested with various lengths of differential stripline traces and 50 ohm matched
    length coax cable.
         Stripline lengths of 10, 15, 20, 30, 40 inches and combinations
         thereof.
    Tested using built in PRBS (27 -1) in a loop back configuration.
    Eye measurements
    Jitter measurements
    BER measurements
         Error free, from 1.6 Gbps to 2.5 Gbps, within a determined distance.




                                        STMicroelectroics, ISD
     AMICSA 2008, September 02          EADS-Astrium                          27
                                        Thales-Alénia Space
                Ser/Des Validation (2)
  Xilinx ML321 – 3.125 Gbps
      Tested at 3.125 Gbps and 2.5Gbps using on-board and external oscillator.
      Tested with various lengths of differential stripline traces and 50 ohm
      matched length coax cable.
           Stripline lengths of 10, 15, 20, 30, 40 inches and combinations
           thereof.
      Tested using built in PRBS generator using various polynomials in a loop
      back configuration with 33% pre-emphasis.
      Eye and jitter measurements.
      BER measurements..
           Error free, at 2.5 & 3.125 Gbps, within
         a determined distance, with short PRBS
         polynomials.

  Xilinx MK322 – 10 Gbps
      Tested at 5 Gbps and 10 Gbps with various lengths of differential stripline
      traces and 50 ohm matched length coax cable.
      Tested using built in PRBS generator using various polynomials in a loop
      back configuration with default and optimised pre-emphasis.
      Eye and jitter measurements.
      BER measurements.
           Virtually error free, at 10 Gbps, over shorter distances.
                                 STMicroelectroics, ISD
AMICSA 2008, September 02        EADS-Astrium                            28
                                 Thales-Alénia Space
                 Ser/Des Validation (3)

“Quatuor” Validation
   Test Quatuor configurations that are likely to be used in telecoms payloads.
   Test various parametric configurations, e.g. pre-emphasis, output level,
   equalization.
   Consider requirements for autonomous link establishment and maintenance in space
   environment subject to SEE.
   Prove that unidirectional links can be established, that link performance
   degradations and link loss maybe detected and that links can be re-established.
   Test with various media as expected to be used in telecoms payloads.
   Test impact of clock quality on measured BER.
   Perform eye and jitter measurements.
   Estimate best achievable BER (assuming ideal Rx and clock recovery) in the absence
   of other noise sources.
   Measure BER.
   Participate in radiation testing of Quatuor
   Advise on the design of evaluation board ensuring direct access to parallel digital
   data.
   Consider the design of dedicated test hardware, for BER, for link establishment and
   maintenance, for SEE testing.
   Consider hiring dedicated parallel BER Tester.




                                 STMicroelectroics, ISD
 AMICSA 2008, September 02       EADS-Astrium                          29
                                 Thales-Alénia Space
                 Validation with TAS (1/1)

   Thales Alenia Space has been implementing such kind of
   components for a long time, starting with first generation of 400
   Mbits/s links, that are now in orbit
   More recent payloads required far higher
 speeds and Serdes components from
1 Gbits/s to over 3 Gbits/s have been
evaluated in our labs
   We are presently working on last
 generation of components up to 10 Gbits/s

  2 methodologies are being used:
      Elaboration of our own test/evaluation breadboard including
      proprietary BER measurement environment on specific breadboard
      Utilization of commercial tools for BER on breadboard:
           BER tester Anritsu 1632A up to 3,2 Gbps
           BER tester Agilent N4901A up to 12 Gbps

  Thales Alenia Space expertise and means will support the present
  HSSL development


                                      STMicroelectroics, ISD
  AMICSA 2008, September 02           EADS-Astrium                     30
                                      Thales-Alénia Space
                             Cost mitigation

            Hi-rel Rad-Hard stdcells & IPs selection
            Metal-Customizable Logic

Low
troughput/power
consumption
  FPGA                         Structured ASIC           Full cust. ASIC




                                STMicroelectroics, ISD
 AMICSA 2008, September 02      EADS-Astrium                    31
                                Thales-Alénia Space
                            Conclusions

   CMOS 65nm provides needed performances for
   next generation satellite telecom payload
   processors
   NBTI and HCI are well modeled and simulated
   TID is not an issue, mitigation of SEUs needed
   High performances SerDes derived from a
   proven IP used in telecom networking products
   Robust dff + clock trees available libraries
   End-users participate to demonstrator chip
   (4x6.25Gbit/s) definition, trade-offs, CDRs and
   tests
   2sd phase will target to provide ASIC capability


                              STMicroelectroics, ISD
AMICSA 2008, September 02     EADS-Astrium             32
                              Thales-Alénia Space
                            Thank you!


        See ST Rad-hard products at
      www.st.aerospace.com




                              STMicroelectroics, ISD
AMICSA 2008, September 02     EADS-Astrium             33
                              Thales-Alénia Space

				
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