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Advanced Hardware Technology
In ALMA Back End And Correlator
Fabio Biancat Marchet (1) – fmarchet@eso.org
Alain Baudry (2) – Alain.Baudry@obs.u-bordeaux1.fr
(1) European Southern Observatory (ESO), Munich, Germany
(2) Observatoire Aquitain des Sciences de l’Univers de Bordeaux, Bordeaux, France
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The ALMA Project: Atacama Large Millimeter Array
ALMA is an international astronomy facility. It is an equal partnership between Europe and North
America, in cooperation with the Republic of Chile, and it is funded in North America by the U.S.
National Science Foundation (NSF) in cooperation with the National Research Council of Canada
(NRC), and in Europe by the European Southern Observatory (ESO) and Spain. ALMA construction
and operations are led on behalf of North America by the National Radio Astronomy Observatory
(NRAO), which is managed by Associated Universities, Inc. (AUI) and on behalf of Europe by ESO.
ALMA will provide unprecedented performances in the sub-millimeter range for the study
of cold objects, representing the natural complement of the next generation of ground
and space based facilities operating in the optical-infrared domain.
•ALMA full operation is planned for 2011
•The observatory is designed to operate for 3 decades
•It will be composed by >50 12m Antennas
•The overall collecting Surface will exceed 5000 m2
•The Antennas can be relocated among > 170
locations to accommodate different types of
observations with:
•A compact Configuration ~150m diameter
•An extended Configuration ~ 14km diameter
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Site
•Atacama Desert, Northern-Chile
• Plateau de Chajnantor at 5000m altitude
• Observation Window: [30GHz, 1THz] in 10 bands
Example : Band 9 : 602 – 720GHz
Band 10 : 787 – 950GHz
Location selected for the extremely good Atmospheric properties
Drawbacks: low air density (<50%), lack of oxygen, remote
Consequently Operations at site severely limited impose:
• High Reliability (proven technologies, low thermal stress)
• Line Replaceable Unit (LRU) approach
• Remote diagnostics
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Instrument
Front End
Front-End Back End
Back-End fibre optique Correlator
Corrélateur
Front-End Back-End Corrélateur
Antenne
Système
Système
Computing
Informatique
Informatique Frequency
BE/Correlator Custom Developments Down-conversion
Quantification
X[k]
x[k]=x(kTe) Vs7
010
011
xq[k] Sampling
Vs6
Vs5
001
+
000
Vs4
111 Codage Quantization
Vs3
Vs2
LO Photomixers
110
k 101
x * t xk t kT
Vs1
e 100
k
Digital Filtering
+
X f e X ( f kf e)
R X
E X t X t
*
Correlation
Digitizer ASICS
DFT
S
2
Spectral Density
Fabio Biancat Marchet
Correlator ASICS
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Instrument
Antenna Side Technical Building Side
Front-End
Front End Back-End
Back End
Front-End Back-End
Antenne
Antenna Corrélateur
Correlator
Corrélateur
10 Cryogenic Front-End
Front End Back-End
Back End
Front-End Back-End
Cartridges
Antenne
Antenna
Cryogenic
Vessel Système
Système
Computing
Informatique
Informatique
• Cryogenic Receiver (one cartridge for each band)
• Conversion into the 4-12GHz band, two polarizations
• Digitization Transmission of the data to the TB
fs fi=Ifs-floI
G • Filtering
flo • Correlation
• Post-Processing
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
BE IF Processor
Front End
Front-End Back End
Back-End fibre optique Correlator
Corrélateur
Front-End Back-End Corrélateur
Antenne
Système
Système
Computing
Informatique
Informatique
Input 8GHz Band split in 4*2-4GHz sub-bands (two polarizations)
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
Data Transmission System (DTS)
Front End
Front-End Back End
Back-End fibre optique Correlator
Corrélateur
Front-End Back-End Corrélateur
Antenne
Système
Système
Computing
Informatique
Informatique
• Digitization 4Gsamples/s, 3 bits * 8 Channels
• Each channel De-multiplexed to 3* 16-bit parallel streams @250 MHz
• Further formatting converts to 12*10Gb/s serial streams
• Each driving a laser emitter with different “color” (DWDM)
• All 12 light beams mixed in one single fibre
• Net data rate from one Antenna: 96Gb/s (120GB/s coarse)
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Photonics Local Oscillator
Interferometric Operation of the Array requires extremely accurate phase reference. The
Reference shall be distributed synchronously to the Antennas with a phase stability
within 50fs.
•Two laser beams are phase-locked and distributed by a single fibre to the Antennae
•At the Antenna the beams are mixed to obtain the frequency-difference signal (in the
range 27-142GHz) as Local Oscillator source for the Heterodyne Receivers
•In order to compensate for Fibre length variations an interferometric Line Length
Corrector is implemented that measures the round-trip time and acts on a Fibre
Stretcher to compensate for length variations
CENTRAL CONTROL ROOM
Master Laser
Fib er Las er
Fib er Las er
Round-Trip Phase
Optic al C omb Correctio n
Optic al C
Gene ratoromb
Gene rator
Ph ase
Lo ase
Lo ck Phop
Slave L aser Lo ck Lo op
Ro und-Trip
Ex te rnal Ro und-Trip
Se rvo
Ex te rnal
Ca vity L ase r Se rvo
Ca vity L ase r
0.1-25km
Buried Fibre
ANTENNA RECEIVER CABIN
125MHz Ref
Ph ase
Lo ck Lo op
Cryo gen ic
Re cei ver
High Freq .
SIS Mix er Optica l Ref.
Gunn Dio de
3 AOM
Osci ll ator
HE MT
72 -84GHz
Amp li fie r
IF Out 4 -12GHz
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Photomixer
The key component performing the conversion of the incoming
light beams in a signal whose frequency is the difference is the
Photomixer Block
The Photomixer Block is based on a commercial photodiode
which is thinned/cut to match the high frequency requirements
and packaged in a precisely machined case that provides the
optical and electrical connections and the output waveguide/filter.
The device has been designed and manufactured at Rutherford
Appleton Labs (UK).
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Digitizer Assembly
• The Digitizer assembly within the Data Transmission System digitizes
a pair of 2-4GHz input signals at 4GHz sampling rate with 3-bit resolution.
Each bit stream is then de-multiplexed into one parallel 16-bit stream at 250MHz
There are 4 Digitizer assembly in each Antenna
Sampling/Digitization is performed by the custom Digitizer chip VEGA
De-multiplexing is performed by the custom De-multiplexer chip PHOBOS
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
ALMA : VEGA the Digitizer
+
D D
VH -
• Flash Architecture: 7 comparators, 8 levels, 3 bits
• Technology: BiCMOS 0.25µm SiGe (2.5V)
2 -4 G H z +
D D
A m p lif ie r -
O u tp u t
D D D0
b u ffe r
• Input: 2-4GHz (Gaussian noise)
D-Latches
OTA +
D D
-
• Sampling clock: 4GHz
Comparators
B andgap
DFFs
Amplifier
• Output: differential (LVDS)
+ E ncoder O u tp u t
A d a p te r D D D D D1
-
b u ffe r
a m p lifie r
Input
+
-
D D Clock • Output Gray code
Amplifierffeurt
D D
O u tp
bu
D2 • Self clock feature for easy test
4 GHz
C lo c k
b u ffe r
+
-
D D
• Power dissipation: 1.5W
• Bandwidth ripple <0.5dB
0 dBm
+
D D
VL -
Packaging is an issue
• Special High Frequency with low thermal resistance and
thermal drainVFQFPN 44 7x7x1mm
• Ball-bonding
•Parasitic elements :
Bonding : inductance ~1nH/mm
pad capacitance : ~0.3pF
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
ALMA : PHOBOS the De-multiplexer
Basically a shift-register that De-serializes 4 Gb/s into 16 bits @250MHz
Simplified block Diagram (1:4)
Same technology as VEGA, more complex
S0
layout, but less critical being full digital:
S1 •BiCMOS 0.25µm en SiGe (2.5V)
S2 • Input : LVDS)
S3
• Clocks: 4GHz et 250MHz
D2
• 16 differential outputs @ 250MHz
• Power dissipation 1.5W
4GHz
Clock
buffer
250MHz
Clock
buffer
Packaging
Difficult at the beginning: suitable package unavailable: direct bonding on PCB tried
but yield rather poor (60%)
Then VFQFPN 68 10x10x1mm became available
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
Digitizer Chips Development
• The ASICS have been fully designed at UB (Observatoire and IXL labs)
• Synthesis, analysis and simulation tools provided by STm
• Sample production with Multiple Project Wafer service to reduce costs
• Three Digitizer and two De-mux test versions before the final fully
engineered ones
• Overall cost ~1.6 MEur (50% for NRE)
• Development time ~3 years
• Series production complete (~1000 ADC and 3000 Demux produced)
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
Why ASIC?
• Operation speed and power consumption required a custom development
for both chips, not existing on the market any device fully matching the
requirements.
• The most critical one is the Digitizer, the market offers devices with
comparable performances in terms of speed/resolution, however not in the
required combination (as an example 6GHz-1bit or 1GHz/10bits). But in all
cases the power consumption is much higher.
• In order to rank the various flash ADC the figure of merit:
M = 2N*F/P (N resolution in bits, F sampling rate and P power) has been used
• VEGA shows M > 21 GHz/W while similar commercial devices (anyway not
meeting all requirements) have M around 1GHz/W
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Digitizer Test Bench
To Test and qualify the 4Gs/s + X 00[2 -0 ]
X 01[2 -0 ]
X 02[2 -0 ]
X 03[2 -0 ]
X 04[2 -0 ]
Demux assembly a test
X 05[2 -0 ]
X 06[2 -0 ]
X 07[2 -0 ]
X 08[2 -0 ]
X 09[2 -0 ] AUTOCORRELATOR
X 10[2 -0 ]
X 11[2 -0 ]
equipment was developed at
X 12[2 -0 ]
X 13[2 -0 ]
X 14[2 -0 ] MUX D A T A [2 3 -0 ]
X 15[2 -0 ]
CLO CK
IRAM.
R S T_C O R E N AB LE
P D F B U IL D E R
CLO CK
It is based on a scaled-down
R S T_P D F E N AB LE
version of the Correlator that CONTROL
L O G IC
PCLK
REQ
ACK
CLO CK
extracts the most significant Scaled Down Auto-correlator
M AS TE R R E S E T
parameters
DG Sub - Assembly
BB#1 DTEC Board
Input
DGS DGD
Noise Generator #1 #1
FPGA
BB#2
Input
DGS DGD
250M Hz
#2 #2
Clock
Input
Anti - Aliasing filter
4GHz 250M Hz
Clock Clock
Can be replaced by DGCK
Input Input
4 GHz
10M Hz
Synchro RF Generators
PC and Plug - In Digital
250 M Hz
Pattern Acquisition Board
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
Digitizer Test Results
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The ALMA Correlator
The core of the ALMA instrument, it performs the pre-processing on the raw
scientific data received from the Antennae at a rate of 96Gb/s per Antenna.
The basic operation is simple: multiply and accumulate samples from
different Antennae.
But must be performed quickly (125 MHz) and for all the possible Antenna
pairs
•Huge parallel and modular custom processor
•Installed in the Technical Building at 5000m: low power - high reliability
•Building block: custom chip that contains 4096 ‘LAGs’, each consisting of a
2-bit x 2-bit multiplier whose output is integrated in an accumulator.
•Total amount of Correlator chips is 32768.
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Correlator Chip
D3-X[1: 0]
F IG U R E 2
F I G U R E 5/2 6 /0 1
1
CORRELATOR CHIP MATRIX DIAGONAL 16
FROM
BLOCK 1 1
R3-M[15 :0] FULLACC 3
BLOCK O F 256 LAGS BLOCK O F 256 LAGS BLOCK O F 256 LAGS BLOCK O F 256 LAGS
TWO 2 - B IT INPUTS ANTENNA X M0
D- X 1:
6 4 4 -L[A G0 ] C O R R E L A T O R S U B - B L O C K
OVERSAM P3
FROM H O RI Z O N T A L AXIS
ANTENNA X M1 BLOCK 15 BLOCK 14 BLOCK 13 BLOCK 12 4 WRAP-BL K[15:12]
L E A D - B LK C O N C A T O V E R S A MP M1 M0 # D E L A YS 3
TO N EX T 0 R3-W[2: 0]
5/8/01
CH IP ROW 3 2
F I G UR E 4
F I G UR E 6 1 DUAL
2
4-1
MUX R 0 - M [ 1 : 0]
0 0 X 0 0 1 P i p e l i ne r e g i s t e r o n ly .
PU E T
1 6 - B I T O U T A N TT N N AO X + 3 M0
X 1 0 0 0 1 C O N C A T , N o n - O v e r s a m p le d LA EOR
N E X T C O R R E A N TT N N A X + 3
RNE C R REL K
C O R O E L A T OO R B L O CA T O R LAG 3 M1
2 5 6 -L A G 16-BIT RE S U L T S BUS
2/1/01 64-LAG X
CO R R E L A T O R 0 1 1 1 * 0 2 CONCAT, Oversampled 1 -X 0 : 0
( N E X T <D 25 : [ 1> ) ]
1/26/01 0 R 0 - M [ 3 : 2] (PLOADE) FROM BL OCK 7
DL
DIAGONAUMP TO STORAGE' 16 R2-M[15 :0]
FULLACC 2
BLOCK OF 256 LAGS
1 DUAL 5 -1 M U X BLOCK O F 256 LAGS 1 0 0 1 * 0 2 L LAD,
BLOCK O F 256 EAGS No n - O v e r s a m p l e d BLOCK O F 256 LAGS OVERSAM P2
D3-X[1: 0] TO 4-1 DUAL
Bi OC
R O W 0 , C O L 0 , w h Lc hK i m2p l i e s B L O C K 0 fo r th i s d ra w i n g .
1
BLOCK 112 MUX 0 2-1 2 BLOCK 10 1 6 BLOCK S E C O N D A R Y S T O R A G E R E G I S T E R
-BIT 9 BLOCK 8 4 WRAP-BL K[11:8]
MUX
64-STAGE SHIFT 1
R E G I S T ER 0 1 1 1 3 L E A D , Ov e r s a m p l e d ( S E E D E TA I L A )
3 C O R R E L AT O R R E S U L T S
S E L P [ 1 :0 ] S U B - B L OC K = x 1 (CKSS) 3 R2-W[2: 0]
2 OUTPUT BUS TO 4-WAY
where ROW -2 [ 1 : 0 ] f r o m
D0 X CONCAT = *
WRAPBLK0 N o t e: R 0,
F o r M 1 DMC L K 0 1 c o u l d b e us e d i n s t e a d o f 1 0 .
(Unless Lag 63) M U X ( S EE F I G U R E 4 )
previou s Block 16 BITS
x = 0 , 1 , 2, o r 0 WRAPBLK0 ANTENNA X+2 M0
of 256 Lags ( P R E V < 1 5: 0 > )
2
3 1 DUAL 1 6 - B I T OU T P U T F R O M P R EV I O U S C O R R E L A TO R ANTENNA X+2 M1
4-1 AG 0
L( U n l e s s L a g 6 3 ) L A G 1 LAG 2 LAG 3 LAG 4 LAG 5 LAG 6 - 62 LAG 63
D 2 MUX
E NB L B E
R D C L K( L A G L K X T E N S I O N PATH )
R 0 - M [ 5 : 4]
3
16-BIT RE S U L T S BUS
D1 -X [1 :0 ]
R E A D C LO C K E N A B L E T H IS S U B - B L O C K R D C L K E NB L ' \ 64-LAG CO R R E L A T O R 1 FR OM
C
5-BIT A CC U M U L A T O R 4-BIT R IP P L E - T H R U P R E -S C A L E R
0
1 4-1
0
PRDCLK
R 0 - M [ 7 : 6] 0
1 4-1
0
1 4-1 DIAGONAL 0
1 4-1
16 BIT BL OC K 3
2 MUX R1-M0 5 -1 M 2 X U X
U M R1-M0 2 MUX R1-M0 2 MUX R1-M0 RESULTS
(RN)
3 R1-M1 1 DUAL
4-1 DUAL 2
3
(CKSS) R1-M1
K
R D C L( A s y n c h r o n o u s R e s e t ) 3 R1-M1 0 3 R1-M1
OUTPUT
A C C U M U 1 2 T O M H z ECS E T K
L A5 R R L O C T O F I G U R E 7U L L A C C 1
64-LAGS s u b - b l o ck 0 64-LAGS s u b - b l o ck 0 64-LAGS s u b - b l o ck 0 64-LAGS s u b - b l o ck 0 F
2 MUX 0 2-1 1 4-1 T R I - S T A TE BUS
R --
614 M 2S T A G E SHIFT R E G I S T ER
0 R1-M2 MUX 0 0 R1-M2
MUX BUFFER
0 R1-M2 OS
5 7 L A G B L O C KV E R S A M P 1
1 5-1 R1-M3 1 5-1 R1-M3 1 5-1 R1-M3 1 5-1 R1-M3
2 SHIFT R EG 3 1 2 SHIFT R EG 2 SHIFT R EG 2 2 SHIFT R EG
MUX MUX MUX MUX
3 3 CONCAT = R0-W0 3 3O E
W R A P - B L K7 W R A P - B L K6 W R A P - B L K5 3 W R A P - B L K4
D
4
D D D D 4 4 4
0 (P
R 0 - W 0 L O A D E) DUMP TO STORAGE' 0 16
M U X
E
D U M P T O S T O R A1G D U A L R1-M[15 :0]
0 0 0 0
1 4-1 2 4-1 1 4-1 6 M O RR E G
E 4-1 6 MORE
CD
1 1 1
C C C C T T T T B L O C K S E LE C T E D
M U X
2 R1-M4 2 R1-M4 2 R1-M4 2 R1-M4
(CKBLKG) 3
MUX
R1-M5 4-1 3
MUX
R1-M5 3
MUX
R1-M5 STAGES 3
MUX
R1-M5 STAGES
2 MUX 1
GATED 1 25 MHz CLOCK 64-LAGS s u b - b l o ck 1
R 0 - M [ 9 : 8]
64-LAGS s u b - b l o ck 1 64-LAGS s u b - b l o ck 1 64-LAGS s u b - b l o ck 1
0 R1-M6 0 R1-M6 0 0 R1-M6 0 R1-M6
1 5-1 R1-M7 3 1 5-1 R1-M7 FULLACC 1 5-1 R1-M7 T S E L P [ 1 : 0] T 1 5-1 T
R1-M7 T4
GATED BY BLANKING 2 MUX
SHIFT R EG
C 2 MUX P R E - S C A LE R
SHIFT R EG
WILL NOT 16-BIT RE S U L T S B
2 UMS X
U
SHIFT R EG
2 MUX
SHIFT R EG
WRAP-BL K[7:4]
3 3 3 3
4 R1-W0 4 64
R 1 - W 0- C CNT LA BY 2
L A GO U O R R EI N T O R P A SS MODE 4 R1-W0 Pipeline register to ma t c h th e4 r e g i s t e1 - W 0
R r
R C _ T S T E6 4 with the gated clock on Figure 5. 3
0 R 0 - M [ 1 1 :1 0 ]
CONCAT 16-BIT RI P P L E - T H R U N C t e NB LE R K S E L E C T E D
o O U T OC a l so would need a
R1-W[2: 0]
5 -1 M U X
0 1 DUAL 0 0 0
D A T A I N P U T / O U T P U T S T O /F R O M B L O C K : 1 4-1 BLOCK 7 4-1 DUAL 2
1 4-1 B LO C K 6 1 4-1 BpL OeC K n e5 r e g i s t e r
ip li for the sam e1 -a
r4e 1 s o n . B LO C K 4
2 MUX L E ARD-- 8B LK
1 M (RN64) 2 CX
A M U C U M U1LA8 T O R R E S E T
R -M 2 MUX R1-M8
However it is
2
tM U X u s
R1-M8
1) T W O 2- B I T D A T A I N P UT S I G N A L S F R O M V E R T I C A L A X I S3 R1-M9 2 MUX 0 2-1 F U L L A C C14 M 9S T A G E
3 R -
6 - SHIFT R E G I S T ER
3 R1-M9 mit
TE6 t
R Co_ T S t e d 4 o prev n
e3 b R1-M9
2) T W O 2- B I T D A T A I N P UT S I G N A L S F R O M H O R I Z O N T A L A XI S MUX s u b c b l nct e n
- oo k 2 t io n . This n e c es s i t a t e s the
(P T ,0> A
T W O 2 - B I T D A T A O U T P U < 1 S I G N) L S O N V E R T I C A L A X I S 0 A C C U M 4U LL G ST O Rs u b RbEoSkE2T
64-LAGS s u b - b l o ck 2 64-LAGS s u b - b l o ck 2 64-LAGS 6 - AA - l c
3) R1-M10 3 1 0 R1-M10 0 R1-M10 0 R1-M10
4) (P LS PT H
T W O 2 - B I T D A T A O U T P U T S I G N AR O M O N ) O R I Z O N T A L A X I S 5 - 1
1 R1-M11 1 5-1 R 1 - C1O N
M 1 CAT = R0-W1 Note c h a n g i n5g1 t h 1 - M 1 1
1 - Re a lit n
P r o g r a m w o r d l b o w i, g R o n eT S T E c k =c0 c l e
C_ clo64 y slop t
1 -e
i5m 1 a f 1 - e 1r A s
Rt M 1 a ( y n c h ro n o u s R e s e t )
5) MS A IT ROM PU T
2 - B I T D A T A I N P U T S I G N B L S FP - I N L A ST B L O C K 2 MUX F 2U L UL A C C = 1
M X S P E C S H I F I EES
IFT R G A 25 BIT 2 MUX 256 lag readout. 2 MUX
6) 2 - B I T D A T A O U T P U T SI G N A L S T O N E X T B L O C K
3
4 R1-W1
SHIFT R EG 3
4 R1-W1
program word,
3
4
w i l1l W 1
R -
f o r S H nF o rEm a l
I T R G
operation. 3
4 R1-W1
SHIFT R EG
INSTEAD OF A 21 BIT PROMPT c P R O MeP Tm u x c h a n g e s P R O M PC _ T S T E 6 4 = 1
R T PROl t
f P R O M P T t e r f u n c t i o n a M P T es t . PROMPT PROMPT PROMPT
7) 1 6 - B IT O U T P U T R E S U LT S B U S 0 R0-W1
LS BIT P- I N P U T 2-BIT X 2-BIT 5-BIT aus , or fas
2 A C C U M U L AT O R .
2 WIDE M U L T I P L I E R B l a n k i ng n o r m a l l y 1 p l4ac1e dA D D E R t b e f or e t h 0e 1 m s . pu l s e .
DUAL
righ which m ig h t clock 256 ( t y pi c a l )
0
4-1
- F 1U L -L A C C d e f i n e d
4 1 on DEL 4
F i gu r e A Y DELAY 0
4-1 DELAY DELAY DELAY 0
4-1 DELAY CLOCKS DELAY DELAY
(Use
1
2 t h e R B- I1A S E D
MUX 1 M 2 2 MUX 2 MUX R1-M12 the 16 bi t 1
2 cMoXu n t 1 - r1 .
U Re M 2
125 MHz CLOCK
1
G A T E MUX
2 R1-M12
DUMP TO STORAGE 3 R1-M13
D E L A 3 E D B L A N R 0 - MG[ 1 3 : 1 2 ]
Y KIN for
3 the 256
R1-M13 Lag Block. 3 R1-M13 3 R1-M13
M U L T I P L IC A T I O N D BLANKING
64-LAGS 3
s u b - b l o ck 64-LAGS s u b - b l o ck 3 16-BIT RE S U L T S BUS 64-LAGS s u b - b l o ck 3 64-LAGS s u b - b l o ck 3
C L O C K GA T E
C O N T R O L IN P U T S T O B L O C K : 0 R1-M14 0 R1-M14 0 R1-M14 0 R1-M14
PRDCLK T A B L E5 .1
1 - SR e- e1 5
1 M 1 5-1 R 1 - 614 -
M 5 LAG CO R R E L A T O R 3 1 5-1 R1-M15 1 5-1 R1-M15
( D I < 1 , 0 >)
2 MUX
SHIFT R EG
2 MUX
SHIFT R EG C C 2 MUX
C SHIFT R EG C C 2 MUX
C SHIFT R EG C C
( F r o m 0Fi g u r e 8 )R 0 - M [ 1 5 : 1 4 ]
3 3 3 3
DELAYED BLANKING below.) R1-W2 R1-W2 R1-W2 R1-W2
C
4 4 4 4
SEQ DUMP TO STORAGE ( D E L A Y E D) DUMP E N AB L E
125 MHz CLOCK
S E Q A C C UM U L A T O R R E SM T .
ES 1 DUAL
5 -1 M UX
B I T D- I N P U T D2 -X [1 :0 ] TO
4-1 DUAL 2 2
BL OC K 8 2 MUX 0 2-1 TO NEXT BLOCK
R CL o
A ll d a ta N a th s T De twK S its w id e . B IROWD - I N P U T
LS T 1 MUX
64-STAGE SHIFT R E G I S T ER DUMP TO STORAGE xR
I p P U ar P IN b (BLOCK 1) ANTENNA X+1 M0
3 1 CKBLKG T h i s p r ov i d e s a n A s y n ch r o n o u s Jam L oa d
6 - B I T R ES U L T S BUS
DUM L
D U M P E N A BP E T O
L EC
S T O RSAEG E ' T BITS ( S E L [ 5: 0 ] )
ANTENNA Y M1 ANTENNA Y M0
CONCAT = R0-W2
xL
ANTENNA X+1 M1
125 MHz CLOCK N o S H I FT - O U T
R D C L K E N BL P T W O 2 - B IT I N P U T S R0-W2 LEAD-BLK determines if the 64 Lag B lo c k has an e x tr a delay stage at the A C nnM U L TR
b e g iC U i n g .A T O h e ReE S E a d e l a y s t a g e i s n e e d e d o n
xtrT
C l o c k in m i d d l e o f D um p t o F R O M V E RT I C A L A X I S D0 -X [1 :0 ] c l o c k fo r
the LEAD (as opposed to LAG) portion of the array. This p r ov i d e s a n A s y n ch r o n o u s R e s e t
Storage selection. P I P E L I NE R E G I S T E R S
P R O G R A M W O R D B IT S 0 0
Each 64 lag block has separate logic equations
0
for the CONCAT s ig n a l . If there is a wrap a r o un d input
0
from a previous DIAGONAL F R O M P R E V I Ol a g 6 3 .
US
1 4-1
2 1 4-1
block, th e logic e q u a ti o n s in the 64 lag DETAIL a s s u r e
block A1 4-1
there is no extra LEAD st a g e ( L E A D ends up e q 1 a4l 1 t o
u - 0 ).
2 MUX R0-M0
( P R O M P T) 2 MUX R0-M0 2 MUX R0-M0 2 MUX R0-M0 CH IP
W R A P - B L Ky y = Block 0, 1 , 2 , 3 ... 14, or 15 3 R0-M1
D 3 R0-M1
The s i g na l LEAD-BLK is separately d e O e r m iS T3d
tNE neA Gf o rO F h e HsE x 1 e e nB I T 5 6 ElC O N b l o cY s S a s RfA G E o w sE G I S T E R
E t T
R0-M1
i t6- , 2 S ag DAR k TO o l l R :
3 R0-M1
R x O V E R S AM P B l o c k s an d R o w s are d ef i n e d in F i g u re 2.
IL G
P - D A T A 6 4 - NAP SU T s u b - b l o ck 0
R C _ T S T E 64
64-LAGS
Based on
s u b - b l o ck
the two
0
p r o g ra m word bits LE A D L L and L E A DU R , the
64-LAGS
f o l l o wi n g
s u b - b l o ck 0
c o n f i g u r a ti o n s are d e s i r ed :
64-LAGS s u b - b l o ck 0
R x - M [ 1 5 :0 ] x = Row 0, 1, 2, or 3
0 R0-M2 0 R0-M2 0 R0-M2 0 R0-M2 (L AG E XT EN SI ON P AT H)
1 5-1 R0-M3 1 5-1 R0-M3 1 5-1 R0-M3 1 5-1 R0-M3
R x - W [ 2 : 0]
R x F U L L A CC
2
3
MUX
SHIFT R EG
C 2
3
MUX
SHIFT R EG 2
3
MUX
SHIFT R EG 2
3
MUX
SHIFT R EG
4 W R A P - B L K3 4 W R A P - B L K2 4 W R A P - B L K1 4 W R A P - B L K0
Card 1, Cards 0 & 3 B el o w C a r d D i a g on a l s Card 2, Cards 0 & 3 A bo v e C a r d D i a g on a l s
FULLACC 0
R C _ T S T E 64 LEAD-BLK LEADLL=1 LEADUR=1 LEADLL=0 LEADUR=0
S E L P [ 5 : 2] BLOCK=y A L L L E A DS ALL LAGS OVERSAM P0
0 0 0 0
LEADLL B L O C K S E L E C T1E D S E L P [ 1 : 0] FROM P R EV I O U S C O R R E L A TO R TO NEXT
T o T r i - S t a tXe B R 0 fMf e r O V E R S A MP
where 1 4- 1 4-1 1 4-1 1 4-1
LEADRR 2 MU u- 4 2 MUX R0-M4 B L O C M U1 5
2 K X R 0 - M 4B L O C K 1 4 BLOCK13 BLOCK12 B L O C KU X 5
2 M 1 R 0 - M 4B
LOCK14 BLOCK13 BLOCK12
y = 0 , 1 , . .. E ECO LKAR STO BLK E
L S A D - BN D = 1 Y L E A D -R A G = 1 R E G IS T E R L E A D3 0 L K = 0 Q
3 R0-M5 3 R0-M5 R0-M5 R0-M5
L E A D3- B L K = 1 L E A D - B L K= 1 -B 0
L E A D - B L K=D L E A D - B L K= 0 C -BL EL
L E A DO R R K = 0A
16 TR 0R M [ 1 5 : 0 ]
O -
or 15. 64-LAGS s u b - b l o ck 1 64-LAGS s u b - b l o ck 1 64-LAGS s u b - b l o ck 1 64-LAGS s u b - b l o ck 1
0 R0-M6 R D C L K E N BL B L K 0 R0-M6 BLOCK11
0 R 0 - M 6B L O C K 1 0 BLOCK9 BOUN 8
C L O C KT F R O M BLOCK11
0
15 - 1 R 0 - M 6B LOCK10 BLOCK9 B L O C K. S T
SEC 8 OR A G E
5-1 R0-M7 5-1 R0-M7 5-1 R0-M7 R0-M7
R D C L K E N BL P 1
2 U N B I A S EH DF T M E G L T I P L I C A T I O N
U TABLE M0 1
2 B M U X S F UD L M U L T M 1 S LI ITCRAGT I O N T A B L E
IA E L ACC IP H F E L E A D1- B L K = 1
2
L E A D - B L K= 1 L E A D - B L K= 1 L E A D - B L K= 1 L E A D1 B L K = 0
-
2
LEA
R D C L D - B L KS=H 0F T
K L E A D - B L K= 0 L E A D - B L K= 0
MS LS WEIGHT 3
MUX
S I R 3 3
MUX
SHIFT R EG R I P P L E - TH R U COUNTER 3
MUX
CI R EG REGISTER
4 R0-W0 4 A d d 90 ,W 0 t h e n d i v i d e b y 2
R - BLOCK7
4 R0-W0L
B OCK6 BLOCK5 BLOCK4 BLOCK7
4 R 0 - W 0L O C K 6
B BLOCK5 BLOCK4
4
READ C L OC K ENABLE THIS BLOCK F U L L A C C =1 SPECIFIES A 25 0 0 0 0
L E A D - B L K= 1 L E A D - B L K= 1 0L E A D - B L K = 1 L E A D - B L0 = 1
K L E A D - B0 K = 0 ( C K S D - B L K = 0
L LEA S) L E0 D - B L K = 0
A L E A D - B L K= 0
WRAP-BL K[3:0]
M U X
M U X
M U X
M U X
M U X
M U X
M U X
M U X
(DELAT
P - I N P U Y ED ) BIT 0 1 S T E0 D
IN A0 OF 1 2
A 1 1 10
B IT P-INPUT 01 00 11 10
BLOCK3 BLOCK2 BLOCK1 BLOCK0 BLOCK3 BLOCK2 BLOCK1 BLOCK0
2 3 2
DUM K 1
1L E A D - BB K =O C KE A1 - B LP = T O S T O R A G EL'E A D 1- B1- 1K = 0
0 0 0 0
0 F U1L A C C x + 3 A C C U M U L AT O R .
L 1 4-1 B LO C K 3 1 1 4-1 1 B LO C K 2 1 1 4-
L E A D1- B L1K = 1 L E A D - B L K= 1 L L 1 L D 1 4L L E A D - B L K= 0 L E1 D - B L K = 0
A B L O C L E A 0- B L K = 0
K D R0-W[2: 0]
F U L L A C C x= 1 ( x = R oV t h u m b e r )
+ w N for 25 bit 2 D D - D A T AT I N P U T
R0-M8 -INPU D 2- I UN P U T0 - M 8
R 2 R0-M8 (PLOADE) 2 R0-M8
3
MUX
R0-M9 D D3 M X
D
R0-M9 D D D D 3
MUX
D0 - M 9
R D D D D D 3
MUX
R0-M9D D
A c c u m u l at o r , Cross C o rr e l a t i o n Mode.
0 0 +1 0 R0-M10
01 64-LAGS
9
s u b - b l o ck 2
3 -3 -9 0
01 R0-M10
9 64-LAGS
6 3
s u b - b l o ck 2
0 0 R0-M10
64-LAGS s u b - b l o ck 2
R
R D C L K0 r eq u i0-M10
red d u r i6n -g A G D U M s u b - TlOc k S T O R A R E ' S H IL T I P L E X E R R I A LN T A T A T O
4 L S
P b o 25 7 M O G E M U F T . SE CO DRO L
0
5-1
D U M P 1E N A B L E '
R0-M11 1 5-1 R0-M11 1 5-1
Cards
R0-M11
0 and 3 On Card Diagonals 1 5-1 R0-M11
Not Used R E G I S T ER STAGES N E X T M UL T I P L E X E R
From
2 U
r e g i s t e r e d 3 iMn X u t p i n .
p 00 SHIFT R EG 3 1 -1 C- 3 C3
2 MUX
00 C 6 SHIFT R EG 5 C 4 C 3 C C
2
3
MUX
C R 0 - WL E A C L L =H1 F T
D S I G
C
R EL E A D U R = 0
C C C
2
3
MUX
C L E A D C SLH =F0 R E G L E A D U R = 1
L I T BI TS F OR R OW 0
4 R0-W1 E v e r y 1 .0 0 0 0 0 0 m s . 4 D U R 0P W 1 T O
M - STORAGE C4H I P ON DIAGONAL1 - L E AD S I N L O W E R L EF T H
C4 IP ON D 0 - A 1G O N A L - L E A D S I N U P P E R R I G H T
RI W
1 1 -1 SEQ DUMP TO STORAGE 19 B IT S CO MM ON T O AL L
-Vth 11 -3 -1 1 3 11 3 4 5 6 BLOCK15 BLOCK14 BLOCK13 BLOCK12 BLOCK15 BLOCK14 BLOCK13 BLOCK12
0 0
L E A D - B L K= 0
0
L E A D - B L K= 0 L E A D - B L K= 0 L E A D - B L K= 0 L E A D - B L K= 0
0
L E A D - B L K= 1 L E A D - B L K= 1 FO UR C OL UM NS
L E A D - B L K= 1
1
From
0
F i gu r e
-3
8 1 4-1
1 2 5 1M0H z C L O C K - 9 -3 3 9 1 10
4-1 0 3 6
Resets
9
co u n t e r when
1
K X
4-1
B L O C M U1 1 R 0 - M 1B L O C K 1 0 BLOCK9 BLOCK8
1
B L O C KU X 1
4-1
2 R0-M12 2 R0-M12 2 2 2 M 1 R 0 - M 1B L
2OCK10 BLOCK9 BLOCK8
MUX
O u3t p u t s e 0v e1r y
R -M 3 3
MUX
R -
U 3
A C0C M 1M U L A T O R RESET M
L E A D3- B L K = 1 R 0 -L 1 3A D - B L K = 0
E L E A D - B L K= 0 L E A D - B L K= 0 L E A D3 B L K = 0
- R0-M13
L E A D - B L K= 0 L E A D - B L K= 1 4 AD DI TI ON AL B IT S FO R
L E A D - B L K= 1
high. ables
E nP R O V I D E H G E b oF
A N E X T R A B I T O F D E L A Y A T E AC6 4 - L AS ST A G s u ,- b lI c k 3IN O V E R S A M P L E MO D E .
SEQ 4 C A S
6A - L CGU M A b bR
U L s u T-O l o c kR E S E T
blanking
0 R0-M14
3
0 R0-M14
64-LAGS s u b - b l o ck
counter
3
when low. BLOCK7
0 R 0 - M 1B L O C K 6
4 BLOCK5 BLOCK4 BLOCK7
0 R 0 - M 1B L
4OCK6
64-LAGS
BLOCK5
s u b - b l o ck 3
BLOCK4 TH E FO UR 5 -1 M UX ES
- v
i n1t e5r 1 a l . 0 - M 1 5
R 1 5-1 R0-M15 5- M
L E A D1- B L1K = 1 R 0 -L 1 5A D - B L K = 1
E L E A D - B L K= 0 L E A D - B L K= 0 L E A D 1 B5L 1 = 0
- -K R0-M15
L E A D - B L K= 0 L E A D - B L K= 0 L E A D - B L K= 1
2
3
MUX NOTE: T h e R Et h r e e f l i p- f l o p s a n d t h e t w o m u x e s U X w i th
SHIFT G
M 2
3 SHIFT R EG
2
3
MUX
SHIFT R EG
2
3
MUX
SHIFT R EG
4 R0-W2 DELAYED BLANKING 4 L -Y
D E R 0A W 2 E D BLANKING BL CK3
O
4 B
R0-W2L OCK2 BLOCK1 BLOCK0 BL OC
4 K3 R 0 - W 2L
B OCK2 BLOCK1 BLOCK0
M 1 a n d M 0 f o r m a v a r ia b l e 1 t o 3 s ta g e d e l a y l i n e. L E A D - B L K= 1 L E A D - B L K= 1 L E A D - B L K= 1 L E A D - B L K= 0 L E A D - B L K= 0 L E A D - B L K= 0 L E A D - B L K= 0 L E A D - B L K= 0
D1 -X [1 :0 ] TO
I f i t he l p s c h i p d e l ay s , t h e M 1 o r t h e M 0 m u x c oOul d S A M P
VER A p p r o x im a t e G a t e C o u nt C a l c u l a t i o n
S i m i l i a rl y , OVERSAMP = OVERSAMPx BL OC K 4
ROW 0 b e m o v ed t o t h e c e n t er f l i p - f l o p . See the table at H O R IZ O N T A L (X ) A X IS
Where x represents Row number E a c h L ag - 4 5 6 g a t e s When the chip is on a Card 0 or 3 d ia g o n a l , the s el f products on the chip d i a go n a l s
as d e f i ne d in Figure 2. yL yR t h e t o p o f t h e p a g e fo r t h e d e f i n i ti o n o f M 1 a n d M 0 . D e l a y Fl i p - F l o p s - 1 6 g a t e s have L E AD - B L K = 0. T hi s means there is no extra de l a y stage i n se r t e d .
ANTENNA X M0
V E R T IC A L (Y ) A X IS ANTENNA X M1
ANTENNA Y+3 M1 ANTENNA Y+3 M0 ANTENNA Y+2 M1 ANTENNA Y+2 M0 ANTENNA Y+1 M1 ANTENNA Y+1 M0 ANTENNA Y M1 ANTENNA Y M0
CO L 3 CO L 2 CO L 1 CO L 0
4 7 2 g a te s * 6 4 L a g s * 6 4 b l o c k s = 1, 9 3 3 , 3 1 2 g a t e s
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The Correlator Chip
•Well established CMOS 0.25 micron technology
• 2*106 Gates
• 212 LAG blocks
•Clock: 125 MHz
•Voltage supply: 1.8V
•Power dissipation: 1.6 W
•Package: Standard 240-pin PQFP
•Total need: 215 chips
DEVELOPMENT PROCESS
•Specification defined at NRAO
•Design, Prototyping and Production by a Specialized company
•The process took three years
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The ALMA Correlator
•34*109 Millions of op. per second
(Integer, low resolution…)
•170 kW Power dissipation
•32 Full size cabinets
•16000 cables on the backplane (~50 km)
•First Quadrant Complete
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
The ALMA Tunable Filter Bank
The Tunable Filter Bank band-pass filters the rough
data before they are processed by the Correlator.
Each FIR Filter is implemented as two stage
Real/Imaginary architecture.
The second stage can be configured both to tune
the centre frequency and the bandwidth
The data rate is 125MHz
FIR filter FIR filter
6 bits
128 taps
(8 bit encoded)
8 bits
125 Ms/s
64 taps
(9 bit encoded) 9 bits
The TFB design is a shared effort between:
Digital LO
Real part
Low Pass Low Pass 62.5 Ms/s •Université de Bordeaux - HW/Firmware design
•Osservatorio Astr. di Arcetri – Algorithm design
4Gs/s and Mixer
Baseband Output
Input Complex to Real Requantization Signal
x
Signal
32* 3 bits
DDS
•ASTRON – Test Software
Conversion
LO
FIR filter FIR filter 62.5 Ms/s
6 bits
Imag. part 128 taps
(8 bit encoded)
8 bits
125 Ms/s
64 taps
(9 bit encoded)
9 bits
•Prototypes based on FPGA are currently under test.
Low Pass Low Pass
•Each board implements 32 filters in 16 chips
•512 boards are needed
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
ALMA Tunable Filter Bank Chip
ASIC or FPGA?
The high complexity on one side and the relatively low amount of parts
required (8192) does not justify the investment for a complete ASIC design.
On the other hand implementation through FPGA is expensive and not
efficient from the power dissipation point of view
Solutions under investigation/comparison:
1.Semi-custom design using the “Hard Copy” process to convert the FPGA
configuration on Si, provided by the FPGA manufacturer: limited NRE, lower
unit price, lower dissipation. Important limitation: frozen design.
2.Next Generation of FPGA, smaller and less power consuming
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
Conclusion
Remote access, harsh environment and long operating life call for well
established technologies.
On the other side the extremely demanding technical requirements can only
be met with innovative approaches.
Finding the proper balance between the two opposite aspects is one of the
challenges of ALMA.
All the presented new developments have been successfully tested in the lab
and tests on sky at the Antenna Test Facility in Socorro New-Mexico (2000m)
are under preparation.
Only the final operation at the site, facing the actual environmental conditions
will confirm whether a right trade-off between innovation and reliability has
been satisfactorily achieved.
Fabio Biancat Marchet
Alain Baudry Advanced Hardware Technology In ALMA Back End And Correlator
