EtronTech EM638325 (2M x 32 Synchronous DRAM (SDRAM)) by hamada1331

VIEWS: 6 PAGES: 73

									EtronTech                                                                                                                     EM638325
                                                2M x 32 Synchronous DRAM (SDRAM)
                                                                                                          Preliminary (Rev 0.8 Nov/2001)

Features
                                                              Ordering Information
• Clock rate: 285/250/200/183/166
               /143/125 MHz                                           Part Number                          Frequency                           Package

• Fully synchronous operation                                   EM638325TS-3.5                                  285MHz                          TSOP II
                                                                EM638325TS-4                                    250MHz                          TSOP II
• Internal pipelined architecture
                                                                EM638325TS-5                                    200MHz                          TSOP II
• Four internal banks (512K x 32bit x 4bank)
                                                                EM638325TS-5.5                                  183MHz                          TSOP II
• Programmable Mode                                             EM638325TS-6                                    166MHz                          TSOP II
  - CAS# Latency: 2 or 3                                        EM638325TS-7                                    143MHz                          TSOP II
  - Burst Length: 1, 2, 4, 8, or full page                      EM638325TS-8                                    125MHz                          TSOP II
  - Burst Type: interleaved or linear burst
  - Burst-Read-Single-Write
• Burst stop function                                                 Part Number                          Frequency                           Package
• Individual byte controlled by DQM0-3                          EM638325VF-3.5                                  285MHz                         10x11 BGA
• Auto Refresh and Self Refresh                                 EM638325VF-4                                    250MHz                         10x11 BGA

• 4096 refresh cycles/64ms                                      EM638325VF-5                                    200MHz                         10x11 BGA
                                                                                                                                               10x11 BGA
• Single +3.3V ± 0.3V power supply                              EM638325VF-5.5                                  183MHz
                                                                EM638325VF-6                                    166MHz                         10x11 BGA
• Interface: LVTTL
                                                                EM638325VF-7                                    143MHz                         10x11 BGA
• Package: 400 x 875 mil, 86 Pin TSOP II,                                                                                                      10x11 BGA
                                                                EM638325VF-8                                    125MHz
   0.50mm pin pitch
• Package: 10 x 11 mm,90 ball BGA,0.65mm                                 1          2         3       4     5     6   7      8        9         10
   ball pitch
                                                                 A       VS S      DQ 1 5   VS S Q                        VD D Q     DQ 0      VDD
Pin Assignment (Top View)
                                                                  B      DQ 1 4    DQ 1 3   VD D Q                         VS S Q    DQ 2       DQ 1

         VDD    1      86    VSS
         DQ0    2      85    DQ15                                 C     DQ 1 2              VS S Q
                                                                                   DQ 1 1                                  VD D Q     DQ 4      DQ 3
       VDDQ     3      84    VSSQ
         DQ1    4      83    DQ14
         DQ2    5      82    DQ13
       VSSQ     6      81    VDDQ                                 D      DQ 1 0     DQ 9     VD D Q                        VS S Q     DQ 6      DQ 5
         DQ3    7      80    DQ12
         DQ4    8      79    DQ11
       VDDQ     9      78    VSSQ                                 E     DQ 8        NC      VS S                           VDD        NC        DQ 7
         DQ5    10     77    DQ10
         DQ6    11     76    DQ9
       VSSQ     12     75    VDDQ                                 F     DQM 1      NC         NC                            CA S       WE      DQM 0
         DQ7    13     74    DQ8
           NC   14     73    NC
         VDD    15     72    VSS
       DQM0     16     71    DQM1                                G        NC        CK E     CLK                            NC        CS        RA S

         /WE    17     70    NC
        /CAS    18     69    NC
                                                                  H       NC        A9        A8                                                 NC
        /RAS    19     68    CLK                                                                                            BS0       NC
          /CS   20     67    CKE
           NC   21     66    A9
         BS0    22     65    A8                                   J       A5        A6       A7                              BS1      A1 0       A0
         BS1    23     64    A7
      A10/AP    24     63    A6
           A0   25     62    A5
           A1   26     61    A4
                                                                  K      DQM 3      A3        A4                             A1       A2        DQM 2

           A2   27     60    A3
       DQM2     28     59    DQM3
         VDD    29           VSS
                                                                  L      DQ 3 1      NC       VS S                          VDD        NC       DQ 1 6
                       58
           NC   30     57    NC
       DQ16     31     56    DQ31
       VSSQ     32     55    VDDQ                                 M      DQ 2 9    DQ 3 0   VD D Q                          VS S Q    DQ 1 7    DQ 1 8
       DQ17     33     54    DQ30
       DQ18     34     53    DQ29
       VDDQ     35     52    VSSQ                                 N      DQ 2 7    DQ 2 8   VS S Q
                                                                                                                           VD D Q    DQ 1 9     DQ 2 0
       DQ19     36     51    DQ28
       DQ20     37     50    DQ27
       VSSQ     38     49    VDDQ
       DQ21     39           DQ26
                                                                  P     DQ 2 5    DQ 2 6    VD D Q                          VS S Q    DQ 2 1    DQ 2 2
                       48
       DQ22     40     47    DQ25
       VDDQ     41     46    VSSQ
                                                                                  DQ 2 4    VS S Q
       DQ23     42     45    DQ24                                 R     VS S                                               VD D Q    DQ 2 3      VDD
         VDD    43     44    VSS



Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345       FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech                                                 2Mega x 32                               SDRAM                  EM638325
Overview
      The EM638325 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured
as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number
of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then
followed by a Read or Write command.
      The EM638325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.
      By having a programmable mode register, the system can choose the most suitable modes to maximize its
performance. These devices are well suited for applications requiring high memory bandwidth.


Block Diagram

                                                                                                 Colum n     De coder




                                                                      Row Decoder
                                                                                                2048 X 256 X 32
                                                                                                  CELL ARRAY
                                                                                                    (BANK #0)

                                                                                                 Sense      Ampl ifier


                           DLL          C O N TR O L
      CL K
                         C LO C K         S IG N A L
                        B U FFE R     G E N E R A TO R
      CKE
                                                                                                 Sense      Ampl ifier
                                                                    Row Decoder




      C S#
      R A S#         COMMAND                                                                    2048 X 256 X 32
      C A S#         D EC O D ER                                                                  CELL ARRAY
      W E#                                  M ODE                                                   (BANK #1)
                                         R E G IS T E R
                                                                                                Colum n      De coder

                      CO LU MN
                     C O U N TER
 A 1 0/A P


                                                                                                Colum n      De coder
                                                                    Row Decoder




                                                                                                2048 X 256 X 32
                    A D D R E SS                                                                  CELL ARRAY
A 0
                     B U FFE R                                                                      (BANK #2)
A 9
B S0                                                                                            Sense      Ampl ifier
B S1

                     R E FR E SH
                     C O U N TER



                                                                                                  Sense      Ampl ifier
                                                                                  Row Decoder




                                       DQ                                                        2048 X 256 X 32
                                    B U FFE R                                                      CELL ARRAY

                D
               DQ0                                                                                   (BANK #3)

               D Q 31                                                                            Colum n      De coder



                                     D Q M 0~ 3




Preliminary                                                 2                                                 Rev 0.8        Nov 2001
EtronTech                                      2Mega x 32          SDRAM              EM638325
Pin Descriptions

                                   Table 1. Pin Details of EM638325

Symbol Type Description
 CLK     Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
               positive edge of CLK. CLK also increments the internal burst counter and controls the
               output registers.
 CKE     Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
               low synchronously with clock(set-up and hold time same as other inputs), the internal clock
               is suspended from the next clock cycle and the state of output and burst address is frozen
               as long as the CKE remains low. When all banks are in the idle state, deactivating the clock
               controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
               after the device enters Power Down and Self Refresh modes, where CKE becomes
               asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
               during Power Down and Self Refresh modes, providing low standby power.
 BS0,    Input Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or
 BS1           BankPrecharge command is being applied. BS is also used to program the 11th bit of the
               Mode and Special Mode registers.
A0-A10 Input Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-
             A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge)
             to select one location out of the 256K available in the respective bank. During a Precharge
             command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).
             The address inputs also provide the op-code during a Mode Register Set or Special Mode
             Register Set command.
 CS#     Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
               decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
               bank selection on systems with multiple banks. It is considered part of the command code.
 RAS#    Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction
               with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
               and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
               command or the Precharge command is selected by the WE# signal. When the WE# is
               asserted "HIGH," the BankActivate command is selected and the bank designated by BS is
               turned on to the active state. When the WE# is asserted "LOW," the Precharge command is
               selected and the bank designated by BS is switched to the idle state after the precharge
               operation.
 CAS#    Input Column Address Strobe: The CAS# signal              defines the operation commands in
               conjunction with the RAS# and WE# signals and      is latched at the positive edges of CLK.
               When RAS# is held "HIGH" and CS# is asserted       "LOW," the column access is started by
               asserting CAS# "LOW." Then, the Read or Write      command is selected by asserting WE#
               "LOW" or "HIGH."
 WE#     Input Write Enable: The WE# signal defines the operation commands in conjunction with the
               RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
               used to select the BankActivate or Precharge command and Read or Write command.
DQM0 - Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls.
DQM3         The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input data is
             masked when DQM is sampled HIGH during a write cycle. Output data is masked (two-
             clock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31-
             DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
 DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of
 DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes.


Preliminary                                         3                    Rev 0.8               Nov 2001
EtronTech                                    2Mega x 32        SDRAM              EM638325
  NC      -    No Connect: These pins should be left unconnected.
 VDDQ   Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
 VSSQ   Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
 VDD    Supply Power Supply: +3.3V±0.3V
  VSS   Supply Ground




Preliminary                                      4                   Rev 0.8            Nov 2001
EtronTech                                              2Mega x 32    SDRAM                 EM638325
Operation Mode
    Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
                                     Table 2. Truth Table (Note (1), (2) )

        Command              State         CKEn-1 CKEn DQM(6) BS0,1 A10       A9-0    CS# RAS# CAS# WE#
BankActivate                 Idle(3)         H     X     X     V     Row address       L    L   H    H
BankPrecharge                 Any            H     X     X     V     L         X       L    L   H    L
PrechargeAll                  Any            H     X     X     X     H         X       L    L   H    L
Write                      Active(3)         H     X     X     V     L     Column      L    H   L    L
                                                                           address
Write and AutoPrecharge    Active(3)         H     X     X     V     H                 L    H   L    L
                                                                          (A0 ~ A7)
Read                       Active(3)         H     X     X     V     L     Column      L    H   L    H
                                                                           address
Read and Autoprecharge     Active(3)         H     X     X     V     H                 L    H   L    H
                                                                          (A0 ~ A7)
Mode Register Set             Idle           H     X     X          OP code            L    L   L    L
No-Operation                  Any            H     X     X     X     X         X       L    H   H    H
Burst Stop                 Active(4)         H     X     X     X     X         X       L    H   H    L
Device Deselect               Any            H     X     X     X     X         X      H     X   X    X
AutoRefresh                   Idle           H     H     X     X     X         X       L    L   L    H
SelfRefresh Entry             Idle           H     L     X     X     X         X       L    L   L    H
SelfRefresh Exit              Idle           L     H     X     X     X         X      H     X   X    X
                           (SelfRefresh)                                               L    H   H    H
Clock Suspend Mode Entry     Active          H     L     X     X     X         X       X    X   X    X
Power Down Mode Entry        Any(5)          H     L     X     X     X         X      H     X   X    X
                                                                                       L    H   H    H
Clock Suspend Mode Exit      Active          L     H     X     X     X         X       X    X   X    X
Power Down Mode Exit          Any            L     H     X     X     X         X      H     X   X    X
                           (PowerDown)                                                 L    H   H    H
Data Write/Output Enable     Active          H     X     L     X     X         X       X    X   X    X
Data Mask/Output Disable Active        H        X      H       X    X     X        X    X    X       X
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high
      2. CKEn signal is input level when commands are provided.
         CKEn-1 signal is input level one clock cycle before the commands are provided.
      3. These are states of bank designated by BS signal.
      4. Device state is 1, 2, 4, 8, and full page burst operation.
      5. Power Down Mode can not enter in the burst operation.
         When this command is asserted in the burst cycle, device state is clock suspend mode.
      6. DQM0-3




Preliminary                                              5                 Rev 0.8              Nov 2001
EtronTech                                                 2Mega x 32                          SDRAM                       EM638325
Commands
  1     BankActivate
        (RAS# = "L", CAS# = "H", WE# = "H", BS = Bank, A0-A10 = Row Address)
             The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select)
        signal. By latching the row address on A0 to A10 at the time of this command, the selected row
        access is initiated. The read or write operation in the same bank can occur after a time delay of
        tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row
        in the same bank can only be issued after the previous active row has been precharged (refer to the
        following figure). The minimum time interval between successive BankActivate commands to the
        same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares
        part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of
        the four banks. tRRD(min.) specifies the minimum time required between activating different banks.
        After this command is used, the Write command and the Block Write command perform the no mask
        write operation.
                   T0          T1              T2        T3                                    Tn+3             Tn+4        Tn+5              Tn+6


  CLK                                                                     ..............


  ADDRESS         Bank A                                 Bank A          ..............       Bank B                                        Bank A
                 Row Addr.                              Col Addr.                            Row Addr.                                     Row Addr.
                             RAS# - CAS# delay (tRCD)                                                      RAS# - RAS# delay time (tRRD)

  COM M AND       Bank A         NOP           NOP
                                                         R/W A with      ..............        Bank B           NOP           NOP           Bank A
                  Activate                              AutoPrecharge                          Activate                                     Activate
                                                              RAS# Cycle time (tRC)

                                                                                           AutoPrecharge
                                                                                               Begin
        : "H" or "L"
                       BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)

  2     BankPrecharge command
        (RAS# = "L", CAS# = "H", WE# = "L", BS = Bank, A10 = "L", A0-A9 = Don't care)
             The BankPrecharge command precharges the bank disignated by BS0,1 signal. The
        precharged bank is switched from the active state to the idle state. This command can be asserted
        anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The
        maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function
        must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged
        bank is still in the idle state and is ready to be activated again.

  3     PrechargeAll command
        (RAS# = "L", CAS# = "H", WE# = "L", BS = Don’t care, A10 = "H", A0-A9 = Don't care)
            The PrechargeAll command precharges all the four banks simultaneously and can be issued
        even if all banks are not in the active state. All banks are then switched to the idle state.

  4     Read command
        (RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "L", A0-A7 = Column Address)
             The Read command is used to read a burst of data on consecutive clock cycles from an active
        row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
        issued. During read bursts, the valid data-out element from the starting column address will be
        available following the CAS# latency after the issue of the Read command. Each subsequent data-
        out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
        into high-impedance at the end of the burst unless other command is initiated. The burst length,
        burst sequence, and CAS# latency are determined by the mode register which is already
        programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
        column 0 and continue).




Preliminary                                                        6                                      Rev 0.8                     Nov 2001
EtronTech                                                         2Mega x 32                      SDRAM                       EM638325
                     T0         T1            T2             T3               T4             T5               T6             T7             T8



CLK

COMMAND
                 READ A         NOP           NOP            NOP              NOP            NOP              NOP             NOP       NOP


CAS# latency=2                                DOUT A0        DOUT A1         DOUT A2         DOUT A3
tCK2, DQ's


CAS# latency=3                                               DOUT A0         DOUT A1         DOUT A2         DOUT A3
tCK3, DQ's

                               Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3)


                The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
          (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
          may be interrupted by a subsequent Read or Write command to the same bank or the other active
          bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
          command to the same bank too. The interrupt coming from the Read command can occur on any
          clock cycle following a previous Read command (refer to the following figure).
                          T0          T1           T2             T3                T4             T5               T6            T7             T8


    CLK


    COMMAND           READ A         READ B         NOP            NOP              NOP            NOP              NOP           NOP            NOP


    CAS# latency=2                                 DOUT A0        DOUT B0          DOUT B1        DOUT B2          DOUT B3
    tCK2, DQ's

    CAS# latency=3
    tCK3, DQ's                                                     DOUT A0         DOUT B0         DOUT B1         DOUT B2        DOUT B3



                           Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)


               The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
          a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
          command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
          single cycle with high-impedance on the DQ pins must occur between the last read data and the
          Write command (refer to the following three figures). If the data output of the burst read occurs at the
          second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
          Write command to avoid internal bus contention.




Preliminary                                                              7                               Rev 0.8                        Nov 2001
EtronTech                                                          2Mega x 32                       SDRAM                         EM638325
                       T0           T1          T2            T3               T4              T5                  T6            T7             T8


CLK


DQM



COMMAND                NOP          READ A      NOP            NOP             NOP              NOP              WRITE B         NOP            NOP


DQ's                                                                       DOUT A0                                 DINB 0        DINB1          DINB 2
                                                                                      Must be Hi-Z before
                                                                                      the Write Command
              : "H" or "L"
                                   Read to Write Interval (Burst Length                   
 4, CAS# Latency = 3)
                             T0          T1           T2           T3                T4              T5                  T6           T7              T8


      CLK
                                                                                       1 Clk Interval

      DQM



      COMMAND                                     BANKA                             READ A           WRITE A
                             NOP          NOP    ACTIVATE            NOP                                                 NOP           NOP            NOP



      CAS# latency=2
      tCK2, DQ's                                                                                        DIN A0       DIN A1            DIN A2        DIN A3
       : "H" or "L"

                                   Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)


                             T0          T1           T2           T3                T4              T5                  T6           T7              T8


      CLK

      DQM



      COMMAND                NOP          NOP        READ A         NOP              NOP            WRITE B              NOP           NOP            NOP


      CAS# latency=2
      tCK2, DQ's                                                                                        DIN B0          DIN B1         DIN B2        DIN B3

            : "H" or "L"
                                   Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)


                A read burst without the auto precharge function may be interrupted by a BankPrecharge/
            PrechargeAll command to the same bank. The following figure shows the optimum time that
            BankPrecharge/ PrechargeAll command is issued in different CAS# latency.




Preliminary                                                                8                                     Rev 0.8                        Nov 2001
EtronTech                                                          2Mega x 32                       SDRAM                     EM638325
                 T0            T1               T2            T3                T4             T5                 T6         T7          T8

CLK


ADDRESS          Bank,                                                                                                       Bank,
                 Col A                                                        Bank(s)                                        Row
                                                                                                        tRP

COMMAND          READ A          NOP            NOP            NOP            Precharge          NOP              NOP        Activate    NOP



CAS# latency=2
                                              DOUT A0          DOUT A1        DOUT A2           DOUT A3
tCK2, DQ's


CAS# latency=3
                                                              DOUT A0           DOUT A1       DOUT A2             DOUT A3
tCK3, DQ's

                                              Read to Precharge (CAS# Latency = 2, 3)

    5     Read and AutoPrecharge command
          (RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address)
               The Read and AutoPrecharge command automatically performs the precharge operation after
          the read operation. Once this command is given, any subsequent command cannot occur within a
          time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
          command and the auto precharge function is ignored.

    6     Write command
          (RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address)
               The Write command is used to write a burst of data on consecutive clock cycles from an active
          row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
          issued. During write bursts, the first valid data-in element will be registered coincident with the Write
          command. Subsequent data elements will be registered on each successive positive clock edge
          (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
          another command is initiated. The burst length and burst sequence are determined by the mode
          register, which is already programmed. A full-page burst will continue until terminated (at the end of
          the page it will wrap to column 0 and continue).
                      T0             T1              T2             T3               T4               T5               T6         T7          T8

    CLK


    COM M AND            NOP        WRITE A           NOP           NOP              NOP              NOP              NOP        NOP         NOP



    DQ0 - DQ3                       DIN A0           DIN A1        DIN A2         DIN A3            don't care


                  The first data element and the write                                    Extra data is masked.
                  are registered on the same clock edge.


                           Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)


               A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
          BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
          coming from Write command can occur on any clock cycle following the previous Write command
          (refer to the following figure).




Preliminary                                                               9                                   Rev 0.8                   Nov 2001
EtronTech                                                                         2Mega x 32                       SDRAM                           EM638325
                       T0             T1                  T2                 T3                T4             T5              T6              T7              T8

CLK


COM MAND               NOP            WRITE A            WRITE B             NOP               NOP            NOP             NOP             NOP             NOP

                                           1 Clk Interval

DQ's                                  DIN A0             DIN B0          DIN B1            DIN B2           DIN B3

                            Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)

                 The Read command that interrupts a write burst without auto precharge function should be
            issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
            data contention, input data must be removed from the DQs at least one clock cycle before the first
            read data appears on the outputs (refer to the following figure). Once the Read command is
            registered, the data inputs will be ignored and writes will not be executed.
                            T0               T1                 T2                 T3                T4             T5                T6            T7               T8

      CLK


      COMMAND                NOP            WRITE A            READ B              NOP               NOP             NOP              NOP            NOP             NOP


      CAS# latency=2
                                             DIN A0            don't care                            DOUT B0          DOUT B1         DOUT B2       DOUT B3
      tCK2, DQ's


      CAS# latency=3
      tCK3, DQ's                              DIN A0           don't care         don't care                         DOUT B0          DOUT B1        DOUT B2         DOUT B3


                                                                                                           Input data must be removed from the DQ's at least one clock
                                                                                                           cycle before the Read data appears on the outputs to avoid
                                       Input data for the write is masked.
                                                                                                           data contention.


                             Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)

                 The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
            precharge function should be issued m cycles after the clock edge in which the last data-in element
            is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
            signals must be used to mask input data, starting with the clock edge following the last data-in
            element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
            entered (refer to the following figure).
                                 T0                T1                   T2                 T3                  T4                T5                 T6

      CLK


      DQM

                                                                                                     tRP

      COMMAND                WRITE                NOP                Precharge           NOP                NOP             Activate               NOP


                             BANK
      ADDRESS                                                     BANK (S)                                                    ROW
                             COL n
                                                            tWR

      DQ                     DIN                  DIN
                              n                   n+ 1


            : don't care
              Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
                                                                            Write to Precharge


Preliminary                                                                             10                                 Rev 0.8                            Nov 2001
EtronTech                                              2Mega x 32             SDRAM                       EM638325
 7         Write and AutoPrecharge command (refer to the following figure)
           (RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address)
                The Write and AutoPrecharge command performs the precharge operation automatically after
           the write operation. Once this command is given, any subsequent command can not occur within a
           time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
           performed in this command and the auto precharge function is ignored.
                           T0           T1     T2      T3             T4      T5              T6             T7                T8


     CLK


     COMMAND              Bank A         NOP   NOP    Write A        NOP       NOP            NOP              NOP             NOP
                         Activate                    AutoPrecharge

                                                                                   tDAL
     CAS# latency=2
     tCK2, DQ's
                                                      DIN A0         DIN A1
                                                                              *
                                                                                                tDAL
     CAS# latency=3
     tCK3, DQ's                                       DIN A0         DIN A1
                                                                               *
                      tDAL= tWR + tRP
                                                                              *Begin AutoPrecharge
                                                                               Bank can be reactivated at completion of tDAL
                         Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)

     8     Mode Register Set command
           (RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A10-A0 = Register Data)
                The mode register stores the data for controlling the various operating modes of SDRAM. The
           Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
           Length in the Mode register to make SDRAM useful for a variety of different applications. The default
           values of the Mode Register after power-up are undefined; therefore this command must be issued
           at the power-up sequence. The state of pins BS0,1 and A10~A0 in the same cycle is the data written
           to the mode register. One clock cycle is required to complete the write in the mode register (refer to
           the following figure). The contents of the mode register can be changed using the same command
           and the clock cycle requirements during operation as long as all banks are in the idle state.




Preliminary                                                    11                     Rev 0.8                           Nov 2001
EtronTech                                                       2Mega x 32                 SDRAM                        EM638325
                    T0     T1          T2          T3          T4         T5         T6        T7        T8        T9        T10

 CLK

                         tCK2

CKE
                                                            Clock min.

CS#


RAS#


CAS#



WE#


                                             Address Key

ADDR.


DQM

                                             tRP
  DQ    Hi-Z




                          PrechargeAll       Mode Register           Any
                                             Set Command             Command
                                     Mode Register Set Cycle (CAS# Latency = 2, 3)


        The mode register is divided into various fields depending on functionality.

        Address BS0,1 A10/AP                A9           A8          A7         A6        A5        A4        A3        A2         A1   A0

        Function RFU*           RFU*        WBL          Test Mode                CAS Latency                 BT         Burst Length

        *Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
        • Burst Length Field (A2~A0)
        This field specifies the data length of column access using the A2~A0 pins and selects the Burst
        Length to be 2, 4, 8, or full page.
               A2               A1                      A0                 Burst Length
               0                 0                      0                         1
               0                 0                      1                         2
               0                 1                      0                         4
               0                 1                      1                         8
               1                 0                      0                      Reserved
               1                 0                      1                      Reserved
               1                 1                      0                      Reserved
               1                 1                      1                      Full Page




Preliminary                                                              12                         Rev 0.8                        Nov 2001
EtronTech                                               2Mega x 32                 SDRAM             EM638325
      • Burst Type Field (A3)
      The Burst Type can be one of two modes, Interleave Mode or Sequential Mode.
              A3                Burst Type
              0                  Sequential
              1                  Interleave
      --- Addressing Sequence of Sequential Mode
      An internal column address is performed by increasing the address from the column address which
      is input to the device. The internal column address is varied by the Burst Length as shown in the
      following table. When the value of column address, (n + m), in the table is larger than 255, only the
      least significant 8 bits are effective.
              Data n        0        1          2      3     4       5         6     7       -     255    256   257       -
       Column Address       n        n+1        n+2   n+3   n+4   n+5         n+6   n+7      -     N+25    n    n+1       -
                                                                                                    5

                                2 words:

         Burst Length           4 words:

                                8 words:

                            Full Page: Column address is repeated until terminated.
      --- Addressing Sequence of Interleave Mode
      A column access is started in the input column address and is performed by inverting the address
      bits in the sequence shown in the following table.
        Data n                                      Column Address                                         Burst Length
        Data 0         A7   A6             A5         A4     A3          A2         A1      A0
        Data 1         A7   A6             A5         A4     A3          A2         A1      A0#      4 words
        Data 2         A7   A6             A5         A4     A3          A2         A1#     A0
        Data 3         A7   A6             A5         A4     A3          A2         A1#     A0#                   8 words
        Data 4         A7   A6             A5         A4     A3          A2#        A1      A0
        Data 5         A7   A6             A5         A4     A3          A2#        A1      A0#
        Data 6         A7   A6             A5         A4     A3          A2#        A1#     A0
        Data 7         A7   A6             A5         A4     A3          A2#        A1#     A0#


      • CAS# Latency Field (A6~A4)
      This field specifies the number of clock cycles from the assertion of the Read command to the first
      read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The
      minimum whole value satisfying the following formula must be programmed into this field.
      tCAC(min) ≤ CAS# Latency X tCK
              A6                A5                    A4          CAS# Latency
                  0              0                     0             Reserved
                  0              0                     1             Reserved
                  0              1                     0                 2 clocks
                  0              1                     1                 3 clocks
                  1              X                     X             Reserved




Preliminary                                                 13                           Rev 0.8                Nov 2001
EtronTech                                                   2Mega x 32                       SDRAM                           EM638325
         • Test Mode field (A8~A7)
         These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
                    A8                  A7                         Test Mode
                    0                   0                        normal mode
                    0                   1                    Vendor Use Only
                    1                   X                    Vendor Use Only
         • Write Burst Length (A9)
         This bit is used to select the burst write length.
                    A9                     Write Burst Length
                    0                            Burst
                    1                          Single Bit

  9      No-Operation command
         (RAS# = "H", CAS# = "H", WE# = "H")

               The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
         is Low). This prevents unwanted commands from being registered during idle or wait states.

  10     Burst Stop command
         (RAS# = "H", CAS# = "H", WE# = "L")
              The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
         command is only effective in a read/write burst without the auto precharge function. The terminated
         read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
         termination of a write burst is shown in the following figure.
                          T0       T1            T2         T3                 T4              T5               T6              T7               T8

   CLK


   COMMAND               READ A    NOP           NOP         NOP            Burst Stop          NOP             NOP             NOP              NOP


                                                                                                The burst ends after a delay equal to the CAS# latency.
   CAS# latency=2                               DOUT A0     DOUT A1           DOUT A2          DOUT A3
   tCK2, DQ's

   CAS# latency=3
                                                            DOUT A0           DOUT A1          DOUT A2         DOUT A3
   tCK3, DQ's

               Termination of a Burst Read Operation (Burst Length                                 4, CAS# Latency = 2, 3)
                         T0       T1            T2          T3                 T4               T5               T6              T7               T8

  CLK


  COMMAND                 NOP     WRITE A        NOP         NOP            Burst Stop          NOP              NOP             NOP              NOP


  CAS# latency= 2, 3
                                  DIN A0        DIN A1      DIN A2          don't care
  DQ's

                                                                     Input data for the Write is masked.

               Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)




Preliminary                                                        14                                      Rev 0.8                         Nov 2001
EtronTech                                      2Mega x 32          SDRAM              EM638325
  11   Device Deselect command (CS# = "H")
            The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
       and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
       to the No Operation command.

  12   AutoRefresh command
       (RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BS0,1 = “Don‘t care, A0-A10 = Don't care)
            The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
       CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
       must be issued each time a refresh is required. The addressing is generated by the internal refresh
       controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
       refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
       operation must be performed 4096 times within 64ms. The time required to complete the auto
       refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to
       be in the idle state and the device must not be in power down mode (CKE is high in the previous
       cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
       precharge time requirement, tRP(min), must be met before successive auto refresh operations are
       performed.

  13   SelfRefresh Entry command
       (RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A10 = Don't care)
            The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
       mode for data retention and low power operation. Once the SelfRefresh command is registered, all
       the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
       The refresh addressing and timing is internally generated to reduce power consumption. The
       SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
       restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).

  14 SelfRefresh Exit command
       (CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
            This command is used to exit from the SelfRefresh mode. Once this command is registered,
       NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
       completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
       performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
       prior to entering and just after exiting the SelfRefresh mode.

  15   Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
            When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
       subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
       intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command
       performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are
       turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown
       state longer than the refresh period (64ms) since the command does not perform any refresh
       operations.

  16   Clock Suspend Mode Exit / PowerDown Mode Exit command
            When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from
       the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the
       PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
       state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent
       commands can be issued after one clock cycle from the end of this command.

  17   Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
            During a write cycle, the DQM signal functions as a Data Mask and can control every word of
       the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
       also used for device selection, byte selection and bus control in a memory system.


Preliminary                                        15                    Rev 0.8               Nov 2001
EtronTech                                            2Mega x 32            SDRAM            EM638325
Absolute Maximum Rating
     Symbol                          Item                             Rating                Unit          Note
    VIN, VOUT                Input, Output Voltage                    - 1~4.6                V             1
    VDD, VDDQ                Power Supply Voltage                     - 1~4.6                V             1
         TOPR               Operating Temperature                      0~70                 °C             1
         TSTG                Storage Temperature                     - 55~150               °C             1
     TSOLDER             Soldering Temperature (10s)                   240                  °C             1
          PD                   Power Dissipation                           1                 W             1
         IOUT             Short Circuit Output Current                   50                 mA             1


Recommended D.C. Operating Conditions (Ta = 0~70°C)
 Symbol                     Parameter                    Min.        Typ.         Max.      Unit          Note
   VDD                 Power Supply Voltage              3.0         3.3          3.6        V             2
  VDDQ          Power Supply Voltage(for I/O Buffer)     3.0         3.3          3.6        V             2
   VIH               LVTTL Input High Voltage            2.0                  VDDQ + 0.3    V             2
   VIL               LVTTL Input Low Voltage             - 0.3                   0.8        V             2


Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
  Symbol                      Parameter                       Min.              Max.               Unit
     CI            Input Capacitance                                           4.5                pF
    CI/O           Input/Output Capacitance                                    6.5                pF
Note: These parameters are periodically sampled and are not 100% tested.




Preliminary                                              16                      Rev 0.8              Nov 2001
EtronTech                                           2Mega x 32          SDRAM                 EM638325
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0~70°C)
                                                                          - 3.5/4/5/5.5/6/7/8
              Description/Test condition                     Symbol              Max.            Unit   Note
 Operating Current                             1 bank          ICC1       285/250/200/190                3
 tRC ≥ tRC(min), Outputs Open, Input           operation
 signal one transition per one cycle                                        /180/155/135
 Precharge Standby Current in power down mode
                                                               ICC2P              3                      3
    tCK = 15ns, CKE ≤ VIL(max)
 Precharge Standby Current in power down mode
                                                              ICC2PS              3
   tCK = ∞, CKE ≤ VIL(max)
 Precharge Standby Current in non-power down mode
   tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH                       ICC2N             25                      3
    Input signals are changed once during 30ns.
 Precharge Standby Current in non-power down mode
                                                              ICC2NS             15
   tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH
 Active Standby Current in power down mode
                                                               ICC3P              5              mA      3
    CKE ≤ VIL(max), tCK = 15ns
 Active Standby Current in power down mode
                                                              ICC3PS              5                      3
    CKE & CLK ≤ VIL(max), tCK = ∞
 Active Standby Current in non-power down mode
                                                               ICC3N             40
    CKE ≥ VIH(min), CS# ≥ VIH(min), tCK = 15ns
 Active Standby Current in non-power down mode
                                                              ICC3NS             30
    CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
 Operating Current (Burst mode)
                                                               ICC4       290/260/225/220               3, 4
 tCK =tCK(min), Outputs Open, Multi-bank interleave
                                                                            /200/180/150
 Refresh Current
                                                               ICC5       360/310/260/240                3
  tRC ≥ TrC(min)
                                                                            /220/210/190
 Self Refresh Current
                                                               ICC6               2
   CKE ≤ 0.2V



Parameter                          Description                           Min.         Max.      Unit    Note
    IIL                       Input Leakage Current                                               $
              ( 0V	V 	V
                                                                         - 1.5          1.5
                     IN      DD, All other pins not under test = 0V )

   VOH                  LVTTL Output "H" Level Voltage
                               ( IOUT = -2mA )
                                                                         2.4                    V

   VOL                    LVTTL Output "L" Level Voltage
                                 ( IOUT = 2mA )
                                                                                       0.4      V




Preliminary                                             17                    Rev 0.8            Nov 2001
EtronTech                                         2Mega x 32                SDRAM                EM638325
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V ± 0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)
                                                                        - 3.5/4/5/5.5/6/7/8
Symbol                     A.C. Parameter                             Min.                     Max.            Unit   Note
tRC      Row cycle time                                                                                                9
                                                           35/40/50/55/60/70/70
         (same bank)
tRRD     Row activate to row activate delay                                                                            9
                                                            7/8/10/11/12/14/16
         (different banks)
tRCD     RAS# to CAS# delay                                                                                            9
                                                       12/12/15/16.5/18/21/20
         (same bank)
tRP      Precharge to refresh/row activate command                                                                     9
         (same bank)                                   12/12/15/16.5/18/21/20
tRAS     Row activate to precharge time                                                                                9
                                                       23/28/35/38.5/42/49/48                 100,000
         (same bank)
tCK2     Clock cycle time                    CL* = 2         - /- / - / - / - / - /10
tCK3                                         CL* = 3         3.5/4/5/5.5/6/7/8                                  ns
tAC2     Access time from CLK                CL* = 2                                    - / - / - / - / - /6           9
tAC3     (positive edge)                     CL* = 3                                     3.5/3.8/4.5/5
                                                                                           /5.5/5.5/6
tOH      Data output hold time                             1.6/1.8/2/2/2/2.5/2.5                                       9
tCH      Clock high time                                    1.7/1.9/2/2/2.5/3/3                                       10
tCL      Clock low time                                     1.7/1.9/2/2/2.5/3/3                                       10
tIS      Data/Address/Control Input set-up time        1.5/1.5/1.5/1.5/1.5/1.75                                       10
                                                                       /2
tIH      Data/Address/Control Input hold time                           1                                             10
tLZ      Data output low impedance                                      1                                              9
tHZ      Data output high impedance                                                      3.5/3.8/4.5/5                 8
                                                                                           /5.5/5.5/6
tWR      Write recovery time                                            2
tCCD     CAS# to CAS# Delay time                                        1                                      CLK
tMRS     Mode Register Set cycle time                                   2
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
   device.
2. All voltages are referenced to VSS.VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
   minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions


Preliminary                                           18                           Rev 0.8                     Nov 2001
 EtronTech                                           2Mega x 32          SDRAM               EM638325
 LVTTL Interface
          Reference Level of Output Signals                                1.4V / 1.4V
                     Output Load                              Reference to the Under Output Load (B)
                  Input Signal Levels                                      2.4V / 0.4V
   Transition Time (Rise and Fall) of Input Signals                            1ns
           Reference Level of Input Signals                                    1.4V
                                                                                             1.4V
                                     3.3V


                                     1.2kΩ                                                   50 Ω

                                                                           Z0= 50 Ω
       Output                                                  Output

                       30pF                                                                  30pF
                                     870Ω




          LVTTL D.C. Test Load (A)                                 LVTTL A.C. Test Load (B)
 7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
    slope (1 ns).
 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.

 9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns
    If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
    should be added to the parameter.
11. Power up Sequence
     Power up must be performed in the following sequence.
     1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
        and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
     2) After power-up, a pause of 200  VHFRQGV PLQLPXP LV UHTXLUHG 7KHQ LW LV UHFRPPHQGHG WKDW '40
        is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
     3) All banks must be precharged.
     4) Mode Register Set command must be asserted to initialize the Mode register.
     5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
        device.




 Preliminary                                             19                    Rev 0.8              Nov 2001
EtronTech                                                                        2Mega x 32                           SDRAM                            EM638325
Timing Waveforms

Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)


                T0     T 1 T2       T3       T4   T5     T6    T7         T8     T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

         tCH           tCL          tCK2

 CKE                         t IS                        Begin AutoPrecharge                Begin AutoPrecharge
                                                               Bank A                             Bank B
                t IS         t IH                                                                                                                     t IS

 CS#


 RAS#


 CAS#



 WE#


 BS0,1

                                    t IH
                t IS
ADDR.                    RBx           CAx             RBx          CBx               RAy            CAy                                     RAz             RBy



 DQM
                               tRCD                                  tDAL                   t IS
                                                  tRC                                                         tIH           tWR tRP                  tRRD
         Hi-Z
   DQ                                      Ax0 Ax1 Ax2        Ax3    Bx0       Bx1    Bx2      Bx3   Ay0     Ay1    Ay2   Ay3




                        Activate Write with   Activate Write with   Activate                         Write                      Precharge Activate      Activate
                       Command AutoPrecharge Command AutoPrecharge Command                         Command                      Command Command        Command
                        Bank A   Command      Bank B   Command      Bank A                          Bank A                       Bank A   Bank A        Bank B
                                  Bank A                Bank B




Preliminary                                                                                 20                                    Rev 0.8                          Nov 2001
EtronTech                                                           2Mega x 32                   SDRAM                           EM638325

Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)


               T0        T1      T2             T3       T4    T5      T6       T7          T8      T9       T10          T 11      T12      T13


  CLK

               tCH tCL                tCK2
  CKE                                                                                               Begin AutoPrecharge
                                  t IS                                                                    Bank B

                t IS                      t IH                                                                            tIH

  CS#


 RAS#


 CAS#


  WE#



 BS0,1

                                         t IH
   A10                          RAx                                   RBx                                                        RAy

                         t IS
A0-A11                          RAx                      CAx          RBx                 CBx                                    RAy

                                                      tRRD
                                                                            tRAS
 DQM                                                                                  tRC
                                                               tAC2      tAC2      t HZ                              tRP
        Hi-Z                             tRCD                  t LZ
   DQ                                                                 Ax0       Ax1                        Bx0            Bx1


                                                                         t OH                                             t HZ

                           Activate                    Read          Activate        Read with           Precharge                Activate
                          Command                    Command        Command        Auto Precharge        Command                 Command
                           Bank A                     Bank A         Bank B          Command              Bank A                  Bank A
                                                                                       Bank B




Preliminary                                                             21                               Rev 0.8                             Nov 2001
EtronTech                                                         2Mega x 32             SDRAM                 EM638325

Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)


          T0    T 1 T2       T3       T4   T5   T6    T7   T8    T9      T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                tCK2
CKE




CS#



RAS#



CAS#



WE#


BS0,1




 A10                                                                                       RAx




A0-A9                                                                                      RAx         CAx


                                                tRC                             tRC
 DQM               tRP



  DQ                                                                                                           Ax0 Ax1   Ax2 Ax3




         PrechargeAll   AutoRefresh                        AutoRefresh                    Activate     Read
          Command        Command                            Command                      Command     Command
                                                                                          Bank A      Bank A




Preliminary                                                              22                      Rev 0.8                  Nov 2001
EtronTech                                                                  2Mega x 32                 SDRAM          EM638325

Figure 4. Power on Sequene and Auto Refresh (CBR)


               T0    T 1 T2         T3    T4     T5   T6    T7   T8   T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


CLK

                            tCK2
CKE                 High level                          Minimum of 2 Refresh Cycles are required
                    is reauired

CS#


RAS#



CAS#



WE#


BS0,1



 A10

                                   Address Key

A0-A9



DQM
                                   tRP                                                          tRC
  DQ    Hi-Z


                    PrechargeALL          1st AutoRefresh                    2nd Auto Refresh                Any
                      Command                Command                            Command                    Command
                                   Mode Register
         Inputs must be            Set Command
        stable for 200 µs




Preliminary                                                                   23                        Rev 0.8            Nov 2001
EtronTech                                                              2Mega x 32                 SDRAM                      EM638325

Figure 5. Self Refresh Entry & Exit Cycle


          T0      T1          T2     T3      T4   T5   T6   T7    T8   T9    T10    T11    T12    T13   T14   T15    T16     T17   T18   T19

 CLK
                                   *Note 2
                  *Note 1                                                    *Note 4         tRC(min)   *Note 7


 CKE
                                                        *Note 3                                                       tPDE
                                                                                        tSRX
                                                                                       *Note 5
                       t IS
                                                                                        *Note 6
 CS#



 RAS#
           *Note 8
                                                                                                                  *Note 8


 CAS#



BS0,1



A0-A9


 WE#




DQM



                              Hi-Z                                           Hi-Z
     DQ


               Self Refresh Enter                                                  SelfRefresh Exit           AutoRefresh

Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
     To Exit SelfRefresh Mode
5.   System clock restart and be stable before returning CKE high.
6.   Enable CKE and CKE should be set high for minimum time of tSRX.
7.   CS# starts from high.
8.   Minimum tRC is required after CKE going high to complete SelfRefresh exit.
9.   4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
     system uses burst refresh.




Preliminary                                                                 24                           Rev 0.8                         Nov 2001
EtronTech                                                                   2Mega x 32                SDRAM                EM638325

Figure 6.1. Clock Suspension During Burst Read (Using CKE)
             (Burst Length=4, CAS# Latency=1)


            T0    T 1 T2        T3     T4      T5    T6     T     T8       T9   T10 T 11 T1      T13 T14 T15 T16 T17 T1   T19 T20 T21 T22
                                                            7

 CLK

                 tCK1
CKE


CS#


RAS#


CAS#


WE#


BS0,1



 A10                RAx




A0-A9                   RAx   CAx




DQM
                                                                                           tHZ

  DQ Hi-Z                                                                            Ax3
                                     Ax0       Ax1              Ax2


                   Activate                Clock Suspend   Clock Suspend         Clock Suspend
                  Command                     1 Cycle         2 Cycles              3 Cycles
                   Bank A
                            Read
                         Command
                          Bank A

Note: CKE to CLK disable/enable = 1 clock




Preliminary                                                                       25                        Rev 0.8                 Nov 2001
EtronTech                                                          2Mega x 32                SDRAM         EM638325

Figure 6.2. Clock Suspension During Burst Read (Using CKE)
             (Burst Length=4, CAS# Latency=2)


            T0    T 1 T2     T3   T4     T5    T6    T7   T8     T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                 tCK2
CKE




CS#


RAS#


CAS#


WE#



BS0,1


 A10             RAx




A0-A9            RAx       CAx




DQM
                                                                                       tHZ
  DQHi-Z                                                                       Ax3
                                       Ax0    Ax1          Ax2



                                                          Clock Suspend
            Activate      Read           Clock Suspend       2 Cycles      Clock Suspend
           Command      Command             1 Cycle                           3 Cycles
            Bank A       Bank A

Note: CKE to CLK disable/enable = 1 clock




Preliminary                                                               26                   Rev 0.8               Nov 2001
EtronTech                                                       2Mega x 32             SDRAM               EM638325

Figure 6.3. Clock Suspension During Burst Read (Using CKE)
               (Burst Length=4, CAS# Latency=3)


            T0    T 1 T 2 T3     T4   T5   T6     T7   T8    T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                  tCK3
CKE



CS#


RAS#


CAS#


WE#



BS0,1


 A10
                 RAx




A0-A9            RAx           CAx




DQM

                                                                                           tHZ
  DQ Hi-Z
                                            Ax0        Ax1            Ax2           Ax3



                                                                                 Clock Suspend
             Activate       Read                   Clock Suspend Clock Suspend      3 Cycles
            Command       Command                     1 Cycle       2 Cycles
             Bank A        Bank A

Note: CKE to CLK disable/enable = 1 clock




Preliminary                                                           27                         Rev 0.8          Nov 2001
EtronTech                                                                  2Mega x 32           SDRAM              EM638325

Figure 7.1. Clock Suspension During Burst Write (Using CKE)
               (Burst Length = 4, CAS# Latency = 1)


               T0   T 1 T2       T3   T4        T5   T6    T7      T8   T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK1
CKE



CS#


RAS#


CAS#


WE#



BS0,1


 A10                    RAx




A0-A9                   RAx    CAx




DQM


  DQ
        Hi-Z                  DAx0       DAx1
                                                                 DAx2                   DAx3



                       Activate Clock Suspend    Clock Suspend          Clock Suspend
                      Command       1 Cycle         2 Cycles               3 Cycles
                       Bank A
                              Write
                            Command
                             Bank A

Note: CKE to CLK disable/enable = 1 clock




Preliminary                                                                       28                  Rev 0.8                Nov 2001
EtronTech                                                            2Mega x 32            SDRAM              EM638325

Figure 7.2. Clock Suspension During Burst Write (Using CKE)
               (Burst Length=4, CAS# Latency=2)


           T0     T 1 T2      T3   T4     T5    T6    T7      T8    T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                tCK2

CKE


CS#



RAS#



CAS#


WE#



BA0,1



 A10          RAx




A0-A9         RAx       CAx



DQM


  DQHi-Z                 DAx0         DAx1                  DAx2                   DAx3




            Activate          Clock Suspend Clock Suspend          Clock Suspend
           Command               1 Cycle       2 Cycles               3 Cycles
            Bank A
                         Write
                       Command
                        Bank A

Note: CKE to CLK disable/enable = 1 clock




Preliminary                                                                 29                   Rev 0.8               Nov 2001
EtronTech                                                          2Mega x 32               SDRAM          EM638325

Figure 7.3. Clock Suspension During Burst Write (Using CKE)
               (Burst Length=4, CAS# Latency=3)


               T0   T 1 T2   T3     T4   T5   T6    T7    T8    T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK3
 CKE



 CS#


RAS#


CAS#


 WE#


BS0,1


 A10             RAx




A0-A9            RAx          CAx




DQM

  DQ
        Hi-Z                  DAx0                          DAx2                     DAx3
                                          DAx1




                Activate          Clock Suspend Clock Suspend        Clock Suspend
               Command               1 Cycle       2 Cycles             3 Cycles
                Bank A         Write
                             Command
                              Bank A

Note: CKE to CLK disable/enable = 1 clock




Preliminary                                                             30                    Rev 0.8               Nov 2001
EtronTech                                                           2Mega x 32                      SDRAM                     EM638325

Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2)


               T0    T 1 T2    T3      T4   T5    T6   T7    T8    T9      T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                      tCK2                                                                                                    tPDE
                                t IS
 CKE

                                                                                                   Valid

 CS#



RAS#



CAS#



 WE#



BS0,1



  A10           RAx




                    RAx                          CAx
A0~A9



 DQM
                                                                                             tHZ
        Hi-Z
                                                            Ax0   Ax1           Ax2            Ax3
   DQ

                                ACTIVE                                                                            PRECHARGE
                               STANDBY                                                                             STANDBY
                Activate                      Read            Clock Mask        Clock Mask          Precharge                    Power Down
               Command                      Command              Start             End              Command                       Mode Exit
                Bank A                       Bank A                                                  Bank A
                      Power Down     Power Down                                                                                            Any
                      Mode Entry      Mode Exit                                                                                          Command
                                                                                                   Power Down
                                                                                                   Mode Entry




Preliminary                                                                31                                   Rev 0.8                Nov 2001
EtronTech                                                        2Mega x 32                     SDRAM                       EM638325

Figure 9.1. Random Column Read (Page within same Bank)
              (Burst Length=4, CAS# Latency=1)

            T0    T 1 T2     T3    T4   T5    T6   T7     T8    T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                   tCK1
 CKE


 CS#



RAS#


CAS#


 WE#


BA0,1


  A10            RAw                                                                   RAz




A0~A9            RAw CAw                     CAx
                                                         CAy                           RAz    CAz




 DQM



   DQHi-Z                   Aw0   Aw1 Aw2    Aw3Ax0      Ax1    Ay0   Ay1Ay2     Ay3                  Az0    Az1Az2   Az3



             Activate                     Read          Read                   Precharge      Read
            Command                     Command       Command                  Command      Command
             Bank A                      Bank A        Bank A                   Bank A       Bank A
                     Read                                                            Activate
                  Command                                                           Command
                   Bank A                                                             Bank A




Preliminary                                                            32                                   Rev 0.8            Nov 2001
EtronTech                                                            2Mega x 32                   SDRAM                  EM638325

Figure 9.2. Random Column Read (Page within same Bank)
              (Burst Length=4, CAS# Latency=2)


               T0   T 1 T2     T3    T4   T5    T6      T7    T8    T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK2

 CKE


 CS#



RAS#



CAS#



 WE#



BA0,1


  A10           RAw                                                                                   RAz




                RAw         CAw                   CAx              CAy                                RAz        CAz
A0~A9


 DQM


        Hi-Z
   DQ                                     Aw0   Aw1 Aw2      Aw3   Ax0   Ax1 Ay0   Ay1    Ay2   Ay3                      Az0   Az1   Az2   Az3



                Activate     Read                 Read          Read                     Precharge Activate      Read
               Command     Command              Command       Command                    Command Command       Command
                Bank A      Bank A               Bank A        Bank A                     Bank A   Bank A       Bank A




Preliminary                                                               33                                  Rev 0.8                 Nov 2001
EtronTech                                                      2Mega x 32                    SDRAM                     EM638325

Figure 9.3. Random Column Read (Page within same Bank)
              (Burst Length=4, CAS# Latency=3)


               T0    T 1 T2   T3    T4   T5   T6   T7   T8     T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                     tCK3
 CKE



 CS#



 RAS#



 CAS#



 WE#


BS0,1



  A10            RAw                                                                                           RAz



A0~A9                                                             CAy                                                   CAz
                    RAw            CAw               CAx                                                    RAz



 DQM



        Hi-Z                                                                                                                        Az0
   DQ                                          Aw0    Aw1   Aw2     Aw3     Ax0 Ax1   Ay0   Ay1    Ay2   Ay3



                Activate        Read                   Read         Read               Precharge            Activate     Read
               Command        Command                Command      Command              Command             Command     Command
                Bank A         Bank A                 Bank A       Bank A               Bank A              Bank A      Bank A




Preliminary                                                             34                               Rev 0.8                 Nov 2001
EtronTech                                                       2Mega x 32                     SDRAM             EM638325

Figure 10.1. Random Column Write (Page within same Bank)
              (Burst Length=4, CAS# Latency=1)

           T0       T 1 T2    T3   T4   T5    T6     T7    T8   T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                tCK1
 CKE



 CS#



 RAS#



 CAS#



 WE#


BS0,1


  A10           RBw                                                                  RBz




A0~A9         RBw      CBw                                CBy                       RBz                    CBz
                                             CBx



 DQM


    Hi-Z
   DQ                  DBw0DBw1DBw2   DBw3 DBx0    DBx1DBy0 DBy1   DBy2 DBy3                             DBz0 DBz1   DBz2 DBz3



               Activate                    Write       Write               Precharge                     Write
              Command                    Command     Command               Command                     Command
               Bank A                     Bank A      Bank B                Bank B                      Bank B
                      Write                                                         Activate
                    Command                                                        Command
                     Bank B                                                         Bank B




Preliminary                                                           35                         Rev 0.8                    Nov 2001
EtronTech                                                           2Mega x 32              SDRAM                      EM638325

Figure 10.2. Random Column Write (Page within same Bank)
              (Burst Length=4, CAS# Latency=2)

             T0   T 1 T2     T3      T4   T5   T6     T7     T8     T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                  tCK2

 CKE


 CS#



RAS#



CAS#


 WE#



BS0,1


              RBw                                                                               RBz
  A10


A0~A9         RBw         CBw                                     CBy                           RBz        CBz
                                                CBx



 DQM



   DQ Hi-Z                DBw0     DBw1 Bw2 DBw3 DBx0
                                      D                       DBy0 DBy1
                                                           DBx1            DBy2 DBy3
                                                                                                           DBz0      DBz2 DBz3
                                                                                                                  DBz1



              Activate     Write                 Write         Write               Precharge Activate       Write
             Command     Command               Command       Command               Command Command        Command
              Bank A      Bank B                Bank B        Bank B                Bank B   Bank B        Bank B




Preliminary                                                               36                            Rev 0.8                  Nov 2001
EtronTech                                                2Mega x 32             SDRAM                   EM638325

Figure 10.3. Random Column Write (Page within same Bank)
              (Burst Length=4, CAS# Latency=3)


            T0    T 1 T2   T3   T4   T5   T6   T7   T8   T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                 tCK3

 CKE


 CS#



RAS#



CAS#


 WE#



BS0,1


              RBw                                                                              RBz
  A10


A0~A9            RBw        CBw                 CBx           CBy                              RBz         CBz



 DQM



  DQ Hi-Z                   DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3                               DBz0 DBz1 DBz2



              Activate       Write               Write     Write                Precharge    Activate       Write
             Command       Command             Command   Command                Command     Command       Command
              Bank A        Bank B              Bank B    Bank B                 Bank B      Bank B        Bank B




Preliminary                                                     37                      Rev 0.8               Nov 2001
EtronTech                                                                    2Mega x 32              SDRAM                  EM638325

Figure 11.1. Random Row Read (Interleaving Banks)
              (Burst Length=8, CAS# Latency=1)

              T0     T 1 T2        T3   T4     T5   T6   T7       T8     T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                     tCK1
CKE High



CS#


RAS#


CAS#


WE#


BS0,1



  A10       RBx                                                RAx                  RBy




            RBx CBx                                           RAx                   RBy                                   CBy
A0~A9                                                                 CAx

             tRCD
 DQM                        tAC1                                                tRP


  DQ Hi-Z
                       Bx0     Bx1   Bx2     Bx3 Bx4   Bx5     Bx6     Bx7                                                      By0     By1       By2
                                                                              Ax0    Ax1 Ax2 Ax3   Ax4   Ax5   Ax6 Ax7


                                                              Activate    Precharge                                        Read       Precharge
         Activate                                            Command      Command                                        Command      Command
        Command                                               Bank A       Bank B                                         Bank B       Bank A
         Bank B
                    Read                                                         Activate
                                                                       Read     Command
                  Command                                            Command
                   Bank B                                                         Bank B
                                                                      Bank A




Preliminary                                                                         38                         Rev 0.8                     Nov 2001
EtronTech                                                                 2Mega x 32                          SDRAM                       EM638325

Figure 11.2. Random Row Read (Interleaving Banks)
              (Burst Length=8, CAS# Latency=2)

             T0     T 1 T2        T3        T4   T5    T6    T7     T8    T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK2
 CKE High


 CS#



RAS#



CAS#



 WE#


BS0,1



            RBx
 A10                                                              RAx                              RBy



A0~A9       RBx          CBx                                      RAx          CAx                 RBy                                   CBy


                  tRCD         tAC2                                                        tRP
 DQM



    Hi-Z
   DQ
                                      Bx0    Bx1      Bx2   Bx3 Bx4      Bx5 Bx6     Bx7    Ax0     Ax1      Ax2 Ax3
                                                                                                                       Ax4   Ax5   Ax6    Ax7   By0   By1




         Activate     Read                                    Activate          Precharge         Activate                           Read
        Command     Command                                  Command            Command          Command                           Command
         Bank B      Bank B                                   Bank A              Bank B          Bank B                            Bank B
                                                                             Read
                                                                           Command
                                                                            Bank A




Preliminary                                                                      39                                    Rev 0.8                   Nov 2001
EtronTech                                                                   2Mega x 32                      SDRAM                          EM638325

Figure 11.3. Random Row Read (Interleaving Banks)
              (Burst Length=8, CAS# Latency=3)

               T0     T 1 T2     T3    T4     T5     T6    T7       T8      T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                    tCK3

 CKEHigh


 CS#


RAS#


CAS#



 WE#


BS0,1


  A10    RBx                                                  RAx                                                 RBy




           RBx                                                  RAx                CAx                              RBy
A0~A9                          CBx                                                                                                        CBy


                      tRCD             tAC3                                                                 tRP
 DQM


    Hi-Z
   DQ                                                                                                                                                Ax7    By0
                                                                                             Bx6
                                                   Bx0    Bx1 Bx2     Bx3        Bx4   Bx5         Bx7     Ax0 Ax1 Ax2        Ax3   Ax4    Ax5 Ax6


         Activate              Read                          Activate                Read      Precharge           Activate           Read      Precharge
        Command              Command                        Command                Command     Command            Command           Command     Command
         Bank B               Bank B                         Bank A                 Bank A      Bank B             Bank B            Bank B      Bank A




Preliminary                                                                       40                                Rev 0.8                            Nov 2001
EtronTech                                                             2Mega x 32              SDRAM                  EM638325

Figure 12.1. Random Row Write (Interleaving Banks)
              (Burst Length=8, CAS# Latency=1)


               T0     T 1 T2   T3     T4   T5     T6   T7     T8      T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                      tCK1
 CKE
        High


 CS#


RAS#


CAS#


 WE#



BS0,1


  A10     RAx                                            RBx                               RAy




A0~A9     RAx    CAx                                        RBx CBx                        RAy                     CAy


               tRCD                                                                     tRP           tWR
 DQM



   DQ Hi-Z     DAx0    DAx1 DAx2
                               DAx3    DAx4                                     DBx4 DBx5 DBx6 DBx7
                                                DAx5DAx6 DAx7 DBx0 DBx1 DBx2 DBx3                                   DAy0 DAy1 DAy2 DAy3



          Activate                                       Activate                  Precharge          Precharge     Write
         Command                                        Command                    Command            Command     Command
          Bank A                                         Bank B                     Bank A             Bank B      Bank A
                 Write                                          Write                     Activate
               Command                                        Command                    Command
                Bank A                                         Bank B                      Bank A




Preliminary                                                                41                        Rev 0.8                    Nov 2001
EtronTech                                                          2Mega x 32                    SDRAM              EM638325

Figure 12.2. Random Row Write (Interleaving Banks)
              (Burst Length=8, CAS# Latency=2)


             T0    T 1 T2      T3   T4   T5   T6   T7      T8      T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                   tCK2

 CKE High


 CS#


RAS#


CAS#



 WE#



BS0,1


  A10      RAx                                          RBx                              RAy




A0~A9      RAx      CAx                                 RBx             CBx              RAy                CAy



                 tRCD                                               tWR*           tRP                     tWR*
 DQM



   DQ Hi-Z              DAx0 DAx1 DAx2 DAx3 DAx4DAx5   DAx6     DAx7 DBx0 DBx1 DBx2 DBx3 DBx4DBx5 DBx6 DBx7 DAy0 DAy1DAy2    DAy3 DAy4



           Activate  Write                              Activate      Write           Activate               Write
          Command Command                              Command      Command          Command               Command
           Bank A   Bank A                              Bank B       Bank B           Bank A                Bank A
                                                                       Precharge                                 Precharge
                                                                       Command                                   Command
                                                                         Bank A                                    Bank B

       * tWR > tWR(min.)




Preliminary                                                               42                       Rev 0.8                     Nov 2001
EtronTech                                                           2Mega x 32                  SDRAM                 EM638325

Figure 12.3. Random Row Write (Interleaving Banks)
              (Burst Length=8, CAS# Latency=3)


                 T0    T 1 T2     T3   T4   T5   T6   T7      T8    T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                      tCK3
        High
 CKE


 CS#


RAS#



CAS#



 WE#



BS0,1



  A10          RAx                                         RBx                                           RAy




A0~A9          RAx              CAx                    RBx                 CBx                           RAy         CAy



                       tRCD                                                  tWR*               tRP                        tWR*
 DQM


    Hi-Z
   DQ                           DAx0DAx1 DAx2 DAx3DAx4 DAx5      DAx6 DAx7 DBx0 DBx1DBx2    DBx3 DBx4 DBx5 DBx6 DBx7DAy0    DAy1 DAy2 DAy3



           Activate            Write                   Activate            Write    Precharge          Activate     Write     Precharge
          Command            Command                  Command            Command    Command           Command     Command     Command
           Bank A             Bank A                   Bank B             Bank B     Bank A            Bank A      Bank A      Bank B

* tWR > tWR(min.)




Preliminary                                                              43                             Rev 0.8                     Nov 2001
EtronTech                                                    2Mega x 32                 SDRAM                              EM638325

Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)


             T0   T 1 T2      T3   T4   T5    T6   T7   T8   T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                  tCK1

 CKE



 CS#


RAS#



CAS#



 WE#


BS0,1


  A10         RAx




              RAx CAx                                          CAy                    CAz
A0~A9


 DQM



   DQ Hi-Z                                                                                                           Az3
                           Ax0 Ax1   Ax2     Ax3                  DAy0DAy1     DAy3         Az0     Az1



              Activate                                         Write  The Write Data    Read       The Read Data             Precharge
             Command                                         Command is Masked with a Command     is Masked with a           Command
              Bank A                                          Bank A    Zero Clock     Bank A        Two Clock                Bank B
                      Read                                               Latency                      Latency
                    Command
                     Bank A




Preliminary                                                          44                            Rev 0.8                       Nov 2001
EtronTech                                                      2Mega x 32                SDRAM             EM638325

Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)


            T0    T 1 T2    T3     T4    T5    T6   T7   T8   T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                  tCK2
 CKE



 CS#


RAS#



CAS#



 WE#




BS0,1


  A10            RAx




A0~A9            RAx       CAx                                     CAy                     CAz




 DQM



  DQ Hi-Z                               Ax0   Ax1   Ax2 Ax3        DAy0 DAy1      DAy3              Az0   Az1          Az3



              Activate     Read                                 Write  The Write Data       Read           The Read Data
             Command     Command                              Command is Masked with a    Command         is Masked with a
              Bank A      Bank A                               Bank A    Zero Clock        Bank A            Two Clock
                                                                          Latency                             Latency




Preliminary                                                              45                 Rev 0.8                          Nov 2001
EtronTech                                                     2Mega x 32                    SDRAM                 EM638325

Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3)


             T0    T 1 T2   T3   T4   T5   T6     T7   T8     T9      T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                   tCK3
 CKE


 CS#


RAS#



CAS#



 WE#



BS0,1


  A10          RAx




                              CAx                                            CAy                      CAz
A0~A9          RAx




 DQM



   DQ Hi-Z                                  Ax0    Ax1      Ax2 Ax3          DAy0 DAy1          DAy3             Az0     Az1          Az3



              Activate        Read                                           Write  The Write Data      Read            The Read Data
             Command        Command                                        Command is Masked with a   Command          is Masked with a
              Bank A         Bank A                                         Bank A    Zero Clock       Bank A             Two Clock
                                                                                       Latency                             Latency




Preliminary                                                           46                               Rev 0.8                   Nov 2001
EtronTech                                                             2Mega x 32                     SDRAM                           EM638325

Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)


             T0    T 1 T2      T3     T4     T5    T6   T7      T8     T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


  CLK

                   tCK1
 CKE



 CS#


 RAS#



 CAS#



 WE#



 BS0,1


  A10             RAx                      RBw




                  RAx RAx                  RBw    CBw        CBx            CBy         CAy         CBz
A0~A9

                   tRCD tAC1
 DQM


   DQ Hi-Z                  Ax0     Ax1 Ax2       Ax3 Bw0    Bw1     Bx0 Bx1      By0    By1 Ay0    Ay1   Bz0    Bz1 Bz2 Bz3




               Activate                Activate               Read       Read         Read           Read    Precharge   Precharge
              Command                 Command               Command    Command      Command        Command   Command     Command
               Bank A Read             Bank B Read           Bank B     Bank B       Bank A         Bank B    Bank A      Bank B
                     Command                 Command
                      Bank A                  Bank B




Preliminary                                                                   47                                Rev 0.8                 Nov 2001
EtronTech                                                                2Mega x 32                    SDRAM                      EM638325

Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)


               T0   T 1 T2      T3    T4      T5    T6    T7    T8    T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK2

 CKE


 CS#


RAS#



CAS#



 WE#


BS0,1


  A10           RAx                         RAx




A0~A9           RAx           CAy           RAx          CBw         CBx          CBy         CAy      CBz



                       tRCD          tAC2
 DQM



        Hi-Z
  DQ                                    Ax0        Ax1 Ax2     Ax3 Bw0     Bw1     Bx0 Bx1    By0   By1 Ay0   Ay1      Bz0   Bz1 Bz2 Bz3



                Activate     Read       Activate        Read    Read               Read        Read      Read                  Precharge
               Command     Command     Command        Command Command            Command     Command   Command                 Command
                Bank A      Bank A      Bank B         Bank B  Bank B             Bank B      Bank A    Bank B                  Bank B
                                                                                                           Precharge
                                                                                                           Command
                                                                                                             Bank A




Preliminary                                                                      48                           Rev 0.8                      Nov 2001
EtronTech                                                                2Mega x 32                      SDRAM                    EM638325

Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)


            T0    T 1 T2       T3     T4     T5    T6     T7     T8      T9    T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                 tCK3
 CKE



 CS#


RAS#



CAS#



 WE#



BS0,1


              RAx                          RBx
  A10



A0~A9         RAx               CAx    RBx                 CBx                CBy        CBz        CAy



                        tRCD                tAC3
 DQM


   DQHi-Z
                                                                              Ax3 Bx0    Bx1   By0 By1          Bz1 Ay0           Ay2
                                                    Ax0        Ax1 Ax2                                    Bz0             Ay1           Ay3


                                                                                                                      Precharge
             Activate             Read                      Read           Read           Read      Read Prechaerge   Command
            Command             Command                   Command        Command        Command   CommandCommand       Bank A
             Bank A              Bank A                    Bank B         Bank B         Bank B    Bank A Bank B
                                      Activate
                                     Command
                                      Bank B




Preliminary                                                                     49                              Rev 0.8                       Nov 2001
EtronTech                                                         2Mega x 32                  SDRAM                         EM638325

Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)


            T0    T 1 T2       T3      T4   T5   T6   T7     T8   T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                  tCK1
 CKE



 CS#


RAS#



CAS#



 WE#



BS0,1

  A10         RAx           RBw




                                                                   CBy                          CBz
              RAx       CAx RBw              CBw       CBx                     CAy
A0~A9
                                                                                              tRP
                 tRCD                                                                                               tWR tRP
 DQM

                     tRRD
  DQ Hi-Z           DAx0                                                                                   DBz2
                            DAx1 DAx2 DAx3 DBw0DBw1 DBx0 DBx1 DBy0        DBy1 DAy0   DAy1     DBz0 DBz1          DBz3



             Activate       Activate          Write     Write       Write       Write              Write                 Precharge
            Command        Command          Command   Command     Command     Command           Command                  Command
             Bank A         Bank B           Bank B    Bank B      Bank B      Bank A            Bank B                   Bank B
                                                                                         Precharge
                      Write                                                              Command
                    Command                                                               Bank A
                     Bank A




Preliminary                                                              50                            Rev 0.8                       Nov 2001
EtronTech                                                              2Mega x 32               SDRAM                       EM638325

Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)


             T0    T 1 T2        T3   T4     T5     T6    T7   T8     T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                  tCK2

 CKE


 CS#


RAS#



CAS#



WE#



BS0,1


  A10         RAx                      RBw




A0~A9         RAx          CAx             RBw           CBw    CBx           CBy      CAy       CBz



                    tRCD                                                                                      tRP     tWR     tRP
 DQM
                            tRRD

   DQ Hi-Z                  DAx0
                               DAx1 DAx2          DAx3DBw0 DBw1 DBx0     DBx1DBy0   DBy1DAy0 DAy1 DBz0 DBz1 DBz2    DBz3



              Activate     Write       Activate       Write      Write        Write     Write     Write               Precharge
             Command     Command      Command       Command    Command      Command   Command   Command               Command
              Bank A      Bank A       Bank B        Bank B     Bank B       Bank B    Bank A    Bank B                Bank B
                                                                                                      Precharge
                                                                                                      Command
                                                                                                        Bank A




Preliminary                                                                 51                          Rev 0.8                     Nov 2001
EtronTech                                                        2Mega x 32                 SDRAM                     EM638325

Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)


            T0    T 1 T2       T3    T4     T5    T6   T7   T8   T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                 tCK3

 CKE



 CS#


RAS#



CAS#



WE#




BS0,1


  A10         RAx                       RBw




              RAx                 CAx RBw               CBw        CBx         CBy        CAy        CBz
A0~A9

                        tRCD                                                                        tWR         tRP   tWR(min)
 DQM
                    tRRD > tRRD(min)

  DQ Hi-Z                         DAx0 DAx1 DAx2 DAx3DBw0     DBw1DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3



             Activate                  Activate          Write     Write        Write     Write     Write             Precharge
            Command                  Command           Command   Command      Command   Command   Command             Command
             Bank A                    Bank B           Bank B    Bank B       Bank B    Bank A    Bank B              Bank B
                                 Write                                                                  Precharge
                               Command                                                                  Command
                                Bank A                                                                    Bank A




Preliminary                                                              52                         Rev 0.8                       Nov 2001
EtronTech                                                             2Mega x 32                    SDRAM                       EM638325

Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)


            T0    T 1 T2     T3       T4    T5     T6    T7    T8    T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

 CLK

                 tCK1
 CKE High



 CS#



RAS#



CAS#



 WE#



BS0,1


         RAx                                                              RBy                                             RBz
  A10                             RBx



                                           CBx                             RBy            CBy
         RAx   CAx                  RBx                             CAy                                                   RBz   CBz
A0~A9


 DQM


  DQ Hi-Z                  Ax1     Ax2    Ax3    Bx0    Bx1 Bx2     Bx3 Ay0      Ay1   Ay2 Ay3    By0   By1         By3                           Bz2
                     Ax0                                                                                      By2                     Bz0   Bz1         Bz3



         Activate                 Activate                              Activate         Read with                    Activate
        Command                  Command                               Command         Auto Precharge                Command
         Bank A                   Bank B                                Bank B           Command                      Bank B
                  Read                   Read with                                         Bank B
                                      Auto Precharge            Read with                                                   Read with
               Command                                        Auto Precharge                                             Auto Precharge
                Bank A                  Command
                                          Bank B                Command                                                     Command
                                                                  Bank A                                                     Bank B




Preliminary                                                                     53                            Rev 0.8                        Nov 2001
EtronTech                                                                2Mega x 32                  SDRAM                       EM638325

Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)


             T0     T 1 T2     T3     T4    T5    T6    T7        T8     T9      T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK2
 CKE High


 CS#



RAS#



CAS#



 WE#



BS0,1


          RAx                   RBx                                                     RBy                   RAz
  A10


          RAx          CAx          RBx         CBx                           RAy       RBy         CBy       RAz        CAz
A0~A9


 DQM


   DQ Hi-Z                      Ax0       Ax1   Ax2   Ax3   Bx0        Bx1 Bx2      Bx3 Ay0   Ay1   Ay2 Ay3    By0 By1 By2       By3 Az0   Az1 Az2



         Activate      Read     Activate Read with                       Read with     Activate Read with     Activate Read with
        Command      Command   Command Auto Precharge                  Auto Precharge Command Auto Precharge Command Auto Precharge
         Bank A       Bank A    Bank B   Command                         Command       Bank B   Command       Bank A   Command
                                           Bank B                          Bank A                 Bank B                 Bank A




Preliminary                                                                      54                           Rev 0.8                       Nov 2001
EtronTech                                                                2Mega x 32                  SDRAM                         EM638325

Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)


             T0     T 1 T2     T3    T4     T5     T6   T7        T8   T9      T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK3

 CKE High


 CS#


RAS#



CAS#



 WE#



BS0,1



  A10     RAx                    RBx                                                               RBy




A0~A9     RAx                CAx RBx                 CBx                         CAy               RBy                CBy




 DQM


   DQ Hi-Z                                   Ax0     Ax1   Ax2     Ax3   Bx0      Bx1 Bx2    Bx3   Ay0     Ay1   Ay2 Ay3            By0 By1 By2   By3



         Activate                Activate          Read with                                    Activate            Read with
        Command                 Command          Auto Precharge                                Command            Auto Precharge
         Bank A                  Bank B            Command                                      Bank B              Command
                             Read                    Bank B                   Read with                               Bank B
                           Command                                          Auto Precharge
                            Bank A                                            Command
                                                                                Bank A




Preliminary                                                                    55                                Rev 0.8                 Nov 2001
EtronTech                                                              2Mega x 32                       SDRAM              EM638325

Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)


             T0    T 1 T2         T3   T4     T5    T6   T7     T8    T9       T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                  tCK1

 CKE High


 CS#


RAS#



CAS#



 WE#



BS0,1



  A10     RAx               RBx                                                  RBy                               RAz




          RAx CAx           RBx         CBx                          CAy          RBy       CBy                    RAz     CAz
A0~A9


 DQM


   DQ Hi-Z      DAx0
                       DAx1 DAx2 DAx3 DBx0 DBx1 DBx2DBx3 DAy0 DAy1DAy2 DAy3 DBy0
                                                                                                  DBy1 DBy2 DBy3
                                                                                                                         DAz0 DAz0
                                                                                                                                      DAz0DAz0



         Activate           Activate Write with                                 Activate Write with                 Activate
        Command            Command Auto Precharge                              Command Auto Precharge              Command
         Bank A             Bank B   Command                                    Bank B   Command                    Bank A
                  Write                Bank B                   Write with                 Bank B
               Command                                        Auto Precharge                                           Write with
                Bank A                                          Command                                              Auto Precharge
                                                                  Bank A                                               Command
                                                                                                                         Bank A




Preliminary                                                                    56                           Rev 0.8                    Nov 2001
EtronTech                                                        2Mega x 32              SDRAM                      EM638325

Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)


            T0    T 1 T2   T3     T4   T5   T6      T7   T8     T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                 tCK2

 CKE High


 CS#



RAS#



CAS#


 WE#



BS0,1


         RAx                 RBx                                                 RBy                    RAz
  A10


A0~A9    RAx        CAx         RBx     CBx                          CAy          RBy       CBy         RAz       CAz




 DQM



  DQ Hi-Z          DAx0 DAx1 DAx2 DAx3                                                      DBy0 DBy1   DBy2 DBy3DAz0 DAz1 DAz2 DAz3
                                       DBx0 DBx1DBx2 DBx3 DAy0 DAy1DAy2 DAy3



         Activate  Write    Activate Write with                 Write with      Activate Write with    Activate Write with
        Command Command    Command Auto Precharge             Auto Precharge   Command Auto Precharge Command Auto Precharge
         Bank A   Bank A    Bank B   Command                    Command         Bank B   Command       Bank A   Command
                                       Bank B                     Bank A                   Bank B                 Bank A




Preliminary                                                            57                         Rev 0.8                      Nov 2001
EtronTech                                                             2Mega x 32                   SDRAM                      EM638325

Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)


               T0    T 1 T2     T3     T4     T5    T6      T7   T8   T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK3
 CKE High


 CS#



RAS#



CAS#



 WE#


                                                                                                          `
BS0,1



   A9    RAx                       RBx                                                                  RBy




A0~A9    RAx                CAx RBx                   CBx                     CAy                       RBy          CBy




 DQM


   DQ Hi-Z                    DAx0 DAx1 DAx2 DAx3
                                                DBx0 DBx1 DBx2 DBx3 DAy0 DAy1               DAy2 DAy3                 DBy0 DBy1 DBy2DBy3



         Activate                  Activate          Write with              Write with              Activate      Write with
        Command                  Command           Auto Precharge          Auto Precharge           Command      Auto Precharge
         Bank A                    Bank B            Command                 Command                 Bank B        Command
                             Write                     Bank B                  Bank A                                Bank B
                           Command
                            Bank A




Preliminary                                                                 58                                Rev 0.8                  Nov 2001
EtronTech                                                                   2Mega x 32                        SDRAM                               EM638325

Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)


              T0     T 1 T2     T3     T4     T5    T6         T7    T8     T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                     tCK1

 CKE High


 CS#



RAS#



CAS#



 WE#



BS0,1


            RAx
  A10                    RBx                                                                                                          RBy




A0~A9                    RBx                                        CBx                                                                RBy
            RAx    CAx


                  tRRD                                                                                                               tRP
 DQM



   DQHi-Z
                         Ax    Ax+1 Ax+2                                       Bx+1                                  Bx+6 Bx+7
                                            Ax-2 Ax-1     Ax     Ax+1 Bx              Bx+2 Bx+3 Bx+4 Bx+5


         Activate    Activate                                    Read                                                         Precharge
        Command     Command                                    Command                                                        Command
         Bank A      Bank B The burst counter wraps             Bank B                                                          Bank B
                              from the highest order                 Full Page burst operation does not                Burst Stop      Activate
               Read           page address back to zero              terminate when the burst length is satisfied;     Command       Command
             Command          during this time interval              the burst counter increments and continues                        Bank B
              Bank A                                                 bursting beginning with the starting address.




Preliminary                                                                        59                                     Rev 0.8                    Nov 2001
EtronTech                                                                 2Mega x 32                     SDRAM                             EM638325

Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)


              T0    T 1 T2    T3     T4     T5    T6      T7    T8        T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK2
 CKE High



 CS#


RAS#



CAS#



 WE#




BS0,1



            RAx                    RBx                                                                                                    RBy
  A10


            RAx       CAx          RBx                               CBx                                                                 RBy
A0~A9

                                                                                                                                  tRP
 DQM


   DQHi-Z                       Ax        Ax+1 Ax+2Ax-2     Ax-1     Ax    Ax+1    Bx   Bx+1 Bx+2 Bx+3           Bx+5
                                                                                                              Bx+4         Bx+6



         Activate     Read     Activate                             Read                                                  Precharge      Activate
        Command     Command   Command                                    Full
                                                                  Command Page burst operation does not                   Command       Command
         Bank A      Bank A    Bank B                              Bank Bterminate when the burst length is satisfied;     Bank B        Bank B
                                        The burst counter wraps          the burst counter increments and continues
                                        from the highest order           bursting beginning with the starting address.
                                        page address back to zero
                                        during this time interval                                                Burst Stop
                                                                                                                 Command




Preliminary                                                                    60                                   Rev 0.8                         Nov 2001
EtronTech                                                                   2Mega x 32                        SDRAM                             EM638325

Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)


            T0      T 1 T2     T3    T4     T5        T6      T7    T8     T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                    tCK3

 CKE High


 CS#



RAS#



CAS#



 WE#




BS0,1


         RAx                              RBx                                                                                                     RBy
  A10


         RAx                 CAx          RBx                                   CBx                                                               RBy
A0~A9


                                                                                                                                          tRP
 DQM



  DQ Hi-Z                                        Ax    Ax+1 Ax+2 Ax-2           Ax-1     Ax   Ax+1 Bx      Bx+1 Bx+2 Bx+3 Bx+4 Bx+5



         Activate            Read     Activate                                    Read   Full Page burst operation does not   Precharge          Activate
        Command            Command   Command                                   Command   terminate when the burst length is   Command           Command
         Bank A             Bank A    Bank B                                    Bank B   satisfied; the burst counter          Bank B            Bank B
                                                           The burst counter wraps       increments and continues
                                                           from the highest order        bursting beginning with the  Burst Stop
                                                           page address back to zero     starting address.             Command
                                                           during this time interval




Preliminary                                                                            61                               Rev 0.8                             Nov 2001
EtronTech                                                                     2Mega x 32                      SDRAM                             EM638325

Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1)


             T0     T 1 T2       T3     T4    T5     T6       T7      T8     T9      T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                     tCK1
 CKE High


 CS#


RAS#



CAS#



 WE#




BS0,1


          RAx           RBx                                                                                                         RBy
  A10


          RAx     CAx   RBx                                        CBx                                                               RBy
A0~A9


 DQM



   DQ Hi-Z        DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1
                                                             DBx         DBx+ 1
                                                                               DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 DBx+ 7




         Activate     Activate                                    Write                                   Data is ignored    Precharge
        Command     Command                                     Command                                                      Command
         Bank A       Bank B                                     Bank B                                                       Bank B
                              The burst counter wraps     Full Page burst operation does                              Burst Stop
                                                          not terminate when the burst                                Command        Activate
                              from the highest order
                Write                                     length is satisfied; the burst counter                                    Command
                              page address back to zero
              Command                                     increments and continues bursting                                          Bank B
                              during this time interval
               Bank A                                     beginning with the starting address.




Preliminary                                                                          62                                    Rev 0.8                 Nov 2001
EtronTech                                                                 2Mega x 32                        SDRAM                         EM638325

Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)


             T0     T 1 T2    T3    T4      T5     T6     T7     T8     T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK

                    tCK2

 CKE High


 CS#



RAS#



CAS#



 WE#




BS0,1


          RAx                    RBx                                                                                                    RBy
  A10


A0~A9    RAx         CAx           RBx                              CBx                                                                 RBy



 DQM



   DQ Hi-Z            DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx       DBx+ 1DBx+ 2 DBx+ 3     DBx+ 4 DBx+ 5 DBx+ 6




         Activate     Write     Activate                             Write                             Data is ignored     Precharge    Activate
        Command     Command    Command                            Command                                                  Command     Command
         Bank A      Bank A     Bank B                             Bank B                                                   Bank B      Bank B
                                The burst counter wraps Full Page burst operation does                              Burst Stop
                                from the highest order    not terminate when the burst                              Command
                                page address back to zero length is satisfied; the burst counter
                                during this time interval increments and continues bursting
                                                          beginning with the starting address.




Preliminary                                                                     63                                        Rev 0.8                  Nov 2001
EtronTech                                                                 2Mega x 32                          SDRAM                          EM638325

Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)


             T0     T 1 T2        T3   T4    T5     T6     T7     T8     T9       T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

 CLK

                    tCK3
 CKE High


 CS#



RAS#



CAS#



 WE#



BS0,1



          RAx                            RBx                                                                                                       RBy
  A10


          RAx               CAx          RBx
A0~A9                                                                       CBx                                                                    RBy




 DQM
                                                                                                                                 Data is ignored


   DQ Hi-Z
                                                                        DBx        DBx+ 1
                             DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1                  DBx+ 2 DBx+ 3      DBx+ 4 DBx+ 5




         Activate            Write      Activate                           Write                                             Precharge          Activate
        Command            Command     Command                           Command                                             Command           Command
         Bank A             Bank A      Bank B                            Bank B                                              Bank B            Bank B
                                         The burst counter wraps                                                      Burst Stop
                                         from the highest order    Full Page burst operation does
                                                                                                                      Command
                                         page address back to zero not terminate when the burst
                                         during this time interval length is satisfied; the burst counter
                                                                   increments and continues bursting
                                                                   beginning with the starting address.




Preliminary                                                                       64                                        Rev 0.8                        Nov 2001
EtronTech                                                               2Mega x 32                SDRAM                      EM638325

Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)


                   T0    T 1 T2    T3     T4     T5     T6    T7   T8     T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

     CLK

                         tCK2
     CKE High


     CS#



     RAS#



     CAS#



     WE#



    BS0,1




      A10    RAx




    A0~A9       RAx       CAx                                           CAy                 CAz




    LDQM



    UDQM


 DQ0 - DQ7                              Ax0     Ax1   Ax2                         DAy2
                                                                               DAy1                        Az1   Az2



                                               Ax1    Ax2    Ax3        DAy0 DAy1        DAy3              Az1   Az2   Az3
DQ8 - DQ15                                                                                          Az0



              Activate     ReadUpper 3 Bytes    Lower Byte           Write Upper 3 Bytes Read         Lower Byte         Lower Byte
             Command            are
                         Command masked         is masked          Command are masked Command         is masked          is masked
              Bank A      Bank A                                    Bank A               Bank A




Preliminary                                                                    65                         Rev 0.8                     Nov 2001
EtronTech                                                                               2Mega x 32                            SDRAM                            EM638325

Figure 21. Random Row Read (Interleaving Banks)
                       (Burst Length=2, CAS# Latency=1)


                 T0    T 1 T2           T3      T4    T5       T6      T7       T8     T9      T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                           tCK1
        High
 CKE                               Begin Auto    Begin Auto      Begin Auto       Begin Auto    Begin Auto       Begin Auto   Begin Auto      Begin Auto    Begin Auto   Begin Auto
                                   Precharge     Precharge       Precharge        Precharge     Precharge        Precharge    Precharge       Precharge     Precharge    Precharge
                                    Bank B        Bank A          Bank B           Bank A        Bank B           Bank A       Bank B          Bank A        Bank B       Bank A


 CS#



RAS#



CAS#



 WE#


BS0,1


           RBu               RAu           RBv             RAv            RBw                 RAw       RBx            RAx              RBy           RAy          RBz          RAz
  A10


           RBu       CBu    RAu CAu        RBv CBv         RAv      CAv              CBw      RAw CAw RBx          CBx RAx CAx          RBy CBy       RAy CAy RBz           CBz RAz
A0~A9                                                                       RBw


                                        tRP          tRP                tRP            tRP           tRP            tRP              tRP           tRP            tRP        tRP
 DQM



   DQ                        Bu0      Bu1 Au0      Au1       Bv0 Bv1        Av0      Av1 Bw0 Bw1           Aw0      Aw1Bx0     Bx1         Ax0 Ax1 By0         By1 Ay0 Ay1           Bz0



          Activate      Activate        Activate      Activate          Activate       Activate       Activate        Activate        Activate     Activate      Activate      Activate
         Command       Command         Command       Command           Command        Command        Command         Command         Command      Command       Command       Command
          Bank B        Bank A          Bank B        Bank A            Bank B         Bank A         Bank B          Bank A          Bank B       Bank A        Bank B        Bank A
                   Read              Read          Read          Read               Read          Read          Read            Read            Read         Read          Read
                  Bank B            Bank A        Bank B        Bank A             Bank B        Bank A        Bank B          Bank A          Bank B       Bank A        Bank B
                 with Auto         with Auto     with Auto     with Auto          with Auto     with Auto     with Auto       with Auto       with Auto    with Auto     with Auto
                 Precharge         Precharge     Precharge     Precharge          Precharge     Precharge     Precharge       Precharge       Precharge    Precharge     Precharge




Preliminary                                                                                     66                                      Rev 0.8                               Nov 2001
EtronTech                                                                2Mega x 32                   SDRAM                               EM638325

Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)


          T0        T 1 T2     T3     T4    T5     T6    T7     T8       T9     T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                tCK2
 CKE



 CS#



RAS#



CAS#



 WE#



BS0,1


  A10         RAx            RBx                                                                                                RBw




A0~A9         RAx        RBx        CAx   CBx    CAy          CBy             CAz          CBz                                  RBw
                                                                                                                        tRP

 DQM
                      tRRD         tRCD

 DQ                                               Ax0   Bx0    Ay0 Ay1         By0 By1   Az0 Az1     Az2     Bz0 Bz1      Bz2



           Activate      Activate         Read           Read              Read              Read                Precharge
          Command       Command        Command         Command           Command           Command           Command Bank B
           Bank A        Bank B         Bank B Read     Bank B            Bank A            Bank B         (Precharge Temination)
                                     Read      Command                                                                         Activate
                                   Command      Bank A                                                                        Command
                                    Bank A                                                                                     Bank B




Preliminary                                                                     67                                 Rev 0.8                   Nov 2001
EtronTech                                                         2Mega x 32                    SDRAM                          EM638325

Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)


          T0     T 1 T2       T3      T4   T5      T6   T7   T8   T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                 tCK2

 CKE



 CS#



RAS#



CAS#



 WE#




BS0,1


  A10      RAx            RBx                                                                                        RBw




A0~A9         RAx          RBx CAx      CBx   CAy        CBy         CAz           CBz                                RBw

                                                                                                     tWR       tRP

 DQM

                 tRRD            tRCD
   DQ                                                                                             DBz2
                                    DAx0DBx0DAy0    DAy1 DBy0 DBy1   DAz0 DAz1 DAz2 DBz0 DBz1



           Activate      Activate       Write             Write     Write            Write            Precharge
          Command       Command      Command            Command   Command          Command         Command Bank B
           Bank A        Bank B       Bank B Write       Bank B    Bank A           Bank B      (Precharge Temination)
                                  Write     Command                                                                 Activate
                                Command       Bank A                                                   Write Data Command
                                 Bank A                                                                is masked     Bank B




Preliminary                                                             68                               Rev 0.8                  Nov 2001
EtronTech                                                         2Mega x 32                         SDRAM                 EM638325

Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)


          T0   T 1 T2     T3    T4     T5    T6     T7    T8    T9         T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                tCK1
 CKE



 CS#


RAS#



CAS#



 WE#



BS0,1


  A10            RAx                                           RAy                             RAz



                                                                     CAy
                RAx     CAx                                    RAy                               RAz CAz
A0~A9
                                                                                               tRP
                                                    tWR tRP                                             Precharge
                                                                                                      Termination of
                                                                                                      a Read Burst.
 DQM


   DQ                                                                                                                                  DAz6 DAz7
                       DAx0      DAx2 DAx3 DAx4
                               DAx1                                            Ay0   Ay1 Ay2         DAz0    DAz1 DAz2
                                                                                                                    DAz3   DAz4 DAz5




                 Activate                                               Read           Precharge       Write
                               Precharge Termination Precharge       Command           Command       Command
                Command          of a Write Burst.   Command
                 Bank A                                               Bank A            Bank A        Bank A
                               Write data is masked. Bank A
                          Write                                                                 Activate
                       Command                                 Activate
                                                             Command                           Command
                        Bank A                                                                  Bank A
                                                               Bank A




Preliminary                                                                 69                               Rev 0.8                     Nov 2001
EtronTech                                                             2Mega x 32                  SDRAM                       EM638325

Figure 24.2. Precharge Termination of a Burst
               (Burst Length=8 or Full Page, CAS# Latency=2)


               T0   T 1 T2     T3     T4    T5     T6     T7   T8     T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                    tCK2
 CKE High


 CS#


RAS#



CAS#



 WE#



BS0,1


            RAx                                             RAy                                     RAz
  A10


                                                            RAy        CAy                          RAz         CAz
            RAx       CAx
A0~A9
                                             tWR tRP                                        tRP                                           tRP

 DQM


   DQ                         DAx2 DAx3
                      DAx0 DAx1                                                   Ay0 Ay1    Ay2                              Az0   Az1       Az2




         Activate     Write                   Precharge    Activate     Read        Precharge       Activate     Read             Precharge
        Command     Command                   Command     Command     Command       Command        Command     Command            Command
         Bank A      Bank A                     Bank A     Bank A      Bank A        Bank A         Bank A      Bank A             Bank A
                                                                                                                  Precharge Termination
                            Precharge Termination                                                                 of a Read Burst
                              of a Write Burst.
                            Write data is masked.




Preliminary                                                                70                             Rev 0.8                               Nov 2001
EtronTech                                                                   2Mega x 32            SDRAM                           EM638325

Figure 24.3. Precharge Termination of a Burst
               (Burst Length=4, 8 or Full Page, CAS# Latency=3)

               T0     T 1 T2       T3     T4      T5    T6     T7      T8   T9   T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22


 CLK
                      tCK3
        High
 CKE


 CS#


RAS#



CAS#



 WE#



BS0,1


           RAx                                                      RAy                                              RAz
  A10


                                                                    RAy            CAy                               RAz
A0~A9      RAx                 CAx

                                          tWR            tRP                                               tRP
 DQM



   DQ                            DAx0 DAx1                                                      Ay0      Ay1   Ay2




           Activate              Write     Precharge            Activate           Read      Precharge            Activate Precharge Termination
          Command              Command     Command             Command           Command     Command             Command      of a Read Burst
           Bank A               Bank A      Bank A              Bank A            Bank A      Bank A              Bank A

                             Write Data
                             is masked         Precharge Termination
                                                  of a Write Burst




Preliminary                                                                      71                            Rev 0.8                             Nov 2001
EtronTech                                         2Mega x 32              SDRAM                             EM638325
86 Pin TSOP II Package Outline Drawing Information


 86                                                                  44




                                                                                                0.254
                                                                                 HE
                                                                          E
                                                                                                                    θ°

                                                                                                               L

                                                                                                               L1




 1                             D                                   43




                                                                              A1 A2




                                                                                                                                    C
                                                                                      A
                           e                                                               L                                   L1
                                            y
 S             B


      Symbol             Dimension in inch                         Dimension in mm
                    Min      Normal        Max               Min       Normal      Max
       A                                 0.047                                     
                                                                                    1.20
       A1          0.002      0.004        0.006              0.05       0.10       0.15
       A2          0.037      0.039        0.041              0.95         1        1.05
       B           0.007      0.008        0.009              0.17       0.2        0.23
       C                     0.005                                   0.127                           
       D            0.87      0.875         0.88             22.09      22.22      22.35
       E           0.395      0.400        0.405             10.03      10.16      10.29
        e                    0.0197                                   0.50                           
       HE          0.455           0.463        0.471        11.56              11.76              11.96
        L          0.016           0.020        0.024         0.40               0.50               0.60
       L1                         0.0315                                      0.80                    
       S                          0.024                                       0.61                    
        y                                     0.004                                                 0.10
        θ           0±                          8±          0±                                        8±

Notes :
1. Dimension D&E do not include interiead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension : mm




Preliminary                                             72                                Rev 0.8                   Nov 2001
EtronTech     2Mega x 32   SDRAM       EM638325




Preliminary     73           Rev 0.8      Nov 2001

								
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