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Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory July 5, 2004; Revised - June 25, 2005 B.Supmonchai Goals of This Chapter Quantification of Design Metrics of an inverter Static (or Steady-State) Behavior Dynamic (or Transient Response) Behavior Energy Efficiency Optimization of an inverter design Technology Scaling and its impact on the inverter metrics 2102-545 Digital ICs CMOS Inverter 2 B.Supmonchai Digital Gate Design Metrics: Recap Cost Complexity and Area Reliability and Robustness Static Behavior Noise Margin, Regenerative Property Performance Dynamic Behavior Speed (Delay) Energy Efficiency Energy and Power Consumption, Energy-Delay 2102-545 Digital ICs CMOS Inverter 3 B.Supmonchai Why CMOS Inverter? CMOS because it is the dominating technology of the era. High Packing Density Relatively Easy Process Inverter because it is the nucleus of all digital designs. Behavior of more intricate structures (logic gates, adders, etc.) can be almost completely derived by extrapolating the results obtained from the inverters. 2102-545 Digital ICs CMOS Inverter 4 B.Supmonchai CMOS Inverter: A First Glance V DD Driven by Output Of another gate => Fanin PMOS V in V out CL NMOS Collective Capacitances Of Wires and Gates => Fanout 2102-545 Digital ICs CMOS Inverter 5 B.Supmonchai CMOS Inverter: Physical View Recap N Well VDD VDD PMOS 2l PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND 2102-545 Digital ICs CMOS Inverter 6 B.Supmonchai Two CMOS Inverters: Physical View Share power and ground VDD Connect In Metal Abut Cells 2102-545 Digital ICs CMOS Inverter 7 B.Supmonchai CMOS Inverter Static Behavior V DD V DD Rp Vout Vout Rn Vin = VDD Vin = 0 State of Transistors ON: |VGT = VGS - VT| > |VT|, Ron OFF: |VGT = VGS - VT | > |VT|, Roff finite 2102-545 Digital ICs CMOS Inverter 8 B.Supmonchai CMOS Inverter Dynamic Behavior VDD VDD Rp Charge Discharge Vout Vout CL CL Rn Low to High High to Low Vin = 0 Vin = V DD Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn) 2102-545 Digital ICs CMOS Inverter 9 B.Supmonchai CMOS Properties Full rail-to-rail swing High noise margins Logic levels not dependent upon the relative device sizes => Ratioless Transistors can be minimum size Regenerative Property Low output impedance Large Fan-out (albeit with degraded performance) Typical output resistance in k range. 2102-545 Digital ICs CMOS Inverter 10 B.Supmonchai CMOS Properties (2) Extremely high input resistance (MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path between power and ground under steady-state (but there always exists a path with finite resistance between the output and either VDD or GND) no static power dissipation Propagation delay a function of load capacitance and resistance of transistors 2102-545 Digital ICs CMOS Inverter 11 B.Supmonchai NMOS Short Channel I-V Plot Recap X 10-4 2.5 VGS = 2.5 V 2 VGS = 2.0 V 1.5 VGS = 1.5 V 1 0.5 VGS = 1.0 V 0 0 0.5 1 1.5 2 2.5 VDS (V) NMOS transistor, 0.25 m, Ld = 0.25 m, W/L = 1.5, VDD = 2.5 V, VT = 0.4 V 2102-545 Digital ICs CMOS Inverter 12 B.Supmonchai PMOS Short Channel I-V Plot Recap All polarities of all voltages and currents are reversed VDS (V) -2 -1 0 0 VGS = -1.0 V -0.2 VGS = -1.5 V -0.4 VGS = -2.0 V -0.6 VGS = -2.5 V -0.8 -1 X 10-4 PMOS transistor, 0.25 m, Ld = 0.25 m, W/L = 1.5, VDD = 2.5 V, VT = -0.4 V 2102-545 Digital ICs CMOS Inverter 13 B.Supmonchai Transforming PMOS I-V Plot NMOS and PMOS VTC must be put into a common coordinate set of Vin, Vout, and IDn I Dn IDSp = -IDSn VGSn = Vin ; VGSp = Vin - VDD VDSn = Vout ; VDSp = Vout - VDD Vout Vin = 0 Vin = 0 Vin = 1.5 Vin = 1.5 VGSp = -1 Mirror around x-axis Horiz. shift over VDD VGSp = -2.5 Vin = VDD + VGSp Vout = VDD + VDSp IDn = -IDp 2102-545 Digital ICs CMOS Inverter 14 B.Supmonchai CMOS Inverter Load-Line Plot PMOS X 10-4 NMOS 2.5 Vin = 0 V Vin = 2.5 V 2 Vin = 0.5 V 1.5 Vin = 2.0 V Vin = 1.0 V 1 Vin = 1.5 V Vin = 1.5 V Vin = 1 V Vin = 2 V 0.5 Vin = 0.5 V Vin = 1.5 V Vin = 1.0 V Vin = 2.0 V Vin = 0.5 V 0 Vin = 2.5 V 0 0.5 1 1.5 2 2.5 Vin = 0 V Vout (V) CMOS 0.25 m, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5 V, VTn = 0.4 V, VTp = -0.4 V 2102-545 Digital ICs CMOS Inverter 15 B.Supmonchai CMOS Inverter VTC * VTC = Voltage-Transfer Characteristics NMOS off PMOS res 2.5 NMOS sat PMOS res 2 1.5 Vout (V) NMOS sat 1 PMOS sat NMOS res 0.5 PMOS sat NMOS res PMOS off 0 0 0.5 1 1.5 2 2.5 Vin (V) 2102-545 Digital ICs CMOS Inverter 16 B.Supmonchai Robustness of CMOS Inverter Precise Values of Switching Threshold, VM VM is defined as the point where Vin = Vout Noise Margins Piece-Wise Linear Approximation Maximization Process Variations Device Variations Technology Scaling 2102-545 Digital ICs CMOS Inverter 17 B.Supmonchai Switching Threshold At VM where Vin = Vout, both PMOS and NMOS transistors are in saturation (since VDS = VGS) VM rVDD/(1 + r) where r = kpVDSATp/knVDSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Goal: To set VM = VDD/2 (to maximize noise margins), so r 1 W Lp k n 'VDSAT,n VM VT ,n VDSAT,n /2 W Ln k p 'VDSAT, p VDD M VT , p VDSAT, p /2 V 2102-545 Digital ICs CMOS Inverter 18 B.Supmonchai Switch Threshold Example In our generic 0.25 micron CMOS process, using the process parameters from Table 3.2, at VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5) VT0(V) (V0.5) VDSAT(V) k’(A/V2) l(V-1) NMOS 0.43 0.4 0.63 115 x 10-6 0.06 PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1 (W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2) = x x = 3.5 (W/L)n -30 x 10-6 -1.0 (1.25 – 0.4 – 1.0/2) (W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25 V 2102-545 Digital ICs CMOS Inverter 19 B.Supmonchai Example: Simulated Results 1.8 1.7 1.6 1.5 1.4 V (V) 1.3 1.25 V M 1.2 1.1 1 0.9 r = 3.4 0.8 0 1 10 10 W p /W n Minimum Width-to-Length = 1.5 2102-545 Digital ICs CMOS Inverter 20 B.Supmonchai Observations I VM is relatively insensitive to variations in device ratio Small Variations of the ratio do not significantly disturb VTC. Common Industry Practice to set Wp smaller than the requirement. Increasing the width of the PMOS moves VM towards VDD Increasing the width of the NMOS moves VM toward GND 2102-545 Digital ICs CMOS Inverter 21 B.Supmonchai Noise Margins: Determining VIH and VIL By definition, VIH and VIL are where gain 3 dVout/dVin = -1 Gain g = Slope VOH = VDD NMH = VDD - VIH 2 NML = VIL - GND VM Approximating: 1 VIH = VM - VM /g Slope = g VIL = VM + (VDD - VM )/g VOL = GND So high gain in the 0 VIL VIL Vin VIHIH V transition region is A piece-wise linear approximation of VTC very desirable 2102-545 Digital ICs CMOS Inverter 22 B.Supmonchai CMOS Voltage Gain Vin Gain is a strong function of the 0 0.5 1 1.5 2 slopes of the currents in the 0 saturation region, for Vin = VM -2 -4 -6 -8 -10 -12 -14 -16 -18 Determined only by technology parameters, especially channel length modulation (l). Only designer influence through supply voltage and VM (transistor sizing). 2102-545 Digital ICs CMOS Inverter 23 B.Supmonchai Example: VTC and Noise Margin For a 0.25m, (W/L)p/(W/L)n = 3.4, (W/L)n = 1.5 (min size) VDD = 2.5V VM 1.25 V, g = -27.5 Real Value VIL = 1.2 V, VIH = 1.3 V VIL = 1.03 V, VIH = 1.45 V NML = NMH = 1.2 NML = 1.03, NMH = 1.05 Output resistance Sensitivity of gate output with respect to noise low-output = 2.4 k high-output = 3.3 k Preferably as low as possible 2102-545 Digital ICs CMOS Inverter 24 B.Supmonchai Observations II First-Order Analysis overestimates the gain Max. gain only 17 at VM VIL = 1.17V, VIH = 1.33V Piecewise Linear Approximation is too overly optimistic Major contributor to deviation from the true gain CMOS inverter is a poor analog amplifier! One of the major differences between analog and digital designs is that digital circuits operate in the regions of extreme nonlinearity. Well-defined and well-separated high and low signals 2102-545 Digital ICs CMOS Inverter 25 B.Supmonchai Impact of Process Variation on VTC 2.5 Good PMOS 2 Bad NMOS 1.5 Vout(V) 1 0.5 Bad PMOS Good NMOS 0 0 0.5 1 1.5 2 2.5 Vin(V) Process variations (mostly) cause a shift in the switching threshold 2102-545 Digital ICs CMOS Inverter 26 B.Supmonchai Scaling the Supply Voltage 2.5 0.2 2 0.15 1.5 Vout(V) Vout(V) 0.1 1 0.05 0.5 0 0 0 0.5 1 1.5 2 2.5 0 0.05 0.1 0.15 0.2 Vin(V) Gain=-1 Vin(V) Reducing VDD improves Gain… But it deteriorates for very low VDD Practical Lower Bound: VDDmin > 2 to 4 kt /q 2102-545 Digital ICs CMOS Inverter 27 B.Supmonchai Observations III Reducing the supply voltage has a positive impact on the energy dissipation … But is also detrimental to the delay of the gate DC Characteristic becomes increasingly sensitive to device variations once supply and intrinsic voltages become comparable Scaling the supply voltage = reducing the swing Reduce internal noise (e.g., crosstalk) More susceptible to external noise that do not scale 2102-545 Digital ICs CMOS Inverter 28 B.Supmonchai CMOS Inverter Dynamic Behavior Transient behavior of the gate is determined by the time it takes to charge and discharge the load capacitance, CL, through on-transistors Delay is a function of load capacitances and transistor on-resistances Getting CL as small as possible is crucial to the realization of high-performance CMOS circuits Transistor Capacitances Wire Capacitances Fanout Wire Resistances also become more important. 2102-545 Digital ICs CMOS Inverter 29 B.Supmonchai Computing the Capacitances VDD VDD Extrinsic M2 Cdb2 Cg4 M4 Cgd12 Vin Vout Vout2 Cdb1 Cw Cg3 M1 M3 Interconnect Intrinsic Fanout Fanout Vin Vout V Vin Simplified out Vout2 Model CL CL Simplified Model 2102-545 Digital ICs CMOS Inverter 30 B.Supmonchai Finding Cgd: The Miller Effect M1 and M2 are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor). Cgd1 Vout V Vout V Vin V 2Cgd1 V M1 M1 Vin “A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value” 2102-545 Digital ICs CMOS Inverter 31 B.Supmonchai Diffusion Capacitances: Cdb1 and Cdb2 We can simplify the diffusion capacitance calculations by using a Keq to linearize the nonlinear capacitor to the value of the junction capacitance under zero-bias Ceq = Keq Cj0 0.25 m high-to-low low-to-high Process Keqbp Keqsw Keqbp Keqsw NMOS 0.57 0.61 0.79 0.81 PMOS 0.79 0.86 0.59 0.7 2102-545 Digital ICs CMOS Inverter 32 B.Supmonchai Extrinsic Capacitances: Cg3 and Cg4 Simplification of the actual situation Assumes all the components of Cgate are between Vout and GND (or VDD) Assumes the channel capacitances of the loading gates are constant The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4. Cfan-out = Cgate(NMOS) + Cgate(PMOS) = (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox) 2102-545 Digital ICs CMOS Inverter 33 B.Supmonchai Example: Layout of Two Inverters VDD PMOS AD = Drain Area 1.125/0.25 PD = Drain Perimeter AS = Source Area PS = Source Perimeter In Out Metal1 Polysilicon l = 0.125 NMOS Minimum Drawn Length 0.375/0.25 GND 0.25 m W/L AD (m2) PD (m) AS (m2) PS (m) NMOS 0.375/0.25 0.3 1.875 0.3 1.875 PMOS 1.125/0.25 0.7 2.375 0.7 2.375 2102-545 Digital ICs CMOS Inverter 34 B.Supmonchai Example: Components of CL (0.25 m) Value (fF) Value (fF) C Term Expression HL LH Cgd1 2 Cgd0n Wn 0.23 0.23 Cgd2 2 Cgd0p Wp 0.61 0.61 Cdb1 KeqbpnADnCj + KeqswnPDnCjsw 0.66 0.90 Cdb2 KeqbppADpCj + KeqswpPDpCjsw 1.5 1.15 Cg3 (2 Cgd0n)Wn + CoxWnLn 0.76 0.76 Cg4 (2 Cgd0p)Wp + CoxWpLp 2.28 2.28 Cw from extraction 0.12 0.12 CL 6.1 6.0 2102-545 Digital ICs CMOS Inverter 35 B.Supmonchai Wiring Capacitance The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance with the scaling of technology. 2102-545 Digital ICs CMOS Inverter 36 B.Supmonchai Inverter Propagation Delay “Propagation delay is proportional to the time-constant of the network formed by the on-resistance and the load capacitance” VDD tp = f(Ron, CL) VDD Rp tpLH = 0.69 Reqp CL Charge Discharge tpHL = 0.69 Reqn CL Vout Vout CL t pHL t pLH CL tp Rn Low to High 2 High to Low Reqn Reqp Vin = 0 0.69C L Vin = V DD 2 To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal. 2102-545 Digital ICs CMOS Inverter 37 B.Supmonchai Inverter Transient Response (0.25 µm) Simulation Analysis 3 VDD= 2.5V 2.5 W/Ln = 1.5 2 W/Lp = 4.5 Vin, Vout(V) 1.5 tpLH Reqn= 13 k /1.5 1 0.5 Reqp= 31 k /4.5 0 tpHL -0.5 tpHL = 36 psec 0 50 100 150 200 250 tpLH = 29 psec t(psec) tp = (36+29)/2 tpHL = 39.9 psec and tpLH = 31.7 psec = 32.5 psec Analysis results is too optimistic ~ 10% better 2102-545 Digital ICs CMOS Inverter 38 B.Supmonchai Inverter Propagation Delay, Revisited To see how a designer can optimize the delay of a gate, we have to expand Req in the delay equation. 5.5 5 tpHL = 0.69 Reqn CL tp(normalized) 4.5 = 0.69(3CVDD)/(4IDSATn) 4 3.5 CL t pHL 0.52 3 2.5 W Ln knVDSATn 2 1.5 1 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 VDD(V) 2102-545 Digital ICs CMOS Inverter 39 B.Supmonchai Minimizing Propagation Delay Reduce CL Keep the drain diffusion as small as possible Increase W/L ratio of the transistor Most powerful and effective way Watch out for self-loading! When the intrinsic capacitance dominates Increase VDD Trade off energy efficiency for performance Very minimal improvement above a certain level Reliability concerns enforce a firm upper bound on VDD 2102-545 Digital ICs CMOS Inverter 40 B.Supmonchai PMOS-to-NMOS Ratio So far PMOS and NMOS have been sized such that their Req’s match (ratio of 3 to 3.5) symmetrical VTC equal high-to-low and low-to-high propagation delays If speed is the only concern, reduce the width of the PMOS device! widening the PMOS degrades the tpHL due to larger parasitic capacitance CW = (W/L)p/(W/L)n opt r C C 1 dn 2 Cgn 2 r = Reqp/Reqn resistance ratio of identically-sized PMOS and NMOS 2102-545 Digital ICs CMOS Inverter 41 B.Supmonchai PMOS-to-NMOS Ratio Effects 50 tpLH tpHL 45 • of 2.4 (= 31 k/13 k) gives symmetrical response tp(psec) • opt ~ 1.6 - 1.9 40 tp 35 Analytic Simulated 30 2.4 1 1.5 2 2.5 3 3.5 4 4.5 5 • When wire capacitance is negligible (Cdn1+Cgn2 >> CW), opt = r • If wire capacitance dominates then larger value of must be used 2102-545 Digital ICs CMOS Inverter 42 B.Supmonchai Device Sizing for Performance Divide capacitive load, CL, into Cint : intrinsic - diffusion and Miller effect Cext : extrinsic - wiring and fanout tp = 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint) where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the gate Widening both PMOS and NMOS by a factor S reduces Req by an identical factor (Req = Rref/S), but raises the intrinsic capacitance by the same factor (Cint = SCiref) tp = 0.69 Rref Ciref (1 + Cext/(SCiref)) = tp0(1 + Cext/(SCiref)) 2102-545 Digital ICs CMOS Inverter 43 B.Supmonchai Observation IV Intrinsic Delay of the inverter tp0 is independent of the sizing of the gate; • tp0 can be determined purely by technology and inverter layout • With no load the increased drive strength of the gate is totally offset by the increased capacitance Any S sufficiently larger than (Cext/Cint) would yield a much better performance gain with a substantial area increase 2102-545 Digital ICs CMOS Inverter 44 B.Supmonchai Sizing Impacts on Delay The majority of the improvement for a fixed load 38 is already obtained for S = 5. 36 Sizing factors larger than 10 34 barely yield any extra gain (and 32 tp(psec) 30 cost significantly more area). 28 26 24 22 20 1 3 5 7 9 11 13 15 S self-loading effect (intrinsic capacitance dominates) 2102-545 Digital ICs CMOS Inverter 45 B.Supmonchai Impact of Fanout on Delay Extrinsic capacitance, Cext, is a function of the fanout of the gate the larger the fanout, the larger the external load. First determine the input loading effect of the inverter. Both Cg and Cint are proportional to the gate sizing, so Cint = Cg is independent of gate sizing and tp = tp0 (1 + Cext/ Cg) = tp0 (1 + f /) The delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan-out f f = Cext/Cg 2102-545 Digital ICs CMOS Inverter 46 B.Supmonchai Inverter Chain Goal: to minimize the delay through an inverter chain In Out 1 2 N Cg,1 CL The delay of the j-th inverter stage is tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ ) Overall Delay: tp = tp,j = tp0 (1 + Cg,j+1/(Cg,j)) If CL is given How should the inverters be sized? How many stages are needed to minimize the delay? 2102-545 Digital ICs CMOS Inverter 47 B.Supmonchai Sizing the Inverters in the Chain The optimum size of each inverter is the geometric mean of its neighbors – meaning that if each inverter is sized up by the same factor f wrt the preceding gate, it will have the same effective fan-out and the same delay f N CL Cg,1 N F where F represents the overall effective fan-out of the circuit (F = CL/Cg,1) The minimum delay through the inverter chain is t p Nt p 0 1 N F / The relationship between tp and F is linear for one inverter, square root for two, etc. 2102-545 Digital ICs CMOS Inverter 48 B.Supmonchai Example: Inverter Chain Sizing In Out 1 f=2 f2 = 4 Cg,1 CL = 8 Cg,1 CL/Cg,1 has to be evenly distributed over N = 3 inverters CL/Cg,1 = 8/1 3 f = 8 = 2 2102-545 Digital ICs CMOS Inverter 49 B.Supmonchai Determining N: Optimal Number of Inverters What is the optimal value for N given F (=fN) ? If the number of stages is too large, the intrinsic delay of the stages becomes dominate If the number of stages is too small, the effective fan-out of each stage becomes dominate The optimum N is found by differentiating the minimum delay expression divided by the number of stages and setting the result to 0, giving N N + F - ( F lnF)/N = 0 For = 0 (ignoring self-loading) N = ln (F) and the effective-fan out becomes f = e = 2.71828 For = 1 (the typical case) the optimum effective fan-out (tapering factor) turns out to be close to 3.6 2102-545 Digital ICs CMOS Inverter 50 B.Supmonchai Optimum Effective Fan-Out 5 7 6 4.5 Normalized Delay 5 4 4 Fopt 3 3.5 2 3 1 2.5 0 0 0.5 1 1.5 2 2.5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 f Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). Common practice to use f = 4 (for = 1) But too many stages has a substantial negative impact on delay 2102-545 Digital ICs CMOS Inverter 51 B.Supmonchai Example: Inverter (Buffer) Staging 1 N f tp Cg,1 = 1 CL = 64 Cg,1 1 64 65 1 8 Cg,1 = 1 CL = 64 Cg,1 2 8 18 1 4 16 Cg,1 = 1 CL = 64 Cg,1 3 4 15 1 2.8 8 22.6 4 2.8 15.3 Cg,1 = 1 CL = 64 Cg,1 2102-545 Digital ICs CMOS Inverter 52 B.Supmonchai Impact of Buffer Staging for Large CL Two Opt. F Unbuffered Stage Inverter ( = 1) Chain Chain 10 11 8.3 8.3 100 101 22 16.5 1,000 1001 65 24.8 10,000 10,001 202 33.1 Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads. 2102-545 Digital ICs CMOS Inverter 53 B.Supmonchai Input Signal Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CL and impacts propagation delay. t = input signal slope 54 s 52 tp increases linearly with 50 increasing input slope, ts, 48 tp(psec) once ts > tp 46 44 ts is due to the limited 42 driving capability of the 40 preceding gate 38 36 0 20 40 60 80 tS(psec) for a minimum-size inverter with a fan-out of a single gate 2102-545 Digital ICs CMOS Inverter 54 B.Supmonchai Design Challenge A gate is never designed in isolation: its performance is affected by both the fan-out and the driving strength of the gate(s) feeding its inputs. (Revised tp expression) tip = tistep + ti-1step ( 0.25) Keep signal rise times smaller than or equal to the gate propagation delays. good for performance good for power consumption Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering. 2102-545 Digital ICs CMOS Inverter 55 B.Supmonchai Delay with Long Interconnect When gates are farther apart, wire capacitance and resis- tance can no longer be ignored. (rw, cw, L) Vin Vout cint cfan tp = 0.69RdrCint + (0.69Rdr+0.38Rw)Cw + 0.69(Rdr+Rw)Cfan where Rdr = (Reqn + Reqp)/2 tp = 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2 Wire delay rapidly becomes the dominant factor (due to the quadratic term) in the delay budget for longer wires. 2102-545 Digital ICs CMOS Inverter 56 B.Supmonchai Where Does Power Go? Static Power Consumption Ideally zero for static CMOS but in the real world.. Leakage Current Loss Diodes and Transistors constantly losing charge Dynamic Power Consumption Charging/Discharging Capacitances Major Source of Power Dissipation in CMOS Circuits Direct-Path Current Loss Short circuit between Power Rail during Switching 2102-545 Digital ICs CMOS Inverter 57 B.Supmonchai Dynamic Power Consumption VDD iVDD(t) Vin Vout CL Energy Supplied/Cycle = i VDD (t)VDD dt = CL * VDD2 0 Energy Stored/Cycle = i VDD (t)v out (t)dt = CL * VDD2 / 2 0 Pdyn = Energy/cycle * fclk = CL * VDD2 * fclk CMOS Inverter 58 2102-545 Digital ICs B.Supmonchai Switching Activity Power dissipation does not depend on the size of the devices but depends on how often the circuit is switched. Switching Activity frequency of energy-consuming transition = f 01 Clock Pdyn = CL * VDD2 * f 01 = CL * VDD2 * P01 * fclk Gate output = Ceff * VDD2 * fclk P01 = 0.25, f01 = fclk / 4 Effective Capacitance Ceff = Average Capacitance Switched per clock cycle 2102-545 Digital ICs CMOS Inverter 59 B.Supmonchai Lowering Dynamic Power Lowering Physical Capacitance Quadratic Effect Capacitance: Supply Voltage: Function of fan-out, wire Has been dropping with length, transistor sizes successive generations Pdyn = CL VDD2 P01 f Activity factor: Clock frequency: How often, on average, Increasing… do gates switch? Reduction can be obtained only at Logic and Architectural Abstraction Levels 2102-545 Digital ICs CMOS Inverter 61 B.Supmonchai Short Circuit Power Consumption VDD tsc Isc Vin Vout CL Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting (active). 2102-545 Digital ICs CMOS Inverter 62 B.Supmonchai Short Circuit Currents Determinates Esc = tsc VDD Ipeak P01 Psc = tsc VDD Ipeak f01 tsc = Duration of the slope of the input signal Ipeak determined by the saturation current of the PMOS and NMOS transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes a function of CL 2102-545 Digital ICs CMOS Inverter 63 B.Supmonchai Impact of CL on Psc VDD VDD Isc 0 Isc Imax Vin Vout Vin Vout CL CL Large capacitive load Small capacitive load Output fall time significantly Output fall time substantially larger than input rise time. smaller than input rise time. 2102-545 Digital ICs CMOS Inverter 64 B.Supmonchai Ipeak as a Function of CL x 10-4 2.5 When load capacitance CL = 20 fF is small, Ipeak is large. 2 1.5 Short circuit dissipation is minimized by CL = 100 fF 1 matching the rise/fall 0.5 CL = 500 fF times of the input and output signals - slope 0 engineering. 0 2 4 6 -0.5 x 10-10 time (sec) 500 psec input slope 2102-545 Digital ICs CMOS Inverter 65 B.Supmonchai Psc as a Function of Rise/Fall Times 8 VDD= 3.3 V When load capacitance 7 is small (tsin/tsout > 2 for 6 VDD > 2V) the power is 5 dominated by Psc 4 VDD = 2.5 V 3 2 If VDD < VTn + |VTp| then VDD = 1.5V 1 Psc is eliminated since 0 both devices are never 0 1 2 3 4 5 on at the same time. tsin/tsout W/Lp = 1.125 m/0.25 m normalized wrt zero input W/Ln = 0.375 m/0.25 m rise-time dissipation CL = 30 fF 2102-545 Digital ICs CMOS Inverter 66 B.Supmonchai Static (Leakage) Power Consumption VDD VDD Pstat= VDD Istat Vout = VDD dominant Drain junction factor. leakage Gate leakage Sub-threshold current All leakages increase exponentially with temperature Junction leakage doubles every 9C Sub-threshold current becomes more concern in vDSM The closer the threshold voltage to zero, the larger the leakage current at VGS = 0V (when NMOS off) 2102-545 Digital ICs CMOS Inverter 67 B.Supmonchai Leakage as a Function of VT Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make sub-threshold conduction a dominant component of power dissipation. 1.E-02 An 90mV/decade VT 1.E-04 roll-off - so each 1.E-06 255mV increase in VT gives 3 orders of ID (A) 1.E-08 magnitude reduction in leakage (but 1.E-10 VT=0.4V VT=0.1V adversely affects performance) 1.E-12 0 0.2 0.4 0.6 0.8 1 VGS (V) 2102-545 Digital ICs CMOS Inverter 68 B.Supmonchai TSMC Processes Leakage and VT From MPR, June 2000, pp. 19 – Performance of various TSMC processes (G generic, LP low power, ULP ultra low power, HS high speed) CL018 CL018 CL018 CL018 CL015 CL013 G LP ULP HS HS HS Vdd 1.8 V 1.8 V 1.8 V 2V 1.5 V 1.2 V Tox (effective) 42 Å 42 Å 42 Å 42 Å 29 Å 24 Å Lgate 0.16 m 0.16 m 0.18 m 0.13 m 0.11 m 0.08 m IDSat (n/p) 600/260 500/180 320/130 780/360 860/370 920/400 (A/m) Ioff (leakage) 20 1.60 0.15 300 1,800 13,000 (A/m) VTn 0.42 V 0.63 V 0.73 V 0.40 V 0.29 V 0.25 V FET Perf. 30 22 14 43 52 80 (GHz) 2102-545 Digital ICs CMOS Inverter 69 B.Supmonchai Exponential Increase in Leakages 10000 Leakage currents double every 10 degree increase in temperature 0.10 m 1000 0.13 m Ileak age(nA/m) 0.18 m 100 0.25 m 10 1 30 40 50 60 70 80 90 100 110 Temperature (C) The Leakage Power is six orders of magnitude smaller than the dynamic power (at room temperature) 2102-545 Digital ICs CMOS Inverter 70 B.Supmonchai Energy and Power Equations E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD IleakageTclock f01 = P01 * fclock P = CL VDD2 f01 + tsc VDD Ipeak f01 + VDD Ileakage Dynamic power Short-circuit power Leakage power (~90% today and (~8% today and (~2% today and decreasing decreasing absolutely) increasing) relatively) 2102-545 Digital ICs CMOS Inverter 71 B.Supmonchai Sizing for Minimum Energy In Out Cext Cg1 1 f Goal: Minimize Energy of the whole circuit Design parameters: f and VDD tp tpref of circuit with f = 1 and VDD = Vref Overall Effective Fan-out Intrinsic Delay of the inverter F = Cext/Cg1 tp0 ~ VDDt/(VDDt - VTE) f F t p t p 0 1 1 f 2102-545 Digital ICs CMOS Inverter 72 B.Supmonchai Sizing for Minimum Energy II Performance Constraint (=1) F F f 2 f 2 tp tp0 f VDD Vref VTE f 1 t pref t p 0ref 3 F Vref VDD VTE 3 F Energy for single Transition E VDDCg1 1 1 f F 2 E V 2 2 2 f F DD V 4 F E ref ref 2102-545 Digital ICs CMOS Inverter 73 B.Supmonchai Sizing for Minimum Energy III 4 1.5 3.5 F=1 3 2 1 2.5 VDD (V) E/Eref 2 5 1.5 0.5 10 1 0.5 20 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 f f Optimum sizing occurs at fopt = F Increasing device sizes beyond fopt increase self-loading factor Deteriorate performance and require increase in supply voltage 2102-545 Digital ICs CMOS Inverter 74 B.Supmonchai Observation V Device sizing, combined with supply voltage reduction, is very effective in reducing the energy consumption For F = 1, minimum size device is the most effective For network with large effective fan-out (F >> 1), a large reduction factor of almost 10 can be obtained. Oversizing transistors beyond the optimal value results in a hefty increase of energy Unfortunately, a common approach in many today’s design Optimal sizing factor for energy is smaller than the one for performance (delay), especially for large F For a fan-out of 20, fopt(energy) = 3.53, fopt(delay) = 4.47 2102-545 Digital ICs CMOS Inverter 75 B.Supmonchai Power-Delay and Energy-Delay Product Power-delay product (PDP) = Pav * tp = (CLVDD2)/2 PDP is the average energy consumed per switching event (Watts * sec = Joule) Lower power design could simply be a slower design Energy-delay product (EDP) = PDP * tp = Pav * tp2 EDP is the average energy consumed multiplied by the computation time required Takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption) 2102-545 Digital ICs CMOS Inverter 76 B.Supmonchai Energy-Delay Plot 0.25 micron 15 Energy-D el ay ( normalized) CLVDD 2 3 EDP Energy-Delay 2VDD VTE 10 Where VTE = VT+VDSAT/2 5 3 Energy Delay VDDopt VTE 2 0 1.1 V 0.5 1 1.5 2 2.5 VTE ≈ (VTn +| VTp |)/2 = 0.8 V Vdd (V) VTn = 0.43 V, VDSATn = 0.63 V, VTEn = 0.74 V VDDopt = (3/2)*0.8 = 1.2 V VTp = -0.4 V, VDSATp = -1 V, VTEp = -0.9 V 2102-545 Digital ICs CMOS Inverter 77 B.Supmonchai Observation VI Voltage Dependence of the EDP Higher Supply Voltages reduce delay, but harm the energy. Vice Versa for low voltages VDDopt simultaneously optimizes performance (delay) and energy For submicron technologies with VT in the range of 0.5 V, VDDopt ~ 1V. VDDopt does not necessarily represent the optimum voltage for a given design problem Goal of the design (speed or power) determinates the supply voltage 2102-545 Digital ICs CMOS Inverter 78 B.Supmonchai Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price per transistor has to be reduced But also want to be faster, smaller, lower power 2102-545 Digital ICs CMOS Inverter 79 B.Supmonchai Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 2-3 years 2102-545 Digital ICs CMOS Inverter 80 B.Supmonchai Technology Evolution (ITRS2000) International Technology Roadmap for Semiconductors (ITRS) (http://public.itrs.net) Year of Introduction 1999 2000 2001 2004 2008 2011 2014 Technology node 180 130 90 60 40 30 [nm] Supply [V] 1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6 Wiring levels 6-7 6-7 7 8 9 9-10 10 Max frequency 14.9 1.2 1.6-1.4 2.1-1.6 3.5-2 7.1-2.5 11-3 [GHz],Local-Global -3.6 Max P power [W] 90 106 130 160 171 177 186 Bat. power [W] 1.4 1.7 2.0 2.4 2.1 2.3 2.5 Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm 2102-545 Digital ICs CMOS Inverter 81 B.Supmonchai Technology Evolution (1999) 2102-545 Digital ICs CMOS Inverter 82 B.Supmonchai Technology Scaling Models Full Scaling (Constant Electrical Field) Ideal model - dimensions and voltage scale together by the same factor S Fixed Voltage Scaling Most common until recently Only dimensions scale, voltages remain constant General Scaling Most realistic for todays situation Voltages and dimensions scale with different factors 2102-545 Digital ICs CMOS Inverter 83 B.Supmonchai Scaling Long Channel Devices 2102-545 Digital ICs CMOS Inverter 84 B.Supmonchai Scaling Short Channel Devices 2102-545 Digital ICs CMOS Inverter 85 B.Supmonchai Scaling Wire Capacitances S = Technology Scaling, U = Voltage Scaling, SL = Wire-length Scaling c = impact of fringing and interwire capacitance Parameter Relation General Scaling Wire Capacitance WL/t c/SL Wire Delay RonCint c/SL Wire Energy CmV2 c/SLU2 Wire Delay/Intrinsic cS/SL Delay Wire Energy/ Intrinsic cS/SL Energy 2102-545 Digital ICs CMOS Inverter 86 B.Supmonchai Power Density vs. Scaling Factor Power density increase approximately with S2 1000 In correspondance Power Density (mW/mm) 2 with fixed-voltage scaling 100 Recent Trend is more in line with Full-scaling 10 Constant power density Accelerated VDD 11 10 Scaling Factork scaling and more ?j ?i normalized by 4 m design rule attention to power- reducing design techniques 2102-545 Digital ICs CMOS Inverter 87 B.Supmonchai Evolution of Wire Delay and Gate Delay How the ratio of wire over intrinsic contributions will actually evolve is debatable 2102-545 Digital ICs CMOS Inverter 88 B.Supmonchai Looking into the Future… (Year 2010) Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 active Power 2102-545 Digital ICs CMOS Inverter 89 B.Supmonchai Some Interesting Questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation 2102-545 Digital ICs CMOS Inverter 90