A Galois Theory of Quantum Error Correcting Codes

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A Galois Theory of Quantum Error Correcting Codes Powered By Docstoc
					  Arithmetic IV
    CPSC 321


Andreas Klappenecker
Any Questions?
Today’s Menu

   Division
   Floating Point Numbers
                                                                                       Start




Recall: Multiplier                                            Product0 = 1             1. Test     Product0 = 0
                                                                                      Product0




                                           1a. Add multiplicand to the left half of
                                            the product and place the result in
       Multiplicand                         the left half of the Product register

                32 bits


                                                                   2. Shift the Product register right 1 bit
  32-bit ALU



                          Shift right   Control                                                    No: < 32 repetitions
               Product                                                         32nd repetition?
                               Write     test
               64 bits
                                                                                          Yes: 32 repetitions


                                                                                       Done
The Booth Multiplier
              Let’s kick it up a
                   notch!
Booth Multiplication

Current and previous bit

00: middle of run of 0s, no action
01: end of a run of 1s, add multiplicand
10: beginning of a run of 1s, subtract mcnd
11: middle of string of 1s, no action
Negative Numbers
     00102 x 11012 =   1111   10102
0)   Mcnd 0010 Prod    0000   1101,0
1)   Mcnd 0010 Prod    1110   1101,0   sub
1)   Mcnd 0010 Prod    1111   0110,1   >>
2)   Mcnd 0010 Prod    0001   0110,1   add
2)   Mcnd 0010 Prod    0000   1011,0   >>
3)   Mcnd 0010 Prod    1110   1011,0   sub
3)   Mcnd 0010 Prod    1111   0101,1   >>
4)   Mcnd 0010 Prod    1111   0101,1   nop
4)   Mcnd 0010 Prod    1111   1010,1   >>
Exercise

•    Work through some examples
1.   Grade school algorithms
2.   Booth multiplication
•    Read Chapter 4
•    Really!
MIPS Assembly Language

Multiplication of two 32 bit operands

          x          =   high      low


mult $a1, $s1      result is stored in
mfhi $v0           special registers
mflo $v1           high = 32 MSBs
                   low = 32 LSBs
MIPS Assembly Language

Integer division: divide a by b
              a=qb+r
  quotient q = floor(a/b), remainder r = a % b

     a      /    b      =     r         q

div $a0, $a1
mflo $v0        # quotient
mfhi $v1        # remainder
Exponentiation

Suppose you want to raise an integer b to
the nth power:
          (...((b*b)*b)...*b) = bn
Way too slow for large n!

Use square and multiply algorithm.
Square and Multiply

               x                     if n=1

Power(x,n) =   Power(x2,n/2)         if n even
               x*Power(x2,(n-1)/2)   if n odd



          x6= (x2)3=x2 (x2)2
Division
Recall Decimal Division

 Grammar school algorithm
 93:7= 13
-7
 23
-21 (trial multiplication, 3*7 works, 4*7 doesn’t)
  2
Binary division

• Dividend = Quotient x Divisor + Remainder

• See how big a number can be subtracted

• Create a quotient bit (0 or 1) in each step

• Binary division is simpler than decimal division
Binary Division

00000111: 0010 = 11
  -00100
    0011
   -0010
    0001

           7 = 3x2 + 1
Division Hardware (Version 1)
rem = rem - div
if rem < 0 then
  // divisor too big
  rem = rem + div
  quo <<= 1
  LSB(quo) = 0
else
  // can divide
  quo <<= 1
  LSB(quo) = 1
fi
div >>= 1
repeat unless done
iteration Step                       Quot   Divisor     Remainder
         initial step
   0                                 0000   0010 0000   0000 0111
         rem -= div
   1     rem<0 =>+div, Q<<=1, Q0=0
                                     0000   0010 0000   1110 0111
                                     0000   0010 0000   0000 0111
         div >>= 1
                                     0000   0001 0000   0000 0111
         rem -= div
   2     rem<0 =>+div, Q<<=1, Q0=0
                                     0000   0001 0000   1111 0111
                                     0000   0001 0000   0000 0111
         div >>= 1
                                     0000   0000 1000   0000 0111

   3     rem -= div                  0000   0000 1000   1111 1111
         rem<0 =>+div, Q<<=1, Q0=0   0000   0000 1000   0000 0111
         div >>= 1                          0000 0100   0000 0111
                                     0000
         rem -= div
   4     rem<0 => Q<<=1, Q0=1
                                     0001   0000 0100   0000 0011
                                     0001   0000 0100   0000 0011
         div >>= 1
                                     0001   0000 0010   0000 0011
         rem -= div
   5     rem<0 => Q<<=1, Q0=1
                                     0001   0000 0010   0000 0001
                                     0011   0000 0010   0000 0001
         div >>= 1
                                     0011   0000 0001   0000 0001
• Half of the bits in divisor always 0
  • Half of adder and divisor register is wasted
• Instead of shifting divisor to the right,
  shift remainder to the left
• Shift left first to save one iteration
Division hardware (Version 2)




 ALU and divisor registers are reduced, remainder shifted left
                                   Start: Place Dividend in Remainder

                                   1. Shift the Remainder register left 1 bit.

                       2. Subtract the Divisor register from the
                       left half of the Remainder register, & place the
                       result in the left half of the Remainder register.

                      Remainder > 0          Test          Remainder < 0
                                           Remainder

3a. Shift the         3b. Restore the original value by adding the Divisor
Quotient register     register to the left half of the Remainder register,
to the left setting   &place the sum in the left half of the Remainder
the new rightmost     register. Also shift the Quotient register to the left,
 bit to 1.            setting the new least significant bit to 0.


                            nth           No: < n repetitions
                        repetition?
                                   Yes: n repetitions (n = 4 here)
                           Done
  Observations (Divide Version 2)

• Eliminate quotient register => combine with remainder
  register
• Start by shifting the remainder left, as before.
• After that, the loop will contain only two steps
 (because remainder register shifts both remainder and quotient)
• Remainder will now be shifted left one time too many.
• Thus, a final correction step must shift back only the
  remainder in the left half of the register
Version 3
rem <<= 1
rem -= (div >> 32)
if rem < 0 then
 rem += (div >> 32)
 rem <<= 1
 LSB(rem) = 0
else
 rem <<= 1
 LSB(rem) = 1
fi
repeat unless done
Correct remainder
Floating Point Numbers
 IEEE 754 Floating Point Representation

• Float – 1 sign bit, 8 exponent bits, 23
  bits for significand.
 seeeeeeeefffffffffffffffffffffff
           value = (-1)s x F x 2E-127
  with F= 1 + .ffffffff .... fff

• Double – 1 sign bit, 11 exponent bits, 52
  bits for significand
Floating Point Representation:
double

• 1 bit sign, 11 bits for exponent, 52 bits
  for significand
• seeeeeeeeeeeffffffffffffffffffff
  ffffffffffffffffffffffffffffffff

Range of float: 2.0 x 10-38 … 2.0 x 1038
Range of double: 2.0 x 10-308 … 2.0 x 10308
Integer and Floating Point Arithmetic


                                  integer
                                   ALU          data
                       integer                 memory
                       register
     P   instruction     file
     C     memory                  integer
                         HI       multiplier
                         LO

                                    flt pt
                                   adder
                         flt pt
                       register
                          file
                                    flt pt
                                  multiplier
Floating Point Registers in MIPS

• $f0 - $f3 function-returned values
• $f4 - $f11 temporary values
• $f12 - $f15 function arguments
• $f16 - $f19 temporary values
• $f20 - $f31 saved values
Interpretation: 32 registers of 32 bits or
  16 registers of 64 bits (even indices)
Floating Point in MIPS
      .data
Pi:   .double     3.14159
Rad: .double      12.34567
      .text
main: l.d   $f0, Pi           #   $f0 = Pi; load double
      l.d   $f4, Rad          #   $f4 = radius
      mul.d $f12, $f4, $f4    #   $f12 = radius squared
      mul.d $f12, $f12, $f0   #   multiply by Pi
      li $v0, 3               #   print double $f12
      syscall                 #   (= print the area)
      li $v0, 10              #
      syscall                 #   exit
Conclusion

• We learned how to divide
• Make sure that you work through some
  examples
• Read the section on floating point addition
  and multiplication in Chapter 4
  (What are the challenges here?)
• To probe further:
  Knuth’s “Art of Computer Programming”
  contains numerous MIX assembly language
  programs; you can get involved into the
  translation to MMIX.

				
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